blob: ceeead34349c58f5425faca9876f9660a9417f37 [file] [log] [blame]
Peng Fanf77d4412018-10-18 14:28:30 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2018 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070011#include <malloc.h>
Peng Fan99ac6c72023-04-28 12:08:09 +080012#include <firmware/imx/sci/sci.h>
Peng Fanf77d4412018-10-18 14:28:30 +020013#include <asm/arch/clock.h>
14#include <dt-bindings/clock/imx8qxp-clock.h>
15#include <dt-bindings/soc/imx_rsrc.h>
16#include <misc.h>
17
Peng Fan98c63a72019-03-05 02:32:33 +000018#include "clk-imx8.h"
Peng Fanf77d4412018-10-18 14:28:30 +020019
Peng Fan98c63a72019-03-05 02:32:33 +000020__weak ulong imx8_clk_get_rate(struct clk *clk)
Peng Fanf77d4412018-10-18 14:28:30 +020021{
Peng Fanf77d4412018-10-18 14:28:30 +020022 return 0;
23}
24
Peng Fan98c63a72019-03-05 02:32:33 +000025__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
26{
27 return 0;
28}
29
30__weak int __imx8_clk_enable(struct clk *clk, bool enable)
31{
Simon Glass9042bf62021-03-25 10:26:08 +130032 return -EINVAL;
Peng Fan98c63a72019-03-05 02:32:33 +000033}
34
Peng Fanf77d4412018-10-18 14:28:30 +020035static int imx8_clk_disable(struct clk *clk)
36{
37 return __imx8_clk_enable(clk, 0);
38}
39
40static int imx8_clk_enable(struct clk *clk)
41{
42 return __imx8_clk_enable(clk, 1);
43}
44
Simon Glass8dd86202023-02-05 15:36:26 -070045#if IS_ENABLED(CONFIG_CMD_CLK)
Peng Fanf77d4412018-10-18 14:28:30 +020046int soc_clk_dump(void)
47{
48 struct udevice *dev;
49 struct clk clk;
50 unsigned long rate;
51 int i, ret;
52
53 ret = uclass_get_device_by_driver(UCLASS_CLK,
Simon Glass65e25be2020-12-28 20:34:56 -070054 DM_DRIVER_GET(imx8_clk), &dev);
Peng Fanf77d4412018-10-18 14:28:30 +020055 if (ret)
56 return ret;
57
58 printf("Clk\t\tHz\n");
59
Peng Fan98c63a72019-03-05 02:32:33 +000060 for (i = 0; i < num_clks; i++) {
Peng Fanf77d4412018-10-18 14:28:30 +020061 clk.id = imx8_clk_names[i].id;
62 ret = clk_request(dev, &clk);
63 if (ret < 0) {
64 debug("%s clk_request() failed: %d\n", __func__, ret);
65 continue;
66 }
67
68 ret = clk_get_rate(&clk);
69 rate = ret;
70
71 clk_free(&clk);
72
Simon Glass9042bf62021-03-25 10:26:08 +130073 if (ret == -EINVAL) {
Peng Fanf77d4412018-10-18 14:28:30 +020074 printf("clk ID %lu not supported yet\n",
75 imx8_clk_names[i].id);
76 continue;
77 }
78 if (ret < 0) {
79 printf("%s %lu: get_rate err: %d\n",
80 __func__, imx8_clk_names[i].id, ret);
81 continue;
82 }
83
84 printf("%s(%3lu):\t%lu\n",
85 imx8_clk_names[i].name, imx8_clk_names[i].id, rate);
86 }
87
88 return 0;
89}
90#endif
91
92static struct clk_ops imx8_clk_ops = {
93 .set_rate = imx8_clk_set_rate,
94 .get_rate = imx8_clk_get_rate,
95 .enable = imx8_clk_enable,
96 .disable = imx8_clk_disable,
97};
98
99static int imx8_clk_probe(struct udevice *dev)
100{
101 return 0;
102}
103
104static const struct udevice_id imx8_clk_ids[] = {
105 { .compatible = "fsl,imx8qxp-clk" },
Peng Fane45efe92019-03-05 02:32:35 +0000106 { .compatible = "fsl,imx8qm-clk" },
Peng Fanf77d4412018-10-18 14:28:30 +0200107 { },
108};
109
110U_BOOT_DRIVER(imx8_clk) = {
111 .name = "clk_imx8",
112 .id = UCLASS_CLK,
113 .of_match = imx8_clk_ids,
114 .ops = &imx8_clk_ops,
115 .probe = imx8_clk_probe,
116 .flags = DM_FLAG_PRE_RELOC,
117};