blob: 27e7dc483276e71abfa72d4eb600905b717e14fc [file] [log] [blame]
Mario Sixc0a2b082018-10-04 09:00:54 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
5 */
6
7#include <common.h>
8#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Mario Sixc0a2b082018-10-04 09:00:54 +020010#include <dm/lists.h>
11
12#include "gdsys_soc.h"
13
14/**
15 * struct gdsys_soc_priv - Private data for gdsys soc bus
16 * @fpga: The gdsys IHS FPGA this bus is associated with
17 */
18struct gdsys_soc_priv {
19 struct udevice *fpga;
20};
21
22static const struct udevice_id gdsys_soc_ids[] = {
23 { .compatible = "gdsys,soc" },
24 { /* sentinel */ }
25};
26
27int gdsys_soc_get_fpga(struct udevice *child, struct udevice **fpga)
28{
29 struct gdsys_soc_priv *bus_priv;
30
31 if (!child->parent) {
32 debug("%s: Invalid parent\n", child->name);
33 return -EINVAL;
34 }
35
36 if (!device_is_compatible(child->parent, "gdsys,soc")) {
37 debug("%s: Not child of a gdsys soc\n", child->name);
38 return -EINVAL;
39 }
40
41 bus_priv = dev_get_priv(child->parent);
42
43 *fpga = bus_priv->fpga;
44
45 return 0;
46}
47
48static int gdsys_soc_probe(struct udevice *dev)
49{
50 struct gdsys_soc_priv *priv = dev_get_priv(dev);
51 struct udevice *fpga;
52 int res = uclass_get_device_by_phandle(UCLASS_MISC, dev, "fpga",
53 &fpga);
54 if (res == -ENOENT) {
55 debug("%s: Could not find 'fpga' phandle\n", dev->name);
56 return -EINVAL;
57 }
58
59 if (res == -ENODEV) {
60 debug("%s: Could not get FPGA device\n", dev->name);
61 return -EINVAL;
62 }
63
64 priv->fpga = fpga;
65
66 return 0;
67}
68
69U_BOOT_DRIVER(gdsys_soc_bus) = {
70 .name = "gdsys_soc_bus",
71 .id = UCLASS_SIMPLE_BUS,
72 .of_match = gdsys_soc_ids,
73 .probe = gdsys_soc_probe,
Simon Glass41575d82020-12-03 16:55:17 -070074 .priv_auto = sizeof(struct gdsys_soc_priv),
Mario Sixc0a2b082018-10-04 09:00:54 +020075};