blob: 2d63b670cd7c5011bad815533aef8338629f8c50 [file] [log] [blame]
Heiko Schocherf7264c32011-11-29 02:33:47 +00001/*
2 * (C) Copyright 2011
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * Based on:
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * Based on davinci_dvevm.h. Original Copyrights follow:
9 *
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * Board
32 */
33#define CONFIG_DRIVER_TI_EMAC
34#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
35#define CONFIG_USE_NAND
36
37/*
38 * SoC Configuration
39 */
40#define CONFIG_ARM926EJS /* arm926ejs CPU core */
41#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
42#define CONFIG_SOC_DA850 /* TI DA850 SoC */
Christian Rieschb67d8812012-02-02 00:44:39 +000043#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Heiko Schocherf7264c32011-11-29 02:33:47 +000044#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
45#define CONFIG_SYS_OSCIN_FREQ 24000000
46#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
47#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
48#define CONFIG_SYS_HZ 1000
Heiko Schocherf7264c32011-11-29 02:33:47 +000049#define CONFIG_DA850_LOWLEVEL
50#define CONFIG_ARCH_CPU_INIT
Sughosh Ganu6b873dc2012-02-02 00:44:41 +000051#define CONFIG_SYS_DA850_PLL_INIT
52#define CONFIG_SYS_DA850_DDR_INIT
Heiko Schocherf7264c32011-11-29 02:33:47 +000053#define CONFIG_DA8XX_GPIO
54#define CONFIG_HOSTNAME enbw_cmc
Heiko Schocherf7264c32011-11-29 02:33:47 +000055
56#define MACH_TYPE_ENBW_CMC 3585
57#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
58
59/*
60 * Memory Info
61 */
62#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
63#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
64#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
65#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
66
67/* memtest start addr */
68#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
69
70/* memtest will be run on 16MB */
71#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
72
73#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Heiko Schocherf7264c32011-11-29 02:33:47 +000074
75/*
76 * Serial Driver info
77 */
78#define CONFIG_SYS_NS16550
79#define CONFIG_SYS_NS16550_SERIAL
80#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
81#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
82#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
83#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
84#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Sughosh Ganu6b873dc2012-02-02 00:44:41 +000085
Heiko Schocherf7264c32011-11-29 02:33:47 +000086/*
87 * I2C Configuration
88 */
89#define CONFIG_HARD_I2C
90#define CONFIG_DRIVER_DAVINCI_I2C
91#define CONFIG_SYS_I2C_SPEED 80000
92#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
93#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
94#define CONFIG_CMD_I2C
95
96#define CONFIG_CMD_DTT
97#define CONFIG_DTT_LM75
98#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
99#define CONFIG_SYS_DTT_MAX_TEMP 70
100#define CONFIG_SYS_DTT_LOW_TEMP -30
101#define CONFIG_SYS_DTT_HYSTERESIS 3
102
103/*
Heiko Schocher14b9f162012-05-14 20:24:14 +0000104 * SPI Configuration
105 */
106#define CONFIG_DAVINCI_SPI
107#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
108#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
109#define CONFIG_CMD_SPI
110
111/*
Heiko Schocherf7264c32011-11-29 02:33:47 +0000112 * Flash & Environment
113 */
114#ifdef CONFIG_USE_NAND
115#define CONFIG_NAND_DAVINCI
116#define CONFIG_SYS_NAND_USE_FLASH_BBT
117#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
118#define CONFIG_SYS_NAND_PAGE_2K
119#define CONFIG_SYS_NAND_CS 3
120#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
121#define CONFIG_SYS_CLE_MASK 0x10
122#define CONFIG_SYS_ALE_MASK 0x8
123#undef CONFIG_SYS_NAND_HW_ECC
124#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Heiko Schocherf7264c32011-11-29 02:33:47 +0000125
126#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
127#define MTDPARTS_DEFAULT \
128 "mtdparts=" \
129 "physmap-flash.0:" \
130 "512k(U-Boot)," \
131 "64k(env1)," \
132 "64k(env2)," \
133 "-(rest);" \
134 "davinci_nand.1:" \
135 "128k(dtb)," \
136 "3m(kernel)," \
137 "4m(rootfs)," \
138 "-(userfs)"
139
140
141#define CONFIG_CMD_MTDPARTS
142
143#endif
144
145/*
146 * Network & Ethernet Configuration
147 */
148#ifdef CONFIG_DRIVER_TI_EMAC
149#define CONFIG_MII
150#define CONFIG_BOOTP_DEFAULT
151#define CONFIG_BOOTP_DNS
152#define CONFIG_BOOTP_DNS2
153#define CONFIG_BOOTP_SEND_HOSTNAME
154#define CONFIG_NET_RETRY_COUNT 10
Heiko Schocherf7264c32011-11-29 02:33:47 +0000155#endif
156
157/*
158 * Flash configuration
159 */
160#define CONFIG_SYS_FLASH_CFI
161#define CONFIG_FLASH_CFI_DRIVER
162#define CONFIG_FLASH_CFI_MTD
163#define CONFIG_SYS_FLASH_BASE 0x60000000
164#define CONFIG_SYS_FLASH_SIZE 0x01000000
165#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
166#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
167#define CONFIG_SYS_MAX_FLASH_SECT 128
168#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
169
170#define CONFIG_CMD_FLASH
171
172#define CONFIG_ENV_IS_IN_FLASH
173#define CONFIG_SYS_MONITOR_LEN 0x80000
174#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
175 CONFIG_SYS_MONITOR_LEN)
176#define CONFIG_ENV_SECT_SIZE (64 << 10)
177#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
178#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
179 CONFIG_ENV_SECT_SIZE)
180#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
181#undef CONFIG_ENV_IS_IN_NAND
182#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
183 CONFIG_ENV_SECT_SIZE)
184
Heiko Schocherf7264c32011-11-29 02:33:47 +0000185#define CONFIG_EXTRA_ENV_SETTINGS \
186 "u-boot_addr_r=c0000000\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200187 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000188 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200189 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
190 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
191 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000192 " ${filesize};" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200193 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
Heiko Schocherf7264c32011-11-29 02:33:47 +0000194 "netdev=eth0\0" \
195 "rootpath=/opt/eldk-arm/arm\0" \
196 "nfsargs=setenv bootargs root=/dev/nfs rw " \
197 "nfsroot=${serverip}:${rootpath}\0" \
198 "ramargs=setenv bootargs root=/dev/ram rw\0" \
199 "addip=setenv bootargs ${bootargs} " \
200 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
201 ":${hostname}:${netdev}:off panic=1\0" \
202 "kernel_addr_r=c0700000\0" \
203 "fdt_addr_r=c0600000\0" \
204 "ramdisk_addr_r=c0b00000\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200205 "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
206 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
207 "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000208 "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
209 "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
210 "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
211 "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
212 "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
213 "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
214 "addcon=setenv bootargs ${bootargs} console=ttyS2," \
215 "${baudrate}n8\0" \
216 "net_nfs=run load_fdt load_kernel; " \
217 "run nfsargs addip addcon addmtd addmisc;" \
218 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
219 "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
220 "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
221 "bootcmd=run net_nfs\0" \
222 "machid=e01\0" \
223 "key_cmd_0=echo key: 0\0" \
224 "key_cmd_1=echo key: 1\0" \
225 "key_cmd_2=echo key: 2\0" \
226 "key_cmd_3=echo key: 3\0" \
227 "key_magic_0=0\0" \
228 "key_magic_1=1\0" \
229 "key_magic_2=2\0" \
230 "key_magic_3=3\0" \
231 "magic_keys=0123\0" \
Heiko Schocher14b9f162012-05-14 20:24:14 +0000232 "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000233 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
Heiko Schocher14b9f162012-05-14 20:24:14 +0000234 "addmisc=setenv bootargs ${bootargs}\0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000235 "mtdids=" MTDIDS_DEFAULT "\0" \
236 "mtdparts=" MTDPARTS_DEFAULT "\0" \
237 "logversion=2\0" \
238 "\0"
239
240/*
241 * U-Boot general configuration
242 */
243#define CONFIG_BOOTFILE "uImage" /* Boot file name */
244#define CONFIG_SYS_PROMPT "=> " /* Command Prompt */
245#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
246#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
247#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
248#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
249#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
250#define CONFIG_VERSION_VARIABLE
251#define CONFIG_AUTO_COMPLETE
252#define CONFIG_SYS_HUSH_PARSER
Heiko Schocherf7264c32011-11-29 02:33:47 +0000253#define CONFIG_CMDLINE_EDITING
254#define CONFIG_SYS_LONGHELP
255#define CONFIG_CRC32_VERIFY
256#define CONFIG_MX_CYCLIC
257#define CONFIG_BOOTDELAY 3
258#define CONFIG_HWCONFIG
259#define CONFIG_SHOW_BOOT_PROGRESS
260#define CONFIG_BOARD_LATE_INIT
261
262/*
263 * U-Boot commands
264 */
265#include <config_cmd_default.h>
266#define CONFIG_CMD_ENV
267#define CONFIG_CMD_ASKENV
268#define CONFIG_CMD_DHCP
269#define CONFIG_CMD_DIAG
270#define CONFIG_CMD_MII
271#define CONFIG_CMD_PING
272#define CONFIG_CMD_SAVES
273#define CONFIG_CMD_MEMORY
274#define CONFIG_CMD_CACHE
275
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000276#ifdef CONFIG_CMD_BDI
277#define CONFIG_CLOCKS
278#endif
279
Heiko Schocherf7264c32011-11-29 02:33:47 +0000280#ifndef CONFIG_DRIVER_TI_EMAC
281#undef CONFIG_CMD_NET
282#undef CONFIG_CMD_DHCP
283#undef CONFIG_CMD_MII
284#undef CONFIG_CMD_PING
285#endif
286
287#ifdef CONFIG_USE_NAND
288#undef CONFIG_CMD_IMLS
289#define CONFIG_CMD_NAND
290
291#define CONFIG_CMD_MTDPARTS
292#define CONFIG_MTD_DEVICE
293#define CONFIG_MTD_PARTITIONS
294#define CONFIG_LZO
295#define CONFIG_RBTREE
296#define CONFIG_CMD_UBI
297#define CONFIG_CMD_UBIFS
298#endif
299
300#if !defined(CONFIG_USE_NAND) && \
301 !defined(CONFIG_USE_NOR) && \
302 !defined(CONFIG_USE_SPIFLASH)
303#define CONFIG_ENV_IS_NOWHERE
304#define CONFIG_SYS_NO_FLASH
305#define CONFIG_ENV_SIZE (16 << 10)
306#undef CONFIG_CMD_IMLS
307#undef CONFIG_CMD_ENV
308#endif
309
310#define CONFIG_SYS_TEXT_BASE 0x60000000
311#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
312#define CONFIG_SYS_SDRAM_BASE 0xc0000000
313#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
314
315#define CONFIG_VERSION_VARIABLE
316#define CONFIG_ENV_OVERWRITE
317
318#define CONFIG_PREBOOT "echo;" \
319 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
320 "echo"
321#define CONFIG_MISC_INIT_R
322
323#define CONFIG_CMC_RESET_PIN 0x04000000
324#define CONFIG_CMC_RESET_TIMEOUT 3
325
326#define CONFIG_HW_WATCHDOG
327#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
328#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
329#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
330
331#define CONFIG_CMD_DATE
332#define CONFIG_RTC_DAVINCI
333
334/* SD/MMC */
335#define CONFIG_MMC
336#define CONFIG_GENERIC_MMC
337#define CONFIG_DAVINCI_MMC
338#define CONFIG_MMC_MBLOCK
339#define CONFIG_DOS_PARTITION
340#define CONFIG_CMD_FAT
341#define CONFIG_CMD_MMC
342
Heiko Schocher14b9f162012-05-14 20:24:14 +0000343/* GPIO */
344#define CONFIG_ENBW_CMC_BOARD_TYPE 57
345#define CONFIG_ENBW_CMC_HW_ID_BIT0 39
346#define CONFIG_ENBW_CMC_HW_ID_BIT1 38
347#define CONFIG_ENBW_CMC_HW_ID_BIT2 35
Heiko Schocherf7264c32011-11-29 02:33:47 +0000348
349/* FDT support */
350#define CONFIG_OF_LIBFDT
351
352/* LowLevel Init */
353/* PLL */
354#define CONFIG_SYS_DV_CLKMODE 0
355#define CONFIG_SYS_DA850_PLL0_POSTDIV 0
356#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
357#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
358#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */
359#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
360#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
361#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
362#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
363
364#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
365#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
366#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
367#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
368
369#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */
370#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
371
372/* DDR RAM */
373#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
374 DV_DDR_PHY_EXT_STRBEN | \
375 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
376
377#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
378 (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
379 (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
380 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
381 (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
382 (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
383 (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
384 (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
385 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
386 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
387 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
388
389#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
390
391/*
392 * freq = 150MHz -> t = 7ns
393 */
394#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
395 (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \
396 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
397 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
398 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
399 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
400 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
401 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
402 (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
403 ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
404
405/*
406 * freq = 150MHz -> t=7ns
407 */
408#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
409 (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
410 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
411 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
412 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
413 (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
414 (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
415 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
416 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
417
418#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407
419#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
420#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
421 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
422 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
423 DAVINCI_SYSCFG_SUSPSRC_EMAC |\
424 DAVINCI_SYSCFG_SUSPSRC_I2C)
425
426#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
427 DAVINCI_ABCR_WSTROBE(6) | \
428 DAVINCI_ABCR_WHOLD(1) | \
429 DAVINCI_ABCR_RSETUP(2) | \
430 DAVINCI_ABCR_RSTROBE(6) | \
431 DAVINCI_ABCR_RHOLD(1) | \
432 DAVINCI_ABCR_ASIZE_16BIT)
433
434#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
435 DAVINCI_ABCR_WSTROBE(2) | \
436 DAVINCI_ABCR_WHOLD(1) | \
437 DAVINCI_ABCR_RSETUP(1) | \
438 DAVINCI_ABCR_RSTROBE(6) | \
439 DAVINCI_ABCR_RHOLD(1) | \
440 DAVINCI_ABCR_ASIZE_8BIT)
441
442/*
443 * NOR Bootconfiguration word:
444 * Method: Direc boot
445 * EMIFA access mode: 16 Bit
446 */
447#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
448
449#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
Heiko Schocher14b9f162012-05-14 20:24:14 +0000450#define CONFIG_POST_EXTERNAL_WORD_FUNCS
451#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
Heiko Schocherf7264c32011-11-29 02:33:47 +0000452#define CONFIG_LOGBUFFER
453#define CONFIG_SYS_CONSOLE_IS_IN_ENV
454
455#define CONFIG_BOOTCOUNT_LIMIT
456#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
Stefan Roese0044c422012-08-16 17:55:41 +0000457#define CONFIG_SYS_BOOTCOUNT_BE
Heiko Schocherf7264c32011-11-29 02:33:47 +0000458
459#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
460#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
461#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
462#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
463#endif /* __CONFIG_H */