Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 18a952ce7f7d1059fb11bd1b479ad663a4abb6db / . / arch / arm / dts / zynqmp-clk.dtsi
blob: 45d84a6b7df95a6947ef813eea7d10c53943f82b [file] [log] [blame]
Michal Simek18a952c2018-03-27 10:36:39 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]2/*
3 * Clock specification for Xilinx ZynqMP
4 *
Michal Simek18a952c2018-03-27 10:36:39 +0200[diff] [blame^]5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]6 *
7 * Michal Simek <michal.simek@xilinx.com>
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]8 */
9
Michal Simekb0c55202017-07-05 14:51:42 +0200[diff] [blame]10/ {
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]11 clk100: clk100 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <100000000>;
Michal Simeka9022b02016-07-29 13:03:29 +0200[diff] [blame]15 u-boot,dm-pre-reloc;
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]16 };
17
18 clk125: clk125 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <125000000>;
22 };
23
24 clk200: clk200 {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <200000000>;
28 };
29
30 clk250: clk250 {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <250000000>;
34 };
35
36 clk300: clk300 {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <300000000>;
40 };
41
42 clk600: clk600 {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <600000000>;
46 };
47
48 dp_aclk: clock0 {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
51 clock-frequency = <100000000>;
52 clock-accuracy = <100>;
53 };
54
55 dp_aud_clk: clock1 {
56 compatible = "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <24576000>;
59 clock-accuracy = <100>;
60 };
61
62 dpdma_clk: dpdma_clk {
63 compatible = "fixed-clock";
64 #clock-cells = <0x0>;
65 clock-frequency = <533000000>;
66 };
67
68 drm_clock: drm_clock {
69 compatible = "fixed-clock";
70 #clock-cells = <0x0>;
71 clock-frequency = <262750000>;
72 clock-accuracy = <0x64>;
73 };
74};
75
76&can0 {
77 clocks = <&clk100 &clk100>;
78};
79
80&can1 {
81 clocks = <&clk100 &clk100>;
82};
83
84&fpd_dma_chan1 {
85 clocks = <&clk600>, <&clk100>;
86};
87
88&fpd_dma_chan2 {
89 clocks = <&clk600>, <&clk100>;
90};
91
92&fpd_dma_chan3 {
93 clocks = <&clk600>, <&clk100>;
94};
95
96&fpd_dma_chan4 {
97 clocks = <&clk600>, <&clk100>;
98};
99
100&fpd_dma_chan5 {
101 clocks = <&clk600>, <&clk100>;
102};
103
104&fpd_dma_chan6 {
105 clocks = <&clk600>, <&clk100>;
106};
107
108&fpd_dma_chan7 {
109 clocks = <&clk600>, <&clk100>;
110};
111
112&fpd_dma_chan8 {
113 clocks = <&clk600>, <&clk100>;
114};
115
Kedareswara rao Appana57bcd5c2016-09-09 12:36:00 +0530[diff] [blame]116&lpd_dma_chan1 {
117 clocks = <&clk600>, <&clk100>;
118};
119
120&lpd_dma_chan2 {
121 clocks = <&clk600>, <&clk100>;
122};
123
124&lpd_dma_chan3 {
125 clocks = <&clk600>, <&clk100>;
126};
127
128&lpd_dma_chan4 {
129 clocks = <&clk600>, <&clk100>;
130};
131
132&lpd_dma_chan5 {
133 clocks = <&clk600>, <&clk100>;
134};
135
136&lpd_dma_chan6 {
137 clocks = <&clk600>, <&clk100>;
138};
139
140&lpd_dma_chan7 {
141 clocks = <&clk600>, <&clk100>;
142};
143
144&lpd_dma_chan8 {
145 clocks = <&clk600>, <&clk100>;
146};
147
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]148&nand0 {
149 clocks = <&clk100 &clk100>;
150};
151
152&gem0 {
153 clocks = <&clk125>, <&clk125>, <&clk125>;
154};
155
156&gem1 {
157 clocks = <&clk125>, <&clk125>, <&clk125>;
158};
159
160&gem2 {
161 clocks = <&clk125>, <&clk125>, <&clk125>;
162};
163
164&gem3 {
165 clocks = <&clk125>, <&clk125>, <&clk125>;
166};
167
168&gpio {
169 clocks = <&clk100>;
170};
171
172&i2c0 {
173 clocks = <&clk100>;
174};
175
176&i2c1 {
177 clocks = <&clk100>;
178};
179
180&qspi {
181 clocks = <&clk300 &clk300>;
182};
183
184&sata {
185 clocks = <&clk250>;
186};
187
188&sdhci0 {
189 clocks = <&clk200 &clk200>;
190};
191
192&sdhci1 {
193 clocks = <&clk200 &clk200>;
194};
195
196&spi0 {
197 clocks = <&clk200 &clk200>;
198};
199
200&spi1 {
201 clocks = <&clk200 &clk200>;
202};
203
204&uart0 {
205 clocks = <&clk100 &clk100>;
206};
207
208&uart1 {
209 clocks = <&clk100 &clk100>;
210};
211
212&usb0 {
213 clocks = <&clk250>, <&clk250>;
214};
215
216&usb1 {
217 clocks = <&clk250>, <&clk250>;
218};
219
Shubhrajyoti Datta14de6c42016-10-21 16:12:19 +0530[diff] [blame]220&watchdog0 {
221 clocks = <&clk250>;
222};
223
Michal Simek1f4f3d32016-04-07 15:58:23 +0200[diff] [blame]224&xilinx_drm {
225 clocks = <&drm_clock>;
226};
227
228&xlnx_dp {
229 clocks = <&dp_aclk>, <&dp_aud_clk>;
230};
231
232&xlnx_dpdma {
233 clocks = <&dpdma_clk>;
234};
235
236&xlnx_dp_snd_codec0 {
237 clocks = <&dp_aud_clk>;
238};