Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 18aa5a4134e8179c7c3e38675822284a2718a3d8 / . / include / configs / socfpga_cyclone5_socdk.h
blob: 018a0c3bb48a494de01937740f620f26fa30521b [file] [log] [blame]
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]1/*
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]2 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]5 */
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]6#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
7#define __CONFIG_SOCFPGA_CYCLONE5_H__
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]8
Dinh Nguyen871c24b2015-11-23 17:27:17 -0600[diff] [blame]9#include <asm/arch/base_addr_ac5.h>
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]10
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]11#define CONFIG_HW_WATCHDOG
12
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]13/* Memory configurations */
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]14#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]15
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]16/* Booting Linux */
Marek Vasut4c6d8b92015-07-22 06:18:19 +0200[diff] [blame]17#define CONFIG_LOADADDR 0x01000000
Marek Vasut47f9b4e2014-09-08 14:08:45 +0200[diff] [blame]18#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
19
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]20/* Ethernet on SoC (EMAC) */
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]21
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]22/* The rest of the configuration is shared */
23#include <configs/socfpga_common.h>
Dinh Nguyen77754402012-10-04 06:46:02 +0000[diff] [blame]24
Pavel Machek5095ee02014-09-08 14:08:45 +0200[diff] [blame]25#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */