| Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004 Freescale Semiconductor. |
| 3 | * Jeff Brown (jeffrey@freescale.com) |
| 4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #include <ppc_asm.tmpl> |
| 26 | #include <ppc_defs.h> |
| 27 | #include <asm/cache.h> |
| 28 | #include <asm/mmu.h> |
| 29 | #include <config.h> |
| 30 | #include <mpc86xx.h> |
| 31 | |
| 32 | /* |
| 33 | * LAW(Local Access Window) configuration: |
| 34 | * |
| 35 | * 0x0000_0000 0x7fff_ffff DDR 2G |
| 36 | * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
| 37 | * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
| 38 | * 0xc000_0000 0xdfff_ffff RapidIO 512M |
| 39 | * 0xe000_0000 0xe000_ffff CCSR 1M |
| 40 | * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
| 41 | * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M |
| 42 | * 0xf000_0000 0xf7ff_ffff SDRAM 128M |
| 43 | * 0xf800_0000 0xf80f_ffff BCSR 1M |
| 44 | * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M |
| 45 | * |
| 46 | * Notes: |
| 47 | * CCSRBAR don't need a configured Local Access Window. |
| 48 | * If flash is 8M at default position (last 8M), no LAW needed. |
| 49 | */ |
| 50 | |
| 51 | #if !defined(CONFIG_SPD_EEPROM) |
| 52 | #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff) |
| 53 | #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
| 54 | #else |
| 55 | #define LAWBAR1 0 |
| 56 | #define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) |
| 57 | #endif |
| 58 | |
| 59 | #define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff) |
| 60 | #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
| 61 | |
| 62 | #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff) |
| 63 | /*#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */ |
| 64 | #define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))) |
| 65 | |
| 66 | /* |
| 67 | * This is not so much the SDRAM map as it is the whole localbus map. |
| 68 | */ |
| 69 | #define LAWBAR4 ((0xf8100000>>12) & 0xffffff) |
| 70 | #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M)) |
| 71 | |
| 72 | #define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff) |
| 73 | #define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
| 74 | |
| 75 | #define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff) |
| 76 | /*#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */ |
| 77 | #define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))) |
| 78 | |
| 79 | #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff) |
| 80 | #define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M)) |
| 81 | |
| 82 | |
| Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 83 | .section .bootpg, "ax" |
| 84 | .globl law_entry |
| 85 | law_entry: |
| 86 | lis r7,CFG_CCSRBAR@h |
| 87 | ori r7,r7,CFG_CCSRBAR@l |
| 88 | |
| 89 | addi r4,r7,0 |
| 90 | addi r5,r7,0 |
| 91 | |
| 92 | /* Skip LAWAR0, start at LAWAR1 */ |
| 93 | lis r6,LAWBAR1@h |
| 94 | ori r6,r6,LAWBAR1@l |
| 95 | stwu r6, 0xc28(r4) |
| 96 | |
| 97 | lis r6,LAWAR1@h |
| 98 | ori r6,r6,LAWAR1@l |
| 99 | stwu r6, 0xc30(r5) |
| 100 | |
| 101 | /* LAWBAR2, LAWAR2 */ |
| 102 | lis r6,LAWBAR2@h |
| 103 | ori r6,r6,LAWBAR2@l |
| 104 | stwu r6, 0x20(r4) |
| 105 | |
| 106 | lis r6,LAWAR2@h |
| 107 | ori r6,r6,LAWAR2@l |
| 108 | stwu r6, 0x20(r5) |
| 109 | |
| 110 | /* LAWBAR3, LAWAR3 */ |
| 111 | lis r6,LAWBAR3@h |
| 112 | ori r6,r6,LAWBAR3@l |
| 113 | stwu r6, 0x20(r4) |
| 114 | |
| 115 | lis r6,LAWAR3@h |
| 116 | ori r6,r6,LAWAR3@l |
| 117 | stwu r6, 0x20(r5) |
| 118 | |
| 119 | /* LAWBAR4, LAWAR4 */ |
| 120 | lis r6,LAWBAR4@h |
| 121 | ori r6,r6,LAWBAR4@l |
| 122 | stwu r6, 0x20(r4) |
| 123 | |
| 124 | lis r6,LAWAR4@h |
| 125 | ori r6,r6,LAWAR4@l |
| 126 | stwu r6, 0x20(r5) |
| 127 | /* LAWBAR5, LAWAR5 */ |
| 128 | lis r6,LAWBAR5@h |
| 129 | ori r6,r6,LAWBAR5@l |
| 130 | stwu r6, 0x20(r4) |
| 131 | |
| 132 | lis r6,LAWAR5@h |
| 133 | ori r6,r6,LAWAR5@l |
| 134 | stwu r6, 0x20(r5) |
| 135 | |
| 136 | /* LAWBAR6, LAWAR6 */ |
| 137 | lis r6,LAWBAR6@h |
| 138 | ori r6,r6,LAWBAR6@l |
| 139 | stwu r6, 0x20(r4) |
| 140 | |
| 141 | lis r6,LAWAR6@h |
| 142 | ori r6,r6,LAWAR6@l |
| 143 | stwu r6, 0x20(r5) |
| 144 | |
| 145 | /* LAWBAR7, LAWAR7 */ |
| 146 | lis r6,LAWBAR7@h |
| 147 | ori r6,r6,LAWBAR7@l |
| 148 | stwu r6, 0x20(r4) |
| 149 | |
| 150 | lis r6,LAWAR7@h |
| 151 | ori r6,r6,LAWAR7@l |
| 152 | stwu r6, 0x20(r5) |
| 153 | |
| 154 | blr |
| 155 | |