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wdenk8ed96042005-01-09 23:16:25 +00001/*
2 * Basic I2C functions
3 *
4 * Copyright (c) 2004 Texas Instruments
5 *
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15 *
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
18 *
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20 *
Lubomir Popov960187f2013-06-01 06:44:38 +000021 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24 * OMAPs and derivatives as well. The only anticipated exception would
25 * be the OMAP2420, which shall require driver modification.
26 * - Rewritten i2c_read to operate correctly with all types of chips
27 * (old function could not read consistent data from some I2C slaves).
28 * - Optimized i2c_write.
29 * - New i2c_probe, performs write access vs read. The old probe could
30 * hang the system under certain conditions (e.g. unconfigured pads).
31 * - The read/write/probe functions try to identify unconfigured bus.
32 * - Status functions now read irqstatus_raw as per TRM guidelines
33 * (except for OMAP243X and OMAP34XX).
34 * - Driver now supports up to I2C5 (OMAP5).
Hannes Petermaierd5243352014-02-03 21:22:18 +010035 *
36 * Copyright (c) 2014 Hannes Petermaier <oe5hpm@oevsv.at>, B&R
37 * - Added support for set_speed
38 *
wdenk8ed96042005-01-09 23:16:25 +000039 */
40
41#include <common.h>
Heiko Schocher6789e842013-10-22 11:03:18 +020042#include <i2c.h>
wdenk289f9322005-01-12 00:15:14 +000043
wdenk8ed96042005-01-09 23:16:25 +000044#include <asm/arch/i2c.h>
45#include <asm/io.h>
46
Steve Sakoman938717c2010-06-12 06:42:57 -070047#include "omap24xx_i2c.h"
48
John Rigby29565322010-12-20 18:27:51 -070049DECLARE_GLOBAL_DATA_PTR;
50
Tom Rinicec487a2012-02-20 18:49:16 +000051#define I2C_TIMEOUT 1000
Steve Sakomand7083952010-07-19 20:31:55 -070052
Lubomir Popov960187f2013-06-01 06:44:38 +000053/* Absolutely safe for status update at 100 kHz I2C: */
54#define I2C_WAIT 200
55
Heiko Schocher6789e842013-10-22 11:03:18 +020056static int wait_for_bb(struct i2c_adapter *adap);
57static struct i2c *omap24_get_base(struct i2c_adapter *adap);
58static u16 wait_for_event(struct i2c_adapter *adap);
59static void flush_fifo(struct i2c_adapter *adap);
Hannes Petermaierd5243352014-02-03 21:22:18 +010060static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
61{
62 unsigned int sampleclk, prescaler;
63 int fsscll, fssclh;
wdenk8ed96042005-01-09 23:16:25 +000064
Hannes Petermaierd5243352014-02-03 21:22:18 +010065 speed <<= 1;
66 prescaler = 0;
67 /*
68 * some divisors may cause a precission loss, but shouldn't
69 * be a big thing, because i2c_clk is then allready very slow.
70 */
71 while (prescaler <= 0xFF) {
72 sampleclk = I2C_IP_CLK / (prescaler+1);
73
74 fsscll = sampleclk / speed;
75 fssclh = fsscll;
76 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
77 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
78
79 if (((fsscll > 0) && (fssclh > 0)) &&
80 ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) &&
81 (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) {
82 if (pscl)
83 *pscl = fsscll;
84 if (psch)
85 *psch = fssclh;
86
87 return prescaler;
88 }
89 prescaler++;
90 }
91 return -1;
92}
93static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
wdenk8ed96042005-01-09 23:16:25 +000094{
Heiko Schocher6789e842013-10-22 11:03:18 +020095 struct i2c *i2c_base = omap24_get_base(adap);
Hannes Petermaierd5243352014-02-03 21:22:18 +010096 int psc, fsscll = 0, fssclh = 0;
Tom Rix7f79dfb2009-06-28 12:52:27 -050097 int hsscll = 0, hssclh = 0;
Hannes Petermaierd5243352014-02-03 21:22:18 +010098 u32 scll = 0, sclh = 0;
Tom Rix7f79dfb2009-06-28 12:52:27 -050099
Hannes Petermaierd5243352014-02-03 21:22:18 +0100100 if (speed >= OMAP_I2C_HIGH_SPEED) {
Tom Rix7f79dfb2009-06-28 12:52:27 -0500101 /* High speed */
Hannes Petermaierd5243352014-02-03 21:22:18 +0100102 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
103 psc -= 1;
104 if (psc < I2C_PSC_MIN) {
105 printf("Error : I2C unsupported prescaler %d\n", psc);
106 return -1;
107 }
Tom Rix7f79dfb2009-06-28 12:52:27 -0500108
109 /* For first phase of HS mode */
Hannes Petermaierd5243352014-02-03 21:22:18 +0100110 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
111
112 fssclh = fsscll;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500113
114 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
115 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
116 if (((fsscll < 0) || (fssclh < 0)) ||
117 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000118 puts("Error : I2C initializing first phase clock\n");
Hannes Petermaierd5243352014-02-03 21:22:18 +0100119 return -1;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500120 }
121
122 /* For second phase of HS mode */
123 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
124
125 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
126 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
127 if (((fsscll < 0) || (fssclh < 0)) ||
128 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000129 puts("Error : I2C initializing second phase clock\n");
Hannes Petermaierd5243352014-02-03 21:22:18 +0100130 return -1;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500131 }
132
133 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
134 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
135
136 } else {
137 /* Standard and fast speed */
Hannes Petermaierd5243352014-02-03 21:22:18 +0100138 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
139 if (0 > psc) {
Andreas Müller49e9b4b2012-01-04 15:26:19 +0000140 puts("Error : I2C initializing clock\n");
Hannes Petermaierd5243352014-02-03 21:22:18 +0100141 return -1;
Tom Rix7f79dfb2009-06-28 12:52:27 -0500142 }
Tom Rix7f79dfb2009-06-28 12:52:27 -0500143 }
wdenk8ed96042005-01-09 23:16:25 +0000144
Hannes Petermaierd5243352014-02-03 21:22:18 +0100145 adap->speed = speed;
146 adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
147 writew(0, &i2c_base->con);
148 writew(psc, &i2c_base->psc);
149 writew(scll, &i2c_base->scll);
150 writew(sclh, &i2c_base->sclh);
151 writew(I2C_CON_EN, &i2c_base->con);
152 writew(0xFFFF, &i2c_base->stat); /* clear all pending status */
153
154 return 0;
155}
Heiko Schocherf7c10532014-06-30 09:12:09 +0200156
157static void omap24_i2c_deblock(struct i2c_adapter *adap)
158{
159 struct i2c *i2c_base = omap24_get_base(adap);
160 int i;
161 u16 systest;
162 u16 orgsystest;
163
164 /* set test mode ST_EN = 1 */
165 orgsystest = readw(&i2c_base->systest);
166 systest = orgsystest;
167 /* enable testmode */
168 systest |= I2C_SYSTEST_ST_EN;
169 writew(systest, &i2c_base->systest);
170 systest &= ~I2C_SYSTEST_TMODE_MASK;
171 systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
172 writew(systest, &i2c_base->systest);
173
174 /* set SCL, SDA = 1 */
175 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
176 writew(systest, &i2c_base->systest);
177 udelay(10);
178
179 /* toggle scl 9 clocks */
180 for (i = 0; i < 9; i++) {
181 /* SCL = 0 */
182 systest &= ~I2C_SYSTEST_SCL_O;
183 writew(systest, &i2c_base->systest);
184 udelay(10);
185 /* SCL = 1 */
186 systest |= I2C_SYSTEST_SCL_O;
187 writew(systest, &i2c_base->systest);
188 udelay(10);
189 }
190
191 /* send stop */
192 systest &= ~I2C_SYSTEST_SDA_O;
193 writew(systest, &i2c_base->systest);
194 udelay(10);
195 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
196 writew(systest, &i2c_base->systest);
197 udelay(10);
198
199 /* restore original mode */
200 writew(orgsystest, &i2c_base->systest);
201}
202
Hannes Petermaierd5243352014-02-03 21:22:18 +0100203static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
204{
205 struct i2c *i2c_base = omap24_get_base(adap);
206 int timeout = I2C_TIMEOUT;
Heiko Schocherf7c10532014-06-30 09:12:09 +0200207 int deblock = 1;
Hannes Petermaierd5243352014-02-03 21:22:18 +0100208
Heiko Schocherf7c10532014-06-30 09:12:09 +0200209retry:
Michael Jones89677b22011-07-27 14:01:55 -0400210 if (readw(&i2c_base->con) & I2C_CON_EN) {
211 writew(0, &i2c_base->con);
212 udelay(50000);
wdenk8ed96042005-01-09 23:16:25 +0000213 }
214
Tom Rinicec487a2012-02-20 18:49:16 +0000215 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
216 udelay(1000);
217
218 writew(I2C_CON_EN, &i2c_base->con);
219 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
220 if (timeout <= 0) {
221 puts("ERROR: Timeout in soft-reset\n");
222 return;
223 }
224 udelay(1000);
225 }
226
Hannes Petermaierd5243352014-02-03 21:22:18 +0100227 if (0 != omap24_i2c_setspeed(adap, speed)) {
228 printf("ERROR: failed to setup I2C bus-speed!\n");
229 return;
230 }
Tom Rix7f79dfb2009-06-28 12:52:27 -0500231
wdenk8ed96042005-01-09 23:16:25 +0000232 /* own address */
Michael Jones89677b22011-07-27 14:01:55 -0400233 writew(slaveadd, &i2c_base->oa);
Hannes Petermaierd5243352014-02-03 21:22:18 +0100234
Lubomir Popov960187f2013-06-01 06:44:38 +0000235#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
236 /*
237 * Have to enable interrupts for OMAP2/3, these IPs don't have
238 * an 'irqstatus_raw' register and we shall have to poll 'stat'
239 */
Michael Jones89677b22011-07-27 14:01:55 -0400240 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
Lubomir Popov960187f2013-06-01 06:44:38 +0000241 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
242#endif
Michael Jones89677b22011-07-27 14:01:55 -0400243 udelay(1000);
Heiko Schocher6789e842013-10-22 11:03:18 +0200244 flush_fifo(adap);
Michael Jones89677b22011-07-27 14:01:55 -0400245 writew(0xFFFF, &i2c_base->stat);
Heiko Schocherf7c10532014-06-30 09:12:09 +0200246
247 /* Handle possible failed I2C state */
248 if (wait_for_bb(adap))
249 if (deblock == 1) {
250 omap24_i2c_deblock(adap);
251 deblock = 0;
252 goto retry;
253 }
Tom Rinicec487a2012-02-20 18:49:16 +0000254}
255
Heiko Schocher6789e842013-10-22 11:03:18 +0200256static void flush_fifo(struct i2c_adapter *adap)
257{
258 struct i2c *i2c_base = omap24_get_base(adap);
259 u16 stat;
wdenk082acfd2005-01-10 00:01:04 +0000260
Hannes Petermaierd5243352014-02-03 21:22:18 +0100261 /*
262 * note: if you try and read data when its not there or ready
wdenk082acfd2005-01-10 00:01:04 +0000263 * you get a bus error
264 */
Michael Jones89677b22011-07-27 14:01:55 -0400265 while (1) {
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100266 stat = readw(&i2c_base->stat);
Michael Jones89677b22011-07-27 14:01:55 -0400267 if (stat == I2C_STAT_RRDY) {
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100268 readb(&i2c_base->data);
Michael Jones89677b22011-07-27 14:01:55 -0400269 writew(I2C_STAT_RRDY, &i2c_base->stat);
wdenk8ed96042005-01-09 23:16:25 +0000270 udelay(1000);
Michael Jones89677b22011-07-27 14:01:55 -0400271 } else
wdenk8ed96042005-01-09 23:16:25 +0000272 break;
273 }
274}
275
Lubomir Popov960187f2013-06-01 06:44:38 +0000276/*
277 * i2c_probe: Use write access. Allows to identify addresses that are
278 * write-only (like the config register of dual-port EEPROMs)
279 */
Heiko Schocher6789e842013-10-22 11:03:18 +0200280static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
wdenk8ed96042005-01-09 23:16:25 +0000281{
Heiko Schocher6789e842013-10-22 11:03:18 +0200282 struct i2c *i2c_base = omap24_get_base(adap);
Tom Rinicec487a2012-02-20 18:49:16 +0000283 u16 status;
wdenk8ed96042005-01-09 23:16:25 +0000284 int res = 1; /* default = fail */
285
Michael Jones89677b22011-07-27 14:01:55 -0400286 if (chip == readw(&i2c_base->oa))
wdenk8ed96042005-01-09 23:16:25 +0000287 return res;
wdenk8ed96042005-01-09 23:16:25 +0000288
Lubomir Popov960187f2013-06-01 06:44:38 +0000289 /* Wait until bus is free */
Heiko Schocher6789e842013-10-22 11:03:18 +0200290 if (wait_for_bb(adap))
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000291 return res;
wdenk8ed96042005-01-09 23:16:25 +0000292
Lubomir Popov960187f2013-06-01 06:44:38 +0000293 /* No data transfer, slave addr only */
Michael Jones89677b22011-07-27 14:01:55 -0400294 writew(chip, &i2c_base->sa);
Lubomir Popov960187f2013-06-01 06:44:38 +0000295 /* Stop bit needed here */
296 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
297 I2C_CON_STP, &i2c_base->con);
wdenk8ed96042005-01-09 23:16:25 +0000298
Heiko Schocher6789e842013-10-22 11:03:18 +0200299 status = wait_for_event(adap);
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000300
Lubomir Popov960187f2013-06-01 06:44:38 +0000301 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
302 /*
303 * With current high-level command implementation, notifying
304 * the user shall flood the console with 127 messages. If
305 * silent exit is desired upon unconfigured bus, remove the
306 * following 'if' section:
307 */
308 if (status == I2C_STAT_XRDY)
309 printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
Heiko Schocher6789e842013-10-22 11:03:18 +0200310 adap->hwadapnr, status);
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000311
Lubomir Popov960187f2013-06-01 06:44:38 +0000312 goto pr_exit;
Tom Rini168a5ac2012-05-21 06:46:29 +0000313 }
Tom Rinicec487a2012-02-20 18:49:16 +0000314
Lubomir Popov960187f2013-06-01 06:44:38 +0000315 /* Check for ACK (!NAK) */
316 if (!(status & I2C_STAT_NACK)) {
Hannes Petermaierd5243352014-02-03 21:22:18 +0100317 res = 0; /* Device found */
318 udelay(adap->waitdelay);/* Required by AM335X in SPL */
Lubomir Popov960187f2013-06-01 06:44:38 +0000319 /* Abort transfer (force idle state) */
320 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
321 udelay(1000);
322 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
323 I2C_CON_STP, &i2c_base->con); /* STP */
324 }
325pr_exit:
Heiko Schocher6789e842013-10-22 11:03:18 +0200326 flush_fifo(adap);
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100327 writew(0xFFFF, &i2c_base->stat);
wdenk8ed96042005-01-09 23:16:25 +0000328 return res;
329}
330
Lubomir Popov960187f2013-06-01 06:44:38 +0000331/*
332 * i2c_read: Function now uses a single I2C read transaction with bulk transfer
333 * of the requested number of bytes (note that the 'i2c md' command
334 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
335 * defined in the board config header, this transaction shall be with
336 * Repeated Start (Sr) between the address and data phases; otherwise
337 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
338 * The address (reg offset) may be 0, 1 or 2 bytes long.
339 * Function now reads correctly from chips that return more than one
340 * byte of data per addressed register (like TI temperature sensors),
341 * or that do not need a register address at all (such as some clock
342 * distributors).
343 */
Heiko Schocher6789e842013-10-22 11:03:18 +0200344static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
345 int alen, uchar *buffer, int len)
wdenk8ed96042005-01-09 23:16:25 +0000346{
Heiko Schocher6789e842013-10-22 11:03:18 +0200347 struct i2c *i2c_base = omap24_get_base(adap);
Lubomir Popov960187f2013-06-01 06:44:38 +0000348 int i2c_error = 0;
349 u16 status;
350
351 if (alen < 0) {
352 puts("I2C read: addr len < 0\n");
353 return 1;
354 }
355 if (len < 0) {
356 puts("I2C read: data len < 0\n");
357 return 1;
358 }
359 if (buffer == NULL) {
360 puts("I2C read: NULL pointer passed\n");
361 return 1;
362 }
wdenk8ed96042005-01-09 23:16:25 +0000363
Ilya Yanok55faa582012-06-08 03:12:09 +0000364 if (alen > 2) {
Tom Rinicec487a2012-02-20 18:49:16 +0000365 printf("I2C read: addr len %d not supported\n", alen);
wdenk8ed96042005-01-09 23:16:25 +0000366 return 1;
Tom Rinicec487a2012-02-20 18:49:16 +0000367 }
wdenk8ed96042005-01-09 23:16:25 +0000368
Ilya Yanok55faa582012-06-08 03:12:09 +0000369 if (addr + len > (1 << 16)) {
Tom Rinicec487a2012-02-20 18:49:16 +0000370 puts("I2C read: address out of range\n");
371 return 1;
372 }
373
Lubomir Popov960187f2013-06-01 06:44:38 +0000374 /* Wait until bus not busy */
Heiko Schocher6789e842013-10-22 11:03:18 +0200375 if (wait_for_bb(adap))
Lubomir Popov960187f2013-06-01 06:44:38 +0000376 return 1;
377
378 /* Zero, one or two bytes reg address (offset) */
379 writew(alen, &i2c_base->cnt);
380 /* Set slave address */
381 writew(chip, &i2c_base->sa);
382
383 if (alen) {
384 /* Must write reg offset first */
385#ifdef CONFIG_I2C_REPEATED_START
386 /* No stop bit, use Repeated Start (Sr) */
387 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
388 I2C_CON_TRX, &i2c_base->con);
389#else
390 /* Stop - Start (P-S) */
391 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
392 I2C_CON_TRX, &i2c_base->con);
393#endif
394 /* Send register offset */
395 while (1) {
Heiko Schocher6789e842013-10-22 11:03:18 +0200396 status = wait_for_event(adap);
Lubomir Popov960187f2013-06-01 06:44:38 +0000397 /* Try to identify bus that is not padconf'd for I2C */
398 if (status == I2C_STAT_XRDY) {
399 i2c_error = 2;
400 printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
Heiko Schocher6789e842013-10-22 11:03:18 +0200401 adap->hwadapnr, status);
Lubomir Popov960187f2013-06-01 06:44:38 +0000402 goto rd_exit;
403 }
Hannes Petermaierd5243352014-02-03 21:22:18 +0100404 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000405 i2c_error = 1;
406 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
407 status);
408 goto rd_exit;
409 }
410 if (alen) {
411 if (status & I2C_STAT_XRDY) {
412 alen--;
413 /* Do we have to use byte access? */
414 writeb((addr >> (8 * alen)) & 0xff,
415 &i2c_base->data);
416 writew(I2C_STAT_XRDY, &i2c_base->stat);
417 }
418 }
419 if (status & I2C_STAT_ARDY) {
420 writew(I2C_STAT_ARDY, &i2c_base->stat);
421 break;
422 }
423 }
424 }
425 /* Set slave address */
426 writew(chip, &i2c_base->sa);
427 /* Read len bytes from slave */
428 writew(len, &i2c_base->cnt);
429 /* Need stop bit here */
430 writew(I2C_CON_EN | I2C_CON_MST |
431 I2C_CON_STT | I2C_CON_STP,
432 &i2c_base->con);
433
434 /* Receive data */
435 while (1) {
Heiko Schocher6789e842013-10-22 11:03:18 +0200436 status = wait_for_event(adap);
Lubomir Popov960187f2013-06-01 06:44:38 +0000437 /*
438 * Try to identify bus that is not padconf'd for I2C. This
439 * state could be left over from previous transactions if
440 * the address phase is skipped due to alen=0.
441 */
442 if (status == I2C_STAT_XRDY) {
443 i2c_error = 2;
444 printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
Heiko Schocher6789e842013-10-22 11:03:18 +0200445 adap->hwadapnr, status);
Lubomir Popov960187f2013-06-01 06:44:38 +0000446 goto rd_exit;
447 }
Hannes Petermaierd5243352014-02-03 21:22:18 +0100448 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000449 i2c_error = 1;
450 goto rd_exit;
451 }
452 if (status & I2C_STAT_RRDY) {
453 *buffer++ = readb(&i2c_base->data);
454 writew(I2C_STAT_RRDY, &i2c_base->stat);
455 }
456 if (status & I2C_STAT_ARDY) {
457 writew(I2C_STAT_ARDY, &i2c_base->stat);
458 break;
wdenk8ed96042005-01-09 23:16:25 +0000459 }
460 }
461
Lubomir Popov960187f2013-06-01 06:44:38 +0000462rd_exit:
Heiko Schocher6789e842013-10-22 11:03:18 +0200463 flush_fifo(adap);
Lubomir Popov960187f2013-06-01 06:44:38 +0000464 writew(0xFFFF, &i2c_base->stat);
Lubomir Popov960187f2013-06-01 06:44:38 +0000465 return i2c_error;
wdenk8ed96042005-01-09 23:16:25 +0000466}
467
Lubomir Popov960187f2013-06-01 06:44:38 +0000468/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
Heiko Schocher6789e842013-10-22 11:03:18 +0200469static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
470 int alen, uchar *buffer, int len)
wdenk8ed96042005-01-09 23:16:25 +0000471{
Heiko Schocher6789e842013-10-22 11:03:18 +0200472 struct i2c *i2c_base = omap24_get_base(adap);
Tom Rinicec487a2012-02-20 18:49:16 +0000473 int i;
474 u16 status;
475 int i2c_error = 0;
Hannes Petermaierd5243352014-02-03 21:22:18 +0100476 int timeout = I2C_TIMEOUT;
Lubomir Popov960187f2013-06-01 06:44:38 +0000477
478 if (alen < 0) {
479 puts("I2C write: addr len < 0\n");
480 return 1;
481 }
482
483 if (len < 0) {
484 puts("I2C write: data len < 0\n");
485 return 1;
486 }
487
488 if (buffer == NULL) {
489 puts("I2C write: NULL pointer passed\n");
490 return 1;
491 }
wdenk8ed96042005-01-09 23:16:25 +0000492
Ilya Yanok55faa582012-06-08 03:12:09 +0000493 if (alen > 2) {
Tom Rinicec487a2012-02-20 18:49:16 +0000494 printf("I2C write: addr len %d not supported\n", alen);
wdenk8ed96042005-01-09 23:16:25 +0000495 return 1;
Tom Rinicec487a2012-02-20 18:49:16 +0000496 }
wdenk8ed96042005-01-09 23:16:25 +0000497
Ilya Yanok55faa582012-06-08 03:12:09 +0000498 if (addr + len > (1 << 16)) {
Tom Rinicec487a2012-02-20 18:49:16 +0000499 printf("I2C write: address 0x%x + 0x%x out of range\n",
Lubomir Popov960187f2013-06-01 06:44:38 +0000500 addr, len);
wdenk8ed96042005-01-09 23:16:25 +0000501 return 1;
502 }
503
Lubomir Popov960187f2013-06-01 06:44:38 +0000504 /* Wait until bus not busy */
Heiko Schocher6789e842013-10-22 11:03:18 +0200505 if (wait_for_bb(adap))
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000506 return 1;
Michael Jones0607e2b2011-09-04 14:01:55 -0400507
Lubomir Popov960187f2013-06-01 06:44:38 +0000508 /* Start address phase - will write regoffset + len bytes data */
Tom Rinicec487a2012-02-20 18:49:16 +0000509 writew(alen + len, &i2c_base->cnt);
Lubomir Popov960187f2013-06-01 06:44:38 +0000510 /* Set slave address */
Michael Jones0607e2b2011-09-04 14:01:55 -0400511 writew(chip, &i2c_base->sa);
Lubomir Popov960187f2013-06-01 06:44:38 +0000512 /* Stop bit needed here */
Michael Jones0607e2b2011-09-04 14:01:55 -0400513 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
Lubomir Popov960187f2013-06-01 06:44:38 +0000514 I2C_CON_STP, &i2c_base->con);
Michael Jones0607e2b2011-09-04 14:01:55 -0400515
Lubomir Popov960187f2013-06-01 06:44:38 +0000516 while (alen) {
517 /* Must write reg offset (one or two bytes) */
Heiko Schocher6789e842013-10-22 11:03:18 +0200518 status = wait_for_event(adap);
Lubomir Popov960187f2013-06-01 06:44:38 +0000519 /* Try to identify bus that is not padconf'd for I2C */
520 if (status == I2C_STAT_XRDY) {
521 i2c_error = 2;
522 printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
Heiko Schocher6789e842013-10-22 11:03:18 +0200523 adap->hwadapnr, status);
Lubomir Popov960187f2013-06-01 06:44:38 +0000524 goto wr_exit;
525 }
Hannes Petermaierd5243352014-02-03 21:22:18 +0100526 if (status == 0 || (status & I2C_STAT_NACK)) {
Michael Jones0607e2b2011-09-04 14:01:55 -0400527 i2c_error = 1;
Lubomir Popov960187f2013-06-01 06:44:38 +0000528 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
529 status);
530 goto wr_exit;
Tom Rinicec487a2012-02-20 18:49:16 +0000531 }
Tom Rinicec487a2012-02-20 18:49:16 +0000532 if (status & I2C_STAT_XRDY) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000533 alen--;
534 writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
Tom Rinicec487a2012-02-20 18:49:16 +0000535 writew(I2C_STAT_XRDY, &i2c_base->stat);
536 } else {
537 i2c_error = 1;
Lubomir Popov960187f2013-06-01 06:44:38 +0000538 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
539 status);
540 goto wr_exit;
541 }
542 }
543 /* Address phase is over, now write data */
544 for (i = 0; i < len; i++) {
Heiko Schocher6789e842013-10-22 11:03:18 +0200545 status = wait_for_event(adap);
Hannes Petermaierd5243352014-02-03 21:22:18 +0100546 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000547 i2c_error = 1;
548 printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
549 status);
550 goto wr_exit;
551 }
552 if (status & I2C_STAT_XRDY) {
553 writeb(buffer[i], &i2c_base->data);
554 writew(I2C_STAT_XRDY, &i2c_base->stat);
555 } else {
556 i2c_error = 1;
557 printf("i2c_write: bus not ready for data Tx (i=%d)\n",
558 i);
559 goto wr_exit;
wdenk8ed96042005-01-09 23:16:25 +0000560 }
561 }
Hannes Petermaierd5243352014-02-03 21:22:18 +0100562 /*
563 * poll ARDY bit for making sure that last byte really has been
564 * transferred on the bus.
565 */
566 do {
567 status = wait_for_event(adap);
568 } while (!(status & I2C_STAT_ARDY) && timeout--);
569 if (timeout <= 0)
570 printf("i2c_write: timed out writig last byte!\n");
wdenk8ed96042005-01-09 23:16:25 +0000571
Lubomir Popov960187f2013-06-01 06:44:38 +0000572wr_exit:
Heiko Schocher6789e842013-10-22 11:03:18 +0200573 flush_fifo(adap);
Michael Jones0607e2b2011-09-04 14:01:55 -0400574 writew(0xFFFF, &i2c_base->stat);
Tom Rinicec487a2012-02-20 18:49:16 +0000575 return i2c_error;
wdenk8ed96042005-01-09 23:16:25 +0000576}
577
Lubomir Popov960187f2013-06-01 06:44:38 +0000578/*
579 * Wait for the bus to be free by checking the Bus Busy (BB)
580 * bit to become clear
581 */
Heiko Schocher6789e842013-10-22 11:03:18 +0200582static int wait_for_bb(struct i2c_adapter *adap)
wdenk8ed96042005-01-09 23:16:25 +0000583{
Heiko Schocher6789e842013-10-22 11:03:18 +0200584 struct i2c *i2c_base = omap24_get_base(adap);
Steve Sakoman73e87472010-10-20 06:07:44 -0700585 int timeout = I2C_TIMEOUT;
Tom Rinicec487a2012-02-20 18:49:16 +0000586 u16 stat;
wdenk8ed96042005-01-09 23:16:25 +0000587
Tom Rinicec487a2012-02-20 18:49:16 +0000588 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
Lubomir Popov960187f2013-06-01 06:44:38 +0000589#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
Michael Jones89677b22011-07-27 14:01:55 -0400590 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000591#else
592 /* Read RAW status */
593 while ((stat = readw(&i2c_base->irqstatus_raw) &
594 I2C_STAT_BB) && timeout--) {
595#endif
Michael Jones89677b22011-07-27 14:01:55 -0400596 writew(stat, &i2c_base->stat);
Hannes Petermaierd5243352014-02-03 21:22:18 +0100597 udelay(adap->waitdelay);
wdenk8ed96042005-01-09 23:16:25 +0000598 }
599
600 if (timeout <= 0) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000601 printf("Timed out in wait_for_bb: status=%04x\n",
602 stat);
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000603 return 1;
wdenk8ed96042005-01-09 23:16:25 +0000604 }
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100605 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
Vincent Stehléfebc4cd2012-12-03 05:23:16 +0000606 return 0;
wdenk8ed96042005-01-09 23:16:25 +0000607}
608
Lubomir Popov960187f2013-06-01 06:44:38 +0000609/*
610 * Wait for the I2C controller to complete current action
611 * and update status
612 */
Heiko Schocher6789e842013-10-22 11:03:18 +0200613static u16 wait_for_event(struct i2c_adapter *adap)
wdenk8ed96042005-01-09 23:16:25 +0000614{
Heiko Schocher6789e842013-10-22 11:03:18 +0200615 struct i2c *i2c_base = omap24_get_base(adap);
Tom Rinicec487a2012-02-20 18:49:16 +0000616 u16 status;
Steve Sakoman73e87472010-10-20 06:07:44 -0700617 int timeout = I2C_TIMEOUT;
wdenk8ed96042005-01-09 23:16:25 +0000618
619 do {
Hannes Petermaierd5243352014-02-03 21:22:18 +0100620 udelay(adap->waitdelay);
Lubomir Popov960187f2013-06-01 06:44:38 +0000621#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
Michael Jones89677b22011-07-27 14:01:55 -0400622 status = readw(&i2c_base->stat);
Lubomir Popov960187f2013-06-01 06:44:38 +0000623#else
624 /* Read RAW status */
625 status = readw(&i2c_base->irqstatus_raw);
626#endif
Tom Rinicec487a2012-02-20 18:49:16 +0000627 } while (!(status &
628 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
629 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
630 I2C_STAT_AL)) && timeout--);
wdenk8ed96042005-01-09 23:16:25 +0000631
632 if (timeout <= 0) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000633 printf("Timed out in wait_for_event: status=%04x\n",
634 status);
635 /*
636 * If status is still 0 here, probably the bus pads have
637 * not been configured for I2C, and/or pull-ups are missing.
638 */
639 printf("Check if pads/pull-ups of bus %d are properly configured\n",
Heiko Schocher6789e842013-10-22 11:03:18 +0200640 adap->hwadapnr);
Steve Sakoman73e87472010-10-20 06:07:44 -0700641 writew(0xFFFF, &i2c_base->stat);
Tom Rinicec487a2012-02-20 18:49:16 +0000642 status = 0;
Steve Sakoman73e87472010-10-20 06:07:44 -0700643 }
Tom Rinicec487a2012-02-20 18:49:16 +0000644
wdenk8ed96042005-01-09 23:16:25 +0000645 return status;
646}
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100647
Heiko Schocher6789e842013-10-22 11:03:18 +0200648static struct i2c *omap24_get_base(struct i2c_adapter *adap)
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100649{
Heiko Schocher6789e842013-10-22 11:03:18 +0200650 switch (adap->hwadapnr) {
Lubomir Popov960187f2013-06-01 06:44:38 +0000651 case 0:
Heiko Schocher6789e842013-10-22 11:03:18 +0200652 return (struct i2c *)I2C_BASE1;
Lubomir Popov960187f2013-06-01 06:44:38 +0000653 break;
654 case 1:
Heiko Schocher6789e842013-10-22 11:03:18 +0200655 return (struct i2c *)I2C_BASE2;
Lubomir Popov960187f2013-06-01 06:44:38 +0000656 break;
657#if (I2C_BUS_MAX > 2)
658 case 2:
Heiko Schocher6789e842013-10-22 11:03:18 +0200659 return (struct i2c *)I2C_BASE3;
Lubomir Popov960187f2013-06-01 06:44:38 +0000660 break;
661#if (I2C_BUS_MAX > 3)
662 case 3:
Heiko Schocher6789e842013-10-22 11:03:18 +0200663 return (struct i2c *)I2C_BASE4;
Lubomir Popov960187f2013-06-01 06:44:38 +0000664 break;
665#if (I2C_BUS_MAX > 4)
666 case 4:
Heiko Schocher6789e842013-10-22 11:03:18 +0200667 return (struct i2c *)I2C_BASE5;
Lubomir Popov960187f2013-06-01 06:44:38 +0000668 break;
669#endif
670#endif
671#endif
Heiko Schocher6789e842013-10-22 11:03:18 +0200672 default:
673 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
674 break;
Lubomir Popov960187f2013-06-01 06:44:38 +0000675 }
Heiko Schocher6789e842013-10-22 11:03:18 +0200676 return NULL;
Dirk Behme1d2e96d2009-11-02 20:36:26 +0100677}
Steve Sakoman938717c2010-06-12 06:42:57 -0700678
Heiko Schocher6789e842013-10-22 11:03:18 +0200679#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
680#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
681#endif
682#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
683#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
684#endif
685
686U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
Hannes Petermaierd5243352014-02-03 21:22:18 +0100687 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
Heiko Schocher6789e842013-10-22 11:03:18 +0200688 CONFIG_SYS_OMAP24_I2C_SPEED,
689 CONFIG_SYS_OMAP24_I2C_SLAVE,
690 0)
691U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
Hannes Petermaierd5243352014-02-03 21:22:18 +0100692 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
Heiko Schocher6789e842013-10-22 11:03:18 +0200693 CONFIG_SYS_OMAP24_I2C_SPEED1,
694 CONFIG_SYS_OMAP24_I2C_SLAVE1,
695 1)
696#if (I2C_BUS_MAX > 2)
697#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
698#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
699#endif
700#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
701#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
702#endif
703
704U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
705 omap24_i2c_read, omap24_i2c_write, NULL,
706 CONFIG_SYS_OMAP24_I2C_SPEED2,
707 CONFIG_SYS_OMAP24_I2C_SLAVE2,
708 2)
709#if (I2C_BUS_MAX > 3)
710#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
711#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
712#endif
713#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
714#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
715#endif
716
717U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
718 omap24_i2c_read, omap24_i2c_write, NULL,
719 CONFIG_SYS_OMAP24_I2C_SPEED3,
720 CONFIG_SYS_OMAP24_I2C_SLAVE3,
721 3)
722#if (I2C_BUS_MAX > 4)
723#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
724#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
725#endif
726#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
727#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
728#endif
729
730U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
731 omap24_i2c_read, omap24_i2c_write, NULL,
732 CONFIG_SYS_OMAP24_I2C_SPEED4,
733 CONFIG_SYS_OMAP24_I2C_SLAVE4,
734 4)
735#endif
736#endif
737#endif