blob: 79931372113f79b5d3d9f4fea0b2a1fb4d122813 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +00001/*
wdenk10a36a92004-07-10 23:02:23 +00002 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
wdenkfe8c2802002-11-03 00:38:21 +00004 *
wdenk10a36a92004-07-10 23:02:23 +00005 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
wdenkfe8c2802002-11-03 00:38:21 +000015 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
wdenk10a36a92004-07-10 23:02:23 +000038/* Enable debug prints */
wdenk10a36a92004-07-10 23:02:23 +000039#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
wdenkfe8c2802002-11-03 00:38:21 +000040
wdenk10a36a92004-07-10 23:02:23 +000041/*****************************************************************************
42 *
43 * These settings must match the way _your_ board is set up
44 *
45 *****************************************************************************/
wdenkfe8c2802002-11-03 00:38:21 +000046
wdenk10a36a92004-07-10 23:02:23 +000047/* What is the oscillator's (UX2) frequency in Hz? */
48#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
wdenk466b7412004-07-10 22:35:59 +000049
50/*-----------------------------------------------------------------------
wdenk10a36a92004-07-10 23:02:23 +000051 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
52 *-----------------------------------------------------------------------
53 * What should MODCK_H be? It is dependent on the oscillator
54 * frequency, MODCK[1-3], and desired CPM and core frequencies.
55 * Here are some example values (all frequencies are in MHz):
56 *
57 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
58 * ------- ---------- --- --- ---- ----- ----- -----
59 * 0x1 0x5 33 100 133 Open Close Open
60 * 0x1 0x6 33 100 166 Open Open Close
61 * 0x1 0x7 33 100 200 Open Open Open
62 *
63 * 0x2 0x2 33 133 133 Close Open Close
64 * 0x2 0x3 33 133 166 Close Open Open
65 * 0x2 0x4 33 133 200 Open Close Close
66 * 0x2 0x5 33 133 233 Open Close Open
67 * 0x2 0x6 33 133 266 Open Open Close
68 *
69 * 0x5 0x5 66 133 133 Open Close Open
70 * 0x5 0x6 66 133 166 Open Open Close
71 * 0x5 0x7 66 133 200 Open Open Open
72 * 0x6 0x0 66 133 233 Close Close Close
73 * 0x6 0x1 66 133 266 Close Close Open
74 * 0x6 0x2 66 133 300 Close Open Close
75 */
76#define CFG_SBC_MODCK_H 0x05
77
78/* Define this if you want to boot from 0x00000100. If you don't define
79 * this, you will need to program the bootloader to 0xfff00000, and
80 * get the hardware reset config words at 0xfe000000. The simplest
81 * way to do that is to program the bootloader at both addresses.
82 * It is suggested that you just let U-Boot live at 0x00000000.
83 */
84#define CFG_SBC_BOOT_LOW 1
85
86/* What should the base address of the main FLASH be and how big is
87 * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
88 * The main FLASH is whichever is connected to *CS0. U-Boot expects
89 * this to be the SIMM.
90 */
91#define CFG_FLASH0_BASE 0x40000000
92#define CFG_FLASH0_SIZE 4
93
94/* What should the base address of the secondary FLASH be and how big
95 * is it (in Mbytes)? The secondary FLASH is whichever is connected
96 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
97 * want it enabled, don't define these constants.
98 */
99#define CFG_FLASH1_BASE 0x60000000
100#define CFG_FLASH1_SIZE 2
101
102/* What should be the base address of SDRAM DIMM and how big is
103 * it (in Mbytes)?
104*/
105#define CFG_SDRAM0_BASE 0x00000000
106#define CFG_SDRAM0_SIZE 64
107
108/* What should be the base address of the LEDs and switch S0?
109 * If you don't want them enabled, don't define this.
110 */
111#define CFG_LED_BASE 0xa0000000
112
113
114/*
115 * SBC8260 with 16 MB DIMM:
116 *
117 * 0x0000 0000 Exception Vector code, 8k
118 * :
119 * 0x0000 1FFF
120 * 0x0000 2000 Free for Application Use
121 * :
122 * :
123 *
124 * :
125 * :
126 * 0x00F5 FF30 Monitor Stack (Growing downward)
127 * Monitor Stack Buffer (0x80)
128 * 0x00F5 FFB0 Board Info Data
129 * 0x00F6 0000 Malloc Arena
130 * : CFG_ENV_SECT_SIZE, 256k
131 * : CFG_MALLOC_LEN, 128k
132 * 0x00FC 0000 RAM Copy of Monitor Code
133 * : CFG_MONITOR_LEN, 256k
134 * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
wdenk466b7412004-07-10 22:35:59 +0000135 */
136
wdenk10a36a92004-07-10 23:02:23 +0000137/*
138 * SBC8260 with 64 MB DIMM:
139 *
140 * 0x0000 0000 Exception Vector code, 8k
141 * :
142 * 0x0000 1FFF
143 * 0x0000 2000 Free for Application Use
144 * :
145 * :
146 *
147 * :
148 * :
149 * 0x03F5 FF30 Monitor Stack (Growing downward)
150 * Monitor Stack Buffer (0x80)
151 * 0x03F5 FFB0 Board Info Data
152 * 0x03F6 0000 Malloc Arena
153 * : CFG_ENV_SECT_SIZE, 256k
154 * : CFG_MALLOC_LEN, 128k
155 * 0x03FC 0000 RAM Copy of Monitor Code
156 * : CFG_MONITOR_LEN, 256k
157 * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
158 */
159
160
161/*
162 * select serial console configuration
163 *
164 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
165 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
166 * for SCC).
167 *
168 * if CONFIG_CONS_NONE is defined, then the serial console routines must
169 * defined elsewhere.
170 */
171#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
172#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
173#undef CONFIG_CONS_NONE /* define if console on neither */
174#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
175
176/*
177 * select ethernet configuration
178 *
179 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
180 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
181 * for FCC)
182 *
183 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500184 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk10a36a92004-07-10 23:02:23 +0000185 */
186
187#undef CONFIG_ETHER_ON_SCC
188#define CONFIG_ETHER_ON_FCC
189#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
190
191#ifdef CONFIG_ETHER_ON_SCC
192#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
193#endif /* CONFIG_ETHER_ON_SCC */
194
195#ifdef CONFIG_ETHER_ON_FCC
196#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
197#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
198#define CONFIG_MII /* MII PHY management */
199#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
200/*
201 * Port pins used for bit-banged MII communictions (if applicable).
202 */
203#define MDIO_PORT 2 /* Port C */
204#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
205#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
206#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
207
208#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
209 else iop->pdat &= ~0x00400000
210
211#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
212 else iop->pdat &= ~0x00200000
213
214#define MIIDELAY udelay(1)
215#endif /* CONFIG_ETHER_ON_FCC */
216
217#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
218
219/*
220 * - RX clk is CLK11
221 * - TX clk is CLK12
222 */
223# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
224
225#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
226
227/*
228 * - Rx-CLK is CLK13
229 * - Tx-CLK is CLK14
230 * - Select bus for bd/buffers (see 28-13)
231 * - Enable Full Duplex in FSMR
232 */
233# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
234# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
235# define CFG_CPMFCR_RAMTYPE 0
236# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
237
238#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
239
240/*
241 * Select SPI support configuration
242 */
243#undef CONFIG_SPI /* Disable SPI driver */
244
245/*
246 * Select i2c support configuration
247 *
248 * Supported configurations are {none, software, hardware} drivers.
249 * If the software driver is chosen, there are some additional
250 * configuration items that the driver uses to drive the port pins.
251 */
252#undef CONFIG_HARD_I2C /* I2C with hardware support */
253#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
254#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
255#define CFG_I2C_SLAVE 0x7F
256
257/*
258 * Software (bit-bang) I2C driver configuration
259 */
260#ifdef CONFIG_SOFT_I2C
261#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
262#define I2C_ACTIVE (iop->pdir |= 0x00010000)
263#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
264#define I2C_READ ((iop->pdat & 0x00010000) != 0)
265#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
266 else iop->pdat &= ~0x00010000
267#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
268 else iop->pdat &= ~0x00020000
269#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
270#endif /* CONFIG_SOFT_I2C */
271
272
273/* Define this to reserve an entire FLASH sector (256 KB) for
274 * environment variables. Otherwise, the environment will be
275 * put in the same sector as U-Boot, and changing variables
276 * will erase U-Boot temporarily
277 */
278#define CFG_ENV_IN_OWN_SECT 1
279
280/* Define to allow the user to overwrite serial and ethaddr */
281#define CONFIG_ENV_OVERWRITE
282
283/* What should the console's baud rate be? */
284#define CONFIG_BAUDRATE 9600
285
286/* Ethernet MAC address
287 * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx)
288 * http://standards.ieee.org/regauth/oui/index.shtml
289 */
290#define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb
291
292/*
293 * Define this to set the last octet of the ethernet address from the
294 * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7
295 * switch and the LEDs are backwards with respect to each other. DS7
296 * is on the board edge side of both the LED strip and the DS0-DS7
297 * switch.
298 */
299#undef CONFIG_MISC_INIT_R
300
301/* Set to a positive value to delay for running BOOTCOMMAND */
302#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
303
304/* Be selective on what keys can delay or stop the autoboot process
305 * To stop use: " "
306 */
307#undef CONFIG_AUTOBOOT_KEYED
308#ifdef CONFIG_AUTOBOOT_KEYED
309# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
310# define CONFIG_AUTOBOOT_STOP_STR " "
311# undef CONFIG_AUTOBOOT_DELAY_STR
312# define DEBUG_BOOTKEYS 0
wdenk466b7412004-07-10 22:35:59 +0000313#endif
wdenk466b7412004-07-10 22:35:59 +0000314
wdenk10a36a92004-07-10 23:02:23 +0000315/* Define this to contain any number of null terminated strings that
316 * will be part of the default enviroment compiled into the boot image.
317 *
318 * Variable Usage
319 * -------------- -------------------------------------------------------
320 * serverip server IP address
321 * ipaddr my IP address
322 * reprog Reload flash with a new copy of U-Boot
323 * zapenv Erase the environment area in flash
324 * root-on-initrd Set the bootcmd variable to allow booting of an initial
325 * ram disk.
326 * root-on-nfs Set the bootcmd variable to allow booting of a NFS
327 * mounted root filesystem.
328 * boot-hook Convenient stub to do something useful before the
329 * bootm command is executed.
330 *
331 * Example usage of root-on-initrd and root-on-nfs :
332 *
333 * Note: The lines have been wrapped to improved its readability.
334 *
335 * => printenv bootcmd
336 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100337 * nfsroot=${serverip}:${rootpath}
338 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
wdenk10a36a92004-07-10 23:02:23 +0000339 *
340 * => run root-on-initrd
341 * => printenv bootcmd
342 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100343 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
wdenk10a36a92004-07-10 23:02:23 +0000344 *
345 * => run root-on-nfs
346 * => printenv bootcmd
347 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100348 * nfsroot=${serverip}:${rootpath}
349 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
wdenk10a36a92004-07-10 23:02:23 +0000350 *
351 */
352#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkb9283e22004-07-11 21:49:42 +0000353 "serverip=192.168.123.205\0" \
wdenk10a36a92004-07-10 23:02:23 +0000354 "ipaddr=192.168.123.213\0" \
355 "reprog="\
356 "bootp;" \
357 "tftpboot 0x140000 /bdi2000/u-boot.bin;" \
358 "protect off 1:0;" \
359 "erase 1:0;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100360 "cp.b 140000 40000000 ${filesize};" \
wdenk10a36a92004-07-10 23:02:23 +0000361 "protect on 1:0\0" \
362 "zapenv="\
363 "protect off 1:1;" \
364 "erase 1:1;" \
365 "protect on 1:1\0" \
366 "root-on-initrd="\
367 "setenv bootcmd "\
368 "version;" \
369 "echo;" \
370 "bootp;" \
371 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100372 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000373 "run boot-hook;" \
374 "bootm\0" \
375 "root-on-nfs="\
376 "setenv bootcmd "\
377 "version;" \
378 "echo;" \
379 "bootp;" \
380 "setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100381 "nfsroot=${serverip}:${rootpath} " \
382 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000383 "run boot-hook;" \
384 "bootm\0" \
385 "boot-hook=echo\0"
wdenk466b7412004-07-10 22:35:59 +0000386
wdenk10a36a92004-07-10 23:02:23 +0000387/* Define a command string that is automatically executed when no character
388 * is read on the console interface withing "Boot Delay" after reset.
389 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200390#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
wdenk10a36a92004-07-10 23:02:23 +0000391#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenk466b7412004-07-10 22:35:59 +0000392
wdenk10a36a92004-07-10 23:02:23 +0000393#ifdef CONFIG_BOOT_ROOT_INITRD
394#define CONFIG_BOOTCOMMAND \
395 "version;" \
396 "echo;" \
397 "bootp;" \
398 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100399 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000400 "bootm"
401#endif /* CONFIG_BOOT_ROOT_INITRD */
402
403#ifdef CONFIG_BOOT_ROOT_NFS
404#define CONFIG_BOOTCOMMAND \
405 "version;" \
406 "echo;" \
407 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100408 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
409 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000410 "bootm"
411#endif /* CONFIG_BOOT_ROOT_NFS */
412
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500413/*
414 * BOOTP options
wdenk10a36a92004-07-10 23:02:23 +0000415 */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500416#define CONFIG_BOOTP_SUBNETMASK
417#define CONFIG_BOOTP_GATEWAY
418#define CONFIG_BOOTP_HOSTNAME
419#define CONFIG_BOOTP_BOOTPATH
420#define CONFIG_BOOTP_BOOTFILESIZE
421#define CONFIG_BOOTP_DNS
422#define CONFIG_BOOTP_DNS2
423#define CONFIG_BOOTP_SEND_HOSTNAME
424
wdenk10a36a92004-07-10 23:02:23 +0000425
426/* undef this to save memory */
427#define CFG_LONGHELP
428
429/* Monitor Command Prompt */
430#define CFG_PROMPT "=> "
431
432#undef CFG_HUSH_PARSER
433#ifdef CFG_HUSH_PARSER
434#define CFG_PROMPT_HUSH_PS2 "> "
435#endif
436
437/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
438 * of an image is printed by image commands like bootm or iminfo.
439 */
440#define CONFIG_TIMESTAMP
441
442/* If this variable is defined, an environment variable named "ver"
443 * is created by U-Boot showing the U-Boot version.
444 */
445#define CONFIG_VERSION_VARIABLE
446
Jon Loeliger866e3082007-07-04 22:30:58 -0500447
448/*
449 * Command line configuration.
450 */
451#include <config_cmd_default.h>
452
453#define CONFIG_CMD_ASKENV
454#define CONFIG_CMD_ELF
455#define CONFIG_CMD_I2C
456#define CONFIG_CMD_IMMAP
457#define CONFIG_CMD_PING
458#define CONFIG_CMD_REGINFO
459#define CONFIG_CMD_SDRAM
460
461#undef CONFIG_CMD_KGDB
462
463#if defined(CONFIG_ETHER_ON_FCC)
464 #define CONFIG_CMD_CMD_MII
465#endif
466
wdenk466b7412004-07-10 22:35:59 +0000467
wdenk10a36a92004-07-10 23:02:23 +0000468#undef CONFIG_WATCHDOG /* disable the watchdog */
wdenk466b7412004-07-10 22:35:59 +0000469
wdenk10a36a92004-07-10 23:02:23 +0000470/* Where do the internal registers live? */
471#define CFG_IMMR 0xF0000000
wdenk466b7412004-07-10 22:35:59 +0000472
wdenk10a36a92004-07-10 23:02:23 +0000473/*****************************************************************************
474 *
475 * You should not have to modify any of the following settings
476 *
477 *****************************************************************************/
wdenk466b7412004-07-10 22:35:59 +0000478
wdenk10a36a92004-07-10 23:02:23 +0000479#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
480#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500481#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk466b7412004-07-10 22:35:59 +0000482
wdenkfe8c2802002-11-03 00:38:21 +0000483
484/*
485 * Miscellaneous configurable options
486 */
Jon Loeliger866e3082007-07-04 22:30:58 -0500487#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000488# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000489#else
wdenk10a36a92004-07-10 23:02:23 +0000490# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000491#endif
wdenk10a36a92004-07-10 23:02:23 +0000492
493/* Print Buffer Size */
494#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
495
496#define CFG_MAXARGS 32 /* max number of command args */
497
498#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
499
500#define CFG_LOAD_ADDR 0x400000 /* default load address */
501#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
502
503#define CFG_ALT_MEMTEST /* Select full-featured memory test */
504#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
505 /* the exception vector table */
506 /* to the end of the DRAM */
507 /* less monitor and malloc area */
508#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
509#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
510 + CFG_MALLOC_LEN \
511 + CFG_ENV_SECT_SIZE \
512 + CFG_STACK_USAGE )
513
514#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
515 - CFG_MEM_END_USAGE )
516
517/* valid baudrates */
518#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
519
520/*
521 * Low Level Configuration Settings
522 * (address mappings, register initial values, etc.)
523 * You should know what you are doing if you make changes here.
524 */
525
526#define CFG_FLASH_BASE CFG_FLASH0_BASE
527#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
528#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
529#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
530
531/*-----------------------------------------------------------------------
532 * Hard Reset Configuration Words
533 */
534#if defined(CFG_SBC_BOOT_LOW)
535# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
536#else
537# define CFG_SBC_HRCW_BOOT_FLAGS (0)
538#endif /* defined(CFG_SBC_BOOT_LOW) */
539
540/* get the HRCW ISB field from CFG_IMMR */
541#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
542 ((CFG_IMMR & 0x01000000) >> 7) | \
543 ((CFG_IMMR & 0x00100000) >> 4) )
544
545#define CFG_HRCW_MASTER ( HRCW_BPS11 | \
546 HRCW_DPPC11 | \
547 CFG_SBC_HRCW_IMMR | \
548 HRCW_MMR00 | \
549 HRCW_LBPC11 | \
550 HRCW_APPC10 | \
551 HRCW_CS10PC00 | \
552 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
553 CFG_SBC_HRCW_BOOT_FLAGS )
554
555/* no slaves */
556#define CFG_HRCW_SLAVE1 0
557#define CFG_HRCW_SLAVE2 0
558#define CFG_HRCW_SLAVE3 0
559#define CFG_HRCW_SLAVE4 0
560#define CFG_HRCW_SLAVE5 0
561#define CFG_HRCW_SLAVE6 0
562#define CFG_HRCW_SLAVE7 0
563
564/*-----------------------------------------------------------------------
565 * Definitions for initial stack pointer and data area (in DPRAM)
566 */
567#define CFG_INIT_RAM_ADDR CFG_IMMR
568#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
569#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
570#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
571#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
572
573/*-----------------------------------------------------------------------
574 * Start addresses for the final memory configuration
575 * (Set up by the startup code)
576 * Please note that CFG_SDRAM_BASE _must_ start at 0
577 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
578 */
579#define CFG_MONITOR_BASE CFG_FLASH0_BASE
580
581#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
582# define CFG_RAMBOOT
583#endif
584
585#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
586#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000587
588/*
589 * For booting Linux, the board info and command line data
590 * have to be in the first 8 MB of memory, since this is
591 * the maximum mapped by the Linux kernel during initialization.
592 */
wdenk10a36a92004-07-10 23:02:23 +0000593#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000594
wdenk10a36a92004-07-10 23:02:23 +0000595/*-----------------------------------------------------------------------
596 * FLASH and environment organization
597 */
598#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
599#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
600
601#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
602#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
603
604#ifndef CFG_RAMBOOT
605# define CFG_ENV_IS_IN_FLASH 1
606
607# ifdef CFG_ENV_IN_OWN_SECT
608# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
609# define CFG_ENV_SECT_SIZE 0x40000
610# else
611# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
612# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
613# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
614# endif /* CFG_ENV_IN_OWN_SECT */
615
616#else
617# define CFG_ENV_IS_IN_NVRAM 1
618# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
619# define CFG_ENV_SIZE 0x200
620#endif /* CFG_RAMBOOT */
621
622/*-----------------------------------------------------------------------
623 * Cache Configuration
624 */
625#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
626
Jon Loeliger866e3082007-07-04 22:30:58 -0500627#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000628# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkfe8c2802002-11-03 00:38:21 +0000629#endif
630
wdenk10a36a92004-07-10 23:02:23 +0000631/*-----------------------------------------------------------------------
632 * HIDx - Hardware Implementation-dependent Registers 2-11
633 *-----------------------------------------------------------------------
634 * HID0 also contains cache control - initially enable both caches and
635 * invalidate contents, then the final state leaves only the instruction
636 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
637 * but Soft reset does not.
638 *
639 * HID1 has only read-only information - nothing to set.
640 */
641#define CFG_HID0_INIT (HID0_ICE |\
642 HID0_DCE |\
643 HID0_ICFI |\
644 HID0_DCI |\
645 HID0_IFEM |\
646 HID0_ABE)
647
648#define CFG_HID0_FINAL (HID0_ICE |\
649 HID0_IFEM |\
650 HID0_ABE |\
651 HID0_EMCP)
652#define CFG_HID2 0
653
654/*-----------------------------------------------------------------------
655 * RMR - Reset Mode Register
656 *-----------------------------------------------------------------------
657 */
658#define CFG_RMR 0
659
660/*-----------------------------------------------------------------------
661 * BCR - Bus Configuration 4-25
662 *-----------------------------------------------------------------------
663 */
664#define CFG_BCR (BCR_ETM)
665
666/*-----------------------------------------------------------------------
667 * SIUMCR - SIU Module Configuration 4-31
668 *-----------------------------------------------------------------------
669 */
670
671#define CFG_SIUMCR (SIUMCR_DPPC11 |\
672 SIUMCR_L2CPC00 |\
673 SIUMCR_APPC10 |\
674 SIUMCR_MMR00)
675
676
677/*-----------------------------------------------------------------------
678 * SYPCR - System Protection Control 11-9
679 * SYPCR can only be written once after reset!
680 *-----------------------------------------------------------------------
681 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
682 */
683#if defined(CONFIG_WATCHDOG)
684#define CFG_SYPCR (SYPCR_SWTC |\
685 SYPCR_BMT |\
686 SYPCR_PBME |\
687 SYPCR_LBME |\
688 SYPCR_SWRI |\
689 SYPCR_SWP |\
690 SYPCR_SWE)
691#else
692#define CFG_SYPCR (SYPCR_SWTC |\
693 SYPCR_BMT |\
694 SYPCR_PBME |\
695 SYPCR_LBME |\
696 SYPCR_SWRI |\
697 SYPCR_SWP)
698#endif /* CONFIG_WATCHDOG */
699
700/*-----------------------------------------------------------------------
701 * TMCNTSC - Time Counter Status and Control 4-40
702 *-----------------------------------------------------------------------
703 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
704 * and enable Time Counter
705 */
706#define CFG_TMCNTSC (TMCNTSC_SEC |\
707 TMCNTSC_ALR |\
708 TMCNTSC_TCF |\
709 TMCNTSC_TCE)
710
711/*-----------------------------------------------------------------------
712 * PISCR - Periodic Interrupt Status and Control 4-42
713 *-----------------------------------------------------------------------
714 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
715 * Periodic timer
716 */
717#define CFG_PISCR (PISCR_PS |\
718 PISCR_PTF |\
719 PISCR_PTE)
720
721/*-----------------------------------------------------------------------
722 * SCCR - System Clock Control 9-8
723 *-----------------------------------------------------------------------
724 */
725#define CFG_SCCR 0
726
727/*-----------------------------------------------------------------------
728 * RCCR - RISC Controller Configuration 13-7
729 *-----------------------------------------------------------------------
730 */
731#define CFG_RCCR 0
732
733/*
734 * Initialize Memory Controller:
735 *
736 * Bank Bus Machine PortSz Device
737 * ---- --- ------- ------ ------
738 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) *
739 * 1 60x GPCM 32 bit FLASH (SIMM - Unused)
740 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
741 * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused)
742 * 4 Local SDRAM 32 bit SDRAM (on board - 4MB)
743 * 5 60x GPCM 8 bit EEPROM (8KB)
744 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
745 * 7 60x GPCM 8 bit LEDs, switches
746 *
747 * (*) This configuration requires the SBC8260 be configured
748 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
749 * the on board FLASH. In other words, JP24 should have
750 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
751 *
752 */
753
754/*-----------------------------------------------------------------------
755 * BR0,BR1 - Base Register
756 * Ref: Section 10.3.1 on page 10-14
757 * OR0,OR1 - Option Register
758 * Ref: Section 10.3.2 on page 10-18
759 *-----------------------------------------------------------------------
760 */
761
762/* Bank 0,1 - FLASH SIMM
763 *
764 * This expects the FLASH SIMM to be connected to *CS0
765 * It consists of 4 AM29F080B parts.
766 *
767 * Note: For the 4 MB SIMM, *CS1 is unused.
768 */
769
770/* BR0 is configured as follows:
771 *
772 * - Base address of 0x40000000
773 * - 32 bit port size
774 * - Data errors checking is disabled
775 * - Read and write access
776 * - GPCM 60x bus
777 * - Access are handled by the memory controller according to MSEL
778 * - Not used for atomic operations
779 * - No data pipelining is done
780 * - Valid
781 */
782#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
783 BRx_PS_32 |\
784 BRx_MS_GPCM_P |\
785 BRx_V)
786
787/* OR0 is configured as follows:
788 *
789 * - 4 MB
790 * - *BCTL0 is asserted upon access to the current memory bank
791 * - *CW / *WE are negated a quarter of a clock earlier
792 * - *CS is output at the same time as the address lines
793 * - Uses a clock cycle length of 5
794 * - *PSDVAL is generated internally by the memory controller
795 * unless *GTA is asserted earlier externally.
796 * - Relaxed timing is generated by the GPCM for accesses
797 * initiated to this memory region.
798 * - One idle clock is inserted between a read access from the
799 * current bank and the next access.
800 */
801#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
802 ORxG_CSNT |\
803 ORxG_ACS_DIV1 |\
804 ORxG_SCY_5_CLK |\
805 ORxG_TRLX |\
806 ORxG_EHTR)
807
808/*-----------------------------------------------------------------------
809 * BR2,BR3 - Base Register
810 * Ref: Section 10.3.1 on page 10-14
811 * OR2,OR3 - Option Register
812 * Ref: Section 10.3.2 on page 10-16
813 *-----------------------------------------------------------------------
814 */
815
816/* Bank 2,3 - SDRAM DIMM
817 *
818 * 16MB DIMM: P/N
819 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST
820 *
821 * Note: *CS3 is unused for this DIMM
822 */
823
824/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
825 *
826 * - Base address of 0x00000000
827 * - 64 bit port size (60x bus only)
828 * - Data errors checking is disabled
829 * - Read and write access
830 * - SDRAM 60x bus
831 * - Access are handled by the memory controller according to MSEL
832 * - Not used for atomic operations
833 * - No data pipelining is done
834 * - Valid
835 */
836#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
837 BRx_PS_64 |\
838 BRx_MS_SDRAM_P |\
839 BRx_V)
840
841#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
842 BRx_PS_64 |\
843 BRx_MS_SDRAM_P |\
844 BRx_V)
845
846/* With a 16 MB DIMM, the OR2 is configured as follows:
847 *
848 * - 16 MB
849 * - 2 internal banks per device
850 * - Row start address bit is A9 with PSDMR[PBI] = 0
851 * - 11 row address lines
852 * - Back-to-back page mode
853 * - Internal bank interleaving within save device enabled
854 */
855#if (CFG_SDRAM0_SIZE == 16)
856#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
857 ORxS_BPD_2 |\
858 ORxS_ROWST_PBI0_A9 |\
859 ORxS_NUMR_11)
860#endif
861
862/* With a 64 MB DIMM, the OR2 is configured as follows:
863 *
864 * - 64 MB
865 * - 4 internal banks per device
866 * - Row start address bit is A8 with PSDMR[PBI] = 0
867 * - 12 row address lines
868 * - Back-to-back page mode
869 * - Internal bank interleaving within save device enabled
870 */
871#if (CFG_SDRAM0_SIZE == 64)
872#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
873 ORxS_BPD_4 |\
874 ORxS_ROWST_PBI0_A8 |\
875 ORxS_NUMR_12)
876#endif
877
878/*-----------------------------------------------------------------------
879 * PSDMR - 60x Bus SDRAM Mode Register
880 * Ref: Section 10.3.3 on page 10-21
881 *-----------------------------------------------------------------------
882 */
883
884/* Address that the DIMM SPD memory lives at.
885 */
886#define SDRAM_SPD_ADDR 0x54
887
888#if (CFG_SDRAM0_SIZE == 16)
889/* With a 16 MB DIMM, the PSDMR is configured as follows:
890 *
891 * - Bank Based Interleaving,
892 * - Refresh Enable,
893 * - Address Multiplexing where A5 is output on A14 pin
894 * (A6 on A15, and so on),
895 * - use address pins A16-A18 as bank select,
896 * - A9 is output on SDA10 during an ACTIVATE command,
897 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
898 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
899 * is 3 clocks,
900 * - earliest timing for READ/WRITE command after ACTIVATE command is
901 * 2 clocks,
902 * - earliest timing for PRECHARGE after last data was read is 1 clock,
903 * - earliest timing for PRECHARGE after last data was written is 1 clock,
904 * - CAS Latency is 2.
905 */
906#define CFG_PSDMR (PSDMR_RFEN |\
907 PSDMR_SDAM_A14_IS_A5 |\
908 PSDMR_BSMA_A16_A18 |\
909 PSDMR_SDA10_PBI0_A9 |\
910 PSDMR_RFRC_7_CLK |\
911 PSDMR_PRETOACT_3W |\
912 PSDMR_ACTTORW_2W |\
913 PSDMR_LDOTOPRE_1C |\
914 PSDMR_WRC_1C |\
915 PSDMR_CL_2)
916#endif
917
918#if (CFG_SDRAM0_SIZE == 64)
919/* With a 64 MB DIMM, the PSDMR is configured as follows:
920 *
921 * - Bank Based Interleaving,
922 * - Refresh Enable,
923 * - Address Multiplexing where A5 is output on A14 pin
924 * (A6 on A15, and so on),
925 * - use address pins A14-A16 as bank select,
926 * - A9 is output on SDA10 during an ACTIVATE command,
927 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
928 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
929 * is 3 clocks,
930 * - earliest timing for READ/WRITE command after ACTIVATE command is
931 * 2 clocks,
932 * - earliest timing for PRECHARGE after last data was read is 1 clock,
933 * - earliest timing for PRECHARGE after last data was written is 1 clock,
934 * - CAS Latency is 2.
935 */
936#define CFG_PSDMR (PSDMR_RFEN |\
937 PSDMR_SDAM_A14_IS_A5 |\
938 PSDMR_BSMA_A14_A16 |\
939 PSDMR_SDA10_PBI0_A9 |\
940 PSDMR_RFRC_7_CLK |\
941 PSDMR_PRETOACT_3W |\
942 PSDMR_ACTTORW_2W |\
943 PSDMR_LDOTOPRE_1C |\
944 PSDMR_WRC_1C |\
945 PSDMR_CL_2)
946#endif
947
948/*
949 * Shoot for approximately 1MHz on the prescaler.
950 */
951#if (CONFIG_8260_CLKIN == (66 * 1000 * 1000))
952#define CFG_MPTPR MPTPR_PTP_DIV64
953#elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000))
954#define CFG_MPTPR MPTPR_PTP_DIV32
955#else
956#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
957#define CFG_MPTPR MPTPR_PTP_DIV32
958#endif
959#define CFG_PSRT 14
960
961
962/* Bank 4 - On board SDRAM
963 *
964 * This is not implemented yet.
965 */
966
967/*-----------------------------------------------------------------------
968 * BR6 - Base Register
969 * Ref: Section 10.3.1 on page 10-14
970 * OR6 - Option Register
971 * Ref: Section 10.3.2 on page 10-18
972 *-----------------------------------------------------------------------
973 */
974
975/* Bank 6 - On board FLASH
976 *
977 * This expects the on board FLASH SIMM to be connected to *CS6
978 * It consists of 1 AM29F016A part.
979 */
980#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
981
982/* BR6 is configured as follows:
983 *
984 * - Base address of 0x60000000
985 * - 8 bit port size
986 * - Data errors checking is disabled
987 * - Read and write access
988 * - GPCM 60x bus
989 * - Access are handled by the memory controller according to MSEL
990 * - Not used for atomic operations
991 * - No data pipelining is done
992 * - Valid
993 */
994# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
995 BRx_PS_8 |\
996 BRx_MS_GPCM_P |\
997 BRx_V)
998
999/* OR6 is configured as follows:
1000 *
1001 * - 2 MB
1002 * - *BCTL0 is asserted upon access to the current memory bank
1003 * - *CW / *WE are negated a quarter of a clock earlier
1004 * - *CS is output at the same time as the address lines
1005 * - Uses a clock cycle length of 5
1006 * - *PSDVAL is generated internally by the memory controller
1007 * unless *GTA is asserted earlier externally.
1008 * - Relaxed timing is generated by the GPCM for accesses
1009 * initiated to this memory region.
1010 * - One idle clock is inserted between a read access from the
1011 * current bank and the next access.
1012 */
1013# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
1014 ORxG_CSNT |\
1015 ORxG_ACS_DIV1 |\
1016 ORxG_SCY_5_CLK |\
1017 ORxG_TRLX |\
1018 ORxG_EHTR)
1019#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
1020
1021/*-----------------------------------------------------------------------
1022 * BR7 - Base Register
1023 * Ref: Section 10.3.1 on page 10-14
1024 * OR7 - Option Register
1025 * Ref: Section 10.3.2 on page 10-18
1026 *-----------------------------------------------------------------------
1027 */
1028
1029/* Bank 7 - LEDs and switches
1030 *
1031 * LEDs are at 0x00001 (write only)
1032 * switches are at 0x00001 (read only)
1033 */
1034#ifdef CFG_LED_BASE
1035
1036/* BR7 is configured as follows:
1037 *
1038 * - Base address of 0xA0000000
1039 * - 8 bit port size
1040 * - Data errors checking is disabled
1041 * - Read and write access
1042 * - GPCM 60x bus
1043 * - Access are handled by the memory controller according to MSEL
1044 * - Not used for atomic operations
1045 * - No data pipelining is done
1046 * - Valid
1047 */
1048# define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
1049 BRx_PS_8 |\
1050 BRx_MS_GPCM_P |\
1051 BRx_V)
1052
1053/* OR7 is configured as follows:
1054 *
1055 * - 1 byte
1056 * - *BCTL0 is asserted upon access to the current memory bank
1057 * - *CW / *WE are negated a quarter of a clock earlier
1058 * - *CS is output at the same time as the address lines
1059 * - Uses a clock cycle length of 15
1060 * - *PSDVAL is generated internally by the memory controller
1061 * unless *GTA is asserted earlier externally.
1062 * - Relaxed timing is generated by the GPCM for accesses
1063 * initiated to this memory region.
1064 * - One idle clock is inserted between a read access from the
1065 * current bank and the next access.
1066 */
1067# define CFG_OR7_PRELIM (ORxG_AM_MSK |\
1068 ORxG_CSNT |\
1069 ORxG_ACS_DIV1 |\
1070 ORxG_SCY_15_CLK |\
1071 ORxG_TRLX |\
1072 ORxG_EHTR)
1073#endif /* CFG_LED_BASE */
1074
wdenkfe8c2802002-11-03 00:38:21 +00001075/*
1076 * Internal Definitions
1077 *
1078 * Boot Flags
1079 */
wdenk10a36a92004-07-10 23:02:23 +00001080#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1081#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenkfe8c2802002-11-03 00:38:21 +00001082
1083#endif /* __CONFIG_H */