blob: b9c57132d7ae898f2b4bbd82db40054b8d7fd81b [file] [log] [blame]
wdenke2211742002-11-02 23:30:20 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenke2211742002-11-02 23:30:20 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_IP860 1 /* ...on a IP860 board */
wdenkc837dcb2004-01-20 23:12:12 +000038#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenke2211742002-11-02 23:30:20 +000039
40#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
41#define CONFIG_BAUDRATE 9600
42#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
43
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010044#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010045"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
wdenke2211742002-11-02 23:30:20 +000046
wdenke2211742002-11-02 23:30:20 +000047#undef CONFIG_BOOTARGS
48#define CONFIG_BOOTCOMMAND \
49 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010050 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
51 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenke2211742002-11-02 23:30:20 +000052 "bootm"
53
54#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke2211742002-11-02 23:30:20 +000056
57#undef CONFIG_WATCHDOG /* watchdog disabled */
58
59
60/* enable I2C and select the hardware/software driver */
61#undef CONFIG_HARD_I2C /* I2C with hardware support */
62#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
63/*
64 * Software (bit-bang) I2C driver configuration
65 */
66#define PB_SCL 0x00000020 /* PB 26 */
67#define PB_SDA 0x00000010 /* PB 27 */
68
69#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
70#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
71#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
72#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
73#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
74 else immr->im_cpm.cp_pbdat &= ~PB_SDA
75#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
76 else immr->im_cpm.cp_pbdat &= ~PB_SCL
77#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
78
79
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080# define CONFIG_SYS_I2C_SPEED 50000
81# define CONFIG_SYS_I2C_SLAVE 0xFE
82# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
83# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenke2211742002-11-02 23:30:20 +000084/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
86#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
87#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
wdenke2211742002-11-02 23:30:20 +000088
wdenk414eec32005-04-02 22:37:54 +000089#define CONFIG_TIMESTAMP /* Print image info with timestamp */
90
Jon Loeliger348f2582007-07-08 13:46:18 -050091
92/*
93 * Command line configuration.
94 */
95#include <config_cmd_default.h>
96
97#define CONFIG_CMD_BEDBUG
98#define CONFIG_CMD_I2C
99#define CONFIG_CMD_EEPROM
100#define CONFIG_CMD_NFS
101#define CONFIG_CMD_SNTP
wdenke2211742002-11-02 23:30:20 +0000102
Jon Loeliger7be044e2007-07-09 21:24:19 -0500103/*
104 * BOOTP options
105 */
106#define CONFIG_BOOTP_SUBNETMASK
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109#define CONFIG_BOOTP_BOOTPATH
wdenke2211742002-11-02 23:30:20 +0000110
wdenke2211742002-11-02 23:30:20 +0000111/*
112 * Miscellaneous configurable options
113 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LONGHELP /* undef to save memory */
115#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500116#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000118#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000120#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
122#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
123#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
126#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
wdenke2211742002-11-02 23:30:20 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +0000135
136/*
137 * Low Level Configuration Settings
138 * (address mappings, register initial values, etc.)
139 * You should know what you are doing if you make changes here.
140 */
141/*-----------------------------------------------------------------------
142 * Internal Memory Mapped Register
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_IMMR 0xF1000000 /* Non-standard value!! */
wdenke2211742002-11-02 23:30:20 +0000145
146/*-----------------------------------------------------------------------
147 * Definitions for initial stack pointer and data area (in DPRAM)
148 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
150#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
151#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
152#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
153#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000154
155/*-----------------------------------------------------------------------
156 * Start addresses for the final memory configuration
157 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_SDRAM_BASE 0x00000000
161#define CONFIG_SYS_FLASH_BASE 0x10000000
wdenke2211742002-11-02 23:30:20 +0000162#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
wdenke2211742002-11-02 23:30:20 +0000164#else
165#if 0 /* need more space for I2C tests */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
wdenke2211742002-11-02 23:30:20 +0000167#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_MONITOR_LEN (256 << 10)
wdenke2211742002-11-02 23:30:20 +0000169#endif
170#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
172#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000173
174/*
175 * For booting Linux, the board info and command line data
176 * have to be in the first 8 MB of memory, since this is
177 * the maximum mapped by the Linux kernel during initialization.
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000180/*-----------------------------------------------------------------------
181 * FLASH organization
182 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
184#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
187#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000188
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200189#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200190#undef CONFIG_ENV_IS_IN_NVRAM
191#undef CONFIG_ENV_IS_IN_NVRAM
wdenke2211742002-11-02 23:30:20 +0000192#undef DEBUG_I2C
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200193#define CONFIG_ENV_IS_IN_EEPROM
wdenke2211742002-11-02 23:30:20 +0000194
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200195#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200196#define CONFIG_ENV_ADDR 0x20000000 /* use SRAM */
197#define CONFIG_ENV_SIZE (16<<10) /* use 16 kB */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200198#endif /* CONFIG_ENV_IS_IN_NVRAM */
wdenke2211742002-11-02 23:30:20 +0000199
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200200#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200201#define CONFIG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */
202#define CONFIG_ENV_SIZE 1536 /* Use remaining space */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200203#endif /* CONFIG_ENV_IS_IN_EEPROM */
wdenke2211742002-11-02 23:30:20 +0000204
205/*-----------------------------------------------------------------------
206 * Cache Configuration
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500209#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000211#endif
212
213/*-----------------------------------------------------------------------
214 * SYPCR - System Protection Control 11-9
215 * SYPCR can only be written once after reset!
216 *-----------------------------------------------------------------------
217 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
218 * +0x0004
219 */
220#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke2211742002-11-02 23:30:20 +0000222 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
223#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenke2211742002-11-02 23:30:20 +0000225#endif
226
227/*-----------------------------------------------------------------------
228 * SIUMCR - SIU Module Configuration 11-6
229 *-----------------------------------------------------------------------
230 * +0x0000 => 0x80600800
231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \
wdenke2211742002-11-02 23:30:20 +0000233 SIUMCR_DBGC11 | SIUMCR_MLRC10)
234
235/*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000236 * Clock Setting - get clock frequency from Board Revision Register
wdenke2211742002-11-02 23:30:20 +0000237 *-----------------------------------------------------------------------
238 */
wdenk3bac3512003-03-12 10:41:04 +0000239#ifndef __ASSEMBLY__
240extern unsigned long ip860_get_clk_freq (void);
241#endif
242#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq()
wdenke2211742002-11-02 23:30:20 +0000243
244/*-----------------------------------------------------------------------
245 * TBSCR - Time Base Status and Control 11-26
246 *-----------------------------------------------------------------------
247 * Clear Reference Interrupt Status, Timebase freezing enabled
248 * +0x0200 => 0x00C2
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenke2211742002-11-02 23:30:20 +0000251
252/*-----------------------------------------------------------------------
253 * PISCR - Periodic Interrupt Status and Control 11-31
254 *-----------------------------------------------------------------------
255 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
256 * +0x0240 => 0x0082
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenke2211742002-11-02 23:30:20 +0000259
260/*-----------------------------------------------------------------------
261 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
262 *-----------------------------------------------------------------------
263 * Reset PLL lock status sticky bit, timer expired status bit and timer
264 * interrupt status bit, set PLL multiplication factor !
265 */
266/* +0x0286 => was: 0x0000D000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PLPRCR \
wdenke2211742002-11-02 23:30:20 +0000268 ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
269 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
270 PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
271 )
272
273/*-----------------------------------------------------------------------
274 * SCCR - System Clock and reset Control Register 15-27
275 *-----------------------------------------------------------------------
276 * Set clock output, timebase and RTC source and divider,
277 * power management and some other internal clocks
278 */
279#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS | \
wdenke2211742002-11-02 23:30:20 +0000281 SCCR_RTDIV | SCCR_RTSEL | \
282 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
283 SCCR_EBDF00 | SCCR_DFSYNC00 | \
284 SCCR_DFBRG00 | SCCR_DFNL000 | \
285 SCCR_DFNH000)
286
287/*-----------------------------------------------------------------------
288 * RTCSC - Real-Time Clock Status and Control Register 11-27
289 *-----------------------------------------------------------------------
290 */
291/* +0x0220 => 0x00C3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenke2211742002-11-02 23:30:20 +0000293
294
295/*-----------------------------------------------------------------------
296 * RCCR - RISC Controller Configuration Register 19-4
297 *-----------------------------------------------------------------------
298 */
299/* +0x09C4 => TIMEP=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_RCCR 0x0100
wdenke2211742002-11-02 23:30:20 +0000301
302/*-----------------------------------------------------------------------
303 * RMDS - RISC Microcode Development Support Control Register
304 *-----------------------------------------------------------------------
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_RMDS 0
wdenke2211742002-11-02 23:30:20 +0000307
308/*-----------------------------------------------------------------------
309 * DER - Debug Event Register
310 *-----------------------------------------------------------------------
311 *
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_DER 0
wdenke2211742002-11-02 23:30:20 +0000314
315/*
316 * Init Memory Controller:
317 */
318
319/*
320 * MAMR settings for SDRAM - 16-14
321 * => 0xC3804114
322 */
323
324/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_MAMR_PTA 0xC3
wdenke2211742002-11-02 23:30:20 +0000326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke2211742002-11-02 23:30:20 +0000328 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
329 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
330/*
331 * BR1 and OR1 (FLASH)
332 */
333#define FLASH_BASE 0x10000000 /* FLASH bank #0 */
334
335/* used to re-map FLASH
336 * restrict access enough to keep SRAM working (if any)
337 * but not too much to meddle with FLASH accesses
338 */
339/* allow for max 8 MB of Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
341#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
wdenke2211742002-11-02 23:30:20 +0000342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
wdenke2211742002-11-02 23:30:20 +0000344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
346#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
wdenke2211742002-11-02 23:30:20 +0000347/* 16 bit, bank valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
wdenke2211742002-11-02 23:30:20 +0000349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
351#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_BR0_PRELIM
wdenke2211742002-11-02 23:30:20 +0000352
353/*
354 * BR2/OR2 - SDRAM
355 */
356#define SDRAM_BASE 0x00000000 /* SDRAM bank */
357#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
358#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
359
360#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
363#define CONFIG_SYS_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke2211742002-11-02 23:30:20 +0000364
365/*
366 * BR3/OR3 - SRAM (16 bit)
367 */
368#define SRAM_BASE 0x20000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
370#define CONFIG_SYS_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
371#define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
372#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */
373#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */
wdenke2211742002-11-02 23:30:20 +0000374
375/*
376 * BR4/OR4 - Board Control & Status (8 bit)
377 */
378#define BCSR_BASE 0xFC000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_OR4 0xFFFF0120 /* BI (internal) */
380#define CONFIG_SYS_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000381
382/*
383 * BR5/OR5 - IP Slot A/B (16 bit)
384 */
385#define IP_SLOT_BASE 0x40000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
387#define CONFIG_SYS_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000388
389/*
390 * BR6/OR6 - VME STD (16 bit)
391 */
392#define VME_STD_BASE 0xFE000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
394#define CONFIG_SYS_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000395
396/*
397 * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
398 */
399#define VME_SHORT_BASE 0xFF000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
401#define CONFIG_SYS_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
wdenke2211742002-11-02 23:30:20 +0000402
403/*-----------------------------------------------------------------------
404 * Board Control and Status Region:
405 *-----------------------------------------------------------------------
406 */
407#ifndef __ASSEMBLY__
408typedef struct ip860_bcsr_s {
409 unsigned char shmem_addr; /* +00 shared memory address register */
410 unsigned char reserved0;
411 unsigned char mbox_addr; /* +02 mailbox address register */
412 unsigned char reserved1;
413 unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */
414 unsigned char reserved2;
415 unsigned char vme_int_pend; /* +06 VME interrupt pending register */
416 unsigned char reserved3;
417 unsigned char bd_int_mask; /* +08 board interrupt mask register */
418 unsigned char reserved4;
419 unsigned char bd_int_pend; /* +0A board interrupt pending register */
420 unsigned char reserved5;
421 unsigned char bd_ctrl; /* +0C board control register */
422 unsigned char reserved6;
423 unsigned char bd_status; /* +0E board status register */
424 unsigned char reserved7;
425 unsigned char vme_irq; /* +10 VME interrupt request register */
426 unsigned char reserved8;
427 unsigned char vme_ivec; /* +12 VME interrupt vector register */
428 unsigned char reserved9;
429 unsigned char cli_mbox; /* +14 clear mailbox irq */
430 unsigned char reservedA;
431 unsigned char rtc; /* +16 RTC control register */
432 unsigned char reservedB;
433 unsigned char mbox_data; /* +18 mailbox read/write register */
434 unsigned char reservedC;
435 unsigned char wd_trigger; /* +1A Watchdog trigger register */
436 unsigned char reservedD;
437 unsigned char rmw_req; /* +1C RMW request register */
wdenk3bac3512003-03-12 10:41:04 +0000438 unsigned char reservedE;
439 unsigned char bd_rev; /* +1E Board Revision register */
wdenke2211742002-11-02 23:30:20 +0000440} ip860_bcsr_t;
441#endif /* __ASSEMBLY__ */
442
443/*-----------------------------------------------------------------------
444 * Board Control Register: bd_ctrl (Offset 0x0C)
445 *-----------------------------------------------------------------------
446 */
447#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
448#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
449#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
450#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
451
452/*-----------------------------------------------------------------------
453 *
454 *-----------------------------------------------------------------------
455 *
456 */
457
458/*
459 * Internal Definitions
460 *
461 * Boot Flags
462 */
463#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
464#define BOOTFLAG_WARM 0x02 /* Software reboot */
465
466#endif /* __CONFIG_H */