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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
24 */
25
26#include <common.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000027#include <command.h>
28#include <mpc8260.h>
29#include <mpc8260_irq.h>
30#include <asm/processor.h>
31
32/****************************************************************************/
33
wdenk4a9cbbe2002-08-27 09:48:53 +000034struct irq_action {
35 interrupt_handler_t *handler;
36 void *arg;
37 ulong count;
38};
39
40static struct irq_action irq_handlers[NR_IRQS];
41
42static ulong ppc_cached_irq_mask[NR_MASK_WORDS];
43
44/****************************************************************************/
45/* this section was ripped out of arch/ppc/kernel/ppc8260_pic.c in the */
46/* Linux/PPC 2.4.x source. There was no copyright notice in that file. */
47
48/* The 8260 internal interrupt controller. It is usually
49 * the only interrupt controller.
50 * There are two 32-bit registers (high/low) for up to 64
51 * possible interrupts.
52 *
53 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
54 * in a simple arithmetic fashion to mask or pending registers.
55 * That is, interrupt 4 does not map to bit position 4.
56 * We create two tables, indexed by vector number, to indicate
57 * which register to use and which bit in the register to use.
58 */
59static u_char irq_to_siureg[] = {
60 1, 1, 1, 1, 1, 1, 1, 1,
61 1, 1, 1, 1, 1, 1, 1, 1,
62 0, 0, 0, 0, 0, 0, 0, 0,
63 0, 0, 0, 0, 0, 0, 0, 0,
64 1, 1, 1, 1, 1, 1, 1, 1,
65 1, 1, 1, 1, 1, 1, 1, 1,
66 0, 0, 0, 0, 0, 0, 0, 0,
67 0, 0, 0, 0, 0, 0, 0, 0
68};
69
70static u_char irq_to_siubit[] = {
71 31, 16, 17, 18, 19, 20, 21, 22,
72 23, 24, 25, 26, 27, 28, 29, 30,
73 29, 30, 16, 17, 18, 19, 20, 21,
74 22, 23, 24, 25, 26, 27, 28, 31,
75 0, 1, 2, 3, 4, 5, 6, 7,
76 8, 9, 10, 11, 12, 13, 14, 15,
77 15, 14, 13, 12, 11, 10, 9, 8,
78 7, 6, 5, 4, 3, 2, 1, 0
79};
80
81static void m8260_mask_irq (unsigned int irq_nr)
82{
83 volatile immap_t *immr = (immap_t *) CFG_IMMR;
84 int bit, word;
85 volatile uint *simr;
86
87 bit = irq_to_siubit[irq_nr];
88 word = irq_to_siureg[irq_nr];
89
90 simr = &(immr->im_intctl.ic_simrh);
91 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
92 simr[word] = ppc_cached_irq_mask[word];
93}
94
95static void m8260_unmask_irq (unsigned int irq_nr)
96{
97 volatile immap_t *immr = (immap_t *) CFG_IMMR;
98 int bit, word;
99 volatile uint *simr;
100
101 bit = irq_to_siubit[irq_nr];
102 word = irq_to_siureg[irq_nr];
103
104 simr = &(immr->im_intctl.ic_simrh);
105 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
106 simr[word] = ppc_cached_irq_mask[word];
107}
108
109static void m8260_mask_and_ack (unsigned int irq_nr)
110{
111 volatile immap_t *immr = (immap_t *) CFG_IMMR;
112 int bit, word;
113 volatile uint *simr, *sipnr;
114
115 bit = irq_to_siubit[irq_nr];
116 word = irq_to_siureg[irq_nr];
117
118 simr = &(immr->im_intctl.ic_simrh);
119 sipnr = &(immr->im_intctl.ic_sipnrh);
120 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
121 simr[word] = ppc_cached_irq_mask[word];
122 sipnr[word] = 1 << (31 - bit);
123}
124
125static int m8260_get_irq (struct pt_regs *regs)
126{
127 volatile immap_t *immr = (immap_t *) CFG_IMMR;
128 int irq;
129 unsigned long bits;
130
131 /* For MPC8260, read the SIVEC register and shift the bits down
132 * to get the irq number. */
133 bits = immr->im_intctl.ic_sivec;
134 irq = bits >> 26;
135 return irq;
136}
137
138/* end of code ripped out of arch/ppc/kernel/ppc8260_pic.c */
139/****************************************************************************/
140
wdenka8c7c702003-12-06 19:49:23 +0000141int interrupt_init_cpu (unsigned *decrementer_count)
wdenk4a9cbbe2002-08-27 09:48:53 +0000142{
143 DECLARE_GLOBAL_DATA_PTR;
144
145 volatile immap_t *immr = (immap_t *) CFG_IMMR;
146
wdenka8c7c702003-12-06 19:49:23 +0000147 *decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
wdenk4a9cbbe2002-08-27 09:48:53 +0000148
149 /* Initialize the default interrupt mapping priorities */
150 immr->im_intctl.ic_sicr = 0;
151 immr->im_intctl.ic_siprr = 0x05309770;
152 immr->im_intctl.ic_scprrh = 0x05309770;
153 immr->im_intctl.ic_scprrl = 0x05309770;
154
155 /* disable all interrupts and clear all pending bits */
156 immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
157 immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
158 immr->im_intctl.ic_sipnrh = 0xffffffff;
159 immr->im_intctl.ic_sipnrl = 0xffffffff;
160
wdenk6dd652f2003-06-19 23:40:20 +0000161#ifdef CONFIG_HYMOD
162 /*
163 * ensure all external interrupt sources default to trigger on
164 * high-to-low transition (i.e. edge triggered active low)
165 */
166 immr->im_intctl.ic_siexr = -1;
167#endif
168
wdenk4a9cbbe2002-08-27 09:48:53 +0000169 return (0);
170}
171
172/****************************************************************************/
173
174/*
175 * Handle external interrupts
176 */
177void external_interrupt (struct pt_regs *regs)
178{
179 int irq, unmask = 1;
180
181 irq = m8260_get_irq (regs);
182
183 m8260_mask_and_ack (irq);
184
wdenka8c7c702003-12-06 19:49:23 +0000185 enable_interrupts ();
wdenk4a9cbbe2002-08-27 09:48:53 +0000186
187 if (irq_handlers[irq].handler != NULL)
188 (*irq_handlers[irq].handler) (irq_handlers[irq].arg);
189 else {
190 printf ("\nBogus External Interrupt IRQ %d\n", irq);
191 /*
192 * turn off the bogus interrupt, otherwise it
193 * might repeat forever
194 */
195 unmask = 0;
196 }
197
198 if (unmask)
199 m8260_unmask_irq (irq);
200}
201
202/****************************************************************************/
203
204/*
205 * Install and free an interrupt handler.
206 */
207
208void
209irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
210{
211 if (irq < 0 || irq >= NR_IRQS) {
212 printf ("irq_install_handler: bad irq number %d\n", irq);
213 return;
214 }
215
216 if (irq_handlers[irq].handler != NULL)
217 printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
218 (ulong) handler, (ulong) irq_handlers[irq].handler);
219
220 irq_handlers[irq].handler = handler;
221 irq_handlers[irq].arg = arg;
222
223 m8260_unmask_irq (irq);
224}
225
226void irq_free_handler (int irq)
227{
228 if (irq < 0 || irq >= NR_IRQS) {
229 printf ("irq_free_handler: bad irq number %d\n", irq);
230 return;
231 }
232
233 m8260_mask_irq (irq);
234
235 irq_handlers[irq].handler = NULL;
236 irq_handlers[irq].arg = NULL;
237}
238
239/****************************************************************************/
240
wdenka8c7c702003-12-06 19:49:23 +0000241void timer_interrupt_cpu (struct pt_regs *regs)
wdenk4a9cbbe2002-08-27 09:48:53 +0000242{
wdenka8c7c702003-12-06 19:49:23 +0000243 /* nothing to do here */
244 return;
wdenk4a9cbbe2002-08-27 09:48:53 +0000245}
246
247/****************************************************************************/
248
249#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
250
251/* ripped this out of ppc4xx/interrupts.c */
252
253/*******************************************************************************
254*
255* irqinfo - print information about PCI devices
256*
257*/
258void
259do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
260{
261 int irq, re_enable;
262
263 re_enable = disable_interrupts ();
264
wdenk4b9206e2004-03-23 22:14:11 +0000265 puts ("\nInterrupt-Information:\n"
266 "Nr Routine Arg Count\n");
wdenk4a9cbbe2002-08-27 09:48:53 +0000267
268 for (irq = 0; irq < 32; irq++)
269 if (irq_handlers[irq].handler != NULL)
270 printf ("%02d %08lx %08lx %ld\n", irq,
271 (ulong) irq_handlers[irq].handler,
272 (ulong) irq_handlers[irq].arg,
273 irq_handlers[irq].count);
274
275 if (re_enable)
276 enable_interrupts ();
277}
278
279#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */