| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_K3=y |
| Dhruva Gole | 0415040 | 2022-10-27 20:23:11 +0530 | [diff] [blame] | 3 | CONFIG_SYS_MALLOC_LEN=0x08000000 |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 4 | CONFIG_SYS_MALLOC_F_LEN=0x9000 |
| 5 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 6 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| Georgi Vlaev | 6ea5bcc | 2022-06-14 17:45:34 +0300 | [diff] [blame] | 7 | CONFIG_NR_DRAM_BANKS=2 |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 8 | CONFIG_SOC_K3_AM625=y |
| 9 | CONFIG_TARGET_AM625_R5_EVM=y |
| Sjoerd Simons | 21d39eb | 2022-12-20 16:21:44 +0100 | [diff] [blame] | 10 | CONFIG_ENV_SIZE=0x20000 |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 11 | CONFIG_DM_GPIO=y |
| 12 | CONFIG_SPL_DM_SPI=y |
| 13 | CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-sk" |
| 14 | CONFIG_SPL_TEXT_BASE=0x43c00000 |
| 15 | CONFIG_SPL_MMC=y |
| 16 | CONFIG_SPL_SERIAL=y |
| Tom Rini | 0fc5c49 | 2022-07-25 17:19:18 -0400 | [diff] [blame] | 17 | CONFIG_SPL_DRIVERS_MISC=y |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 18 | CONFIG_SPL_STACK_R_ADDR=0x82000000 |
| 19 | CONFIG_SPL_SIZE_LIMIT=0x40000 |
| 20 | CONFIG_SPL_FS_FAT=y |
| 21 | CONFIG_SPL_LIBDISK_SUPPORT=y |
| Dhruva Gole | 0415040 | 2022-10-27 20:23:11 +0530 | [diff] [blame] | 22 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| Sjoerd Simons | 21d39eb | 2022-12-20 16:21:44 +0100 | [diff] [blame] | 23 | CONFIG_SPL_SPI=y |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 24 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 25 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff |
| 26 | CONFIG_SPL_LOAD_FIT=y |
| 27 | CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 |
| 28 | CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y |
| 29 | # CONFIG_DISPLAY_CPUINFO is not set |
| 30 | CONFIG_SPL_MAX_SIZE=0x58000 |
| 31 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 32 | CONFIG_SPL_BSS_START_ADDR=0x43c37800 |
| 33 | CONFIG_SPL_BSS_MAX_SIZE=0x5000 |
| 34 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
| 35 | CONFIG_SPL_STACK_R=y |
| 36 | CONFIG_SPL_SEPARATE_BSS=y |
| 37 | CONFIG_SYS_SPL_MALLOC=y |
| 38 | CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y |
| 39 | CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 |
| 40 | CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 |
| 41 | CONFIG_SPL_EARLY_BSS=y |
| 42 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y |
| 43 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 |
| 44 | CONFIG_SPL_DM_MAILBOX=y |
| Dhruva Gole | 0415040 | 2022-10-27 20:23:11 +0530 | [diff] [blame] | 45 | CONFIG_SPL_DM_SPI_FLASH=y |
| Sjoerd Simons | 21d39eb | 2022-12-20 16:21:44 +0100 | [diff] [blame] | 46 | CONFIG_SPL_DM_RESET=y |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 47 | CONFIG_SPL_POWER_DOMAIN=y |
| 48 | CONFIG_SPL_RAM_SUPPORT=y |
| 49 | CONFIG_SPL_RAM_DEVICE=y |
| 50 | CONFIG_SPL_REMOTEPROC=y |
| Dhruva Gole | 0415040 | 2022-10-27 20:23:11 +0530 | [diff] [blame] | 51 | # CONFIG_SPL_SPI_FLASH_TINY is not set |
| 52 | CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y |
| 53 | CONFIG_SPL_SPI_LOAD=y |
| Sjoerd Simons | 21d39eb | 2022-12-20 16:21:44 +0100 | [diff] [blame] | 54 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 55 | CONFIG_SPL_YMODEM_SUPPORT=y |
| 56 | CONFIG_HUSH_PARSER=y |
| 57 | CONFIG_CMD_ASKENV=y |
| 58 | CONFIG_CMD_DFU=y |
| 59 | CONFIG_CMD_GPT=y |
| 60 | CONFIG_CMD_MMC=y |
| 61 | CONFIG_CMD_REMOTEPROC=y |
| 62 | # CONFIG_CMD_SETEXPR is not set |
| 63 | CONFIG_CMD_TIME=y |
| 64 | CONFIG_CMD_FAT=y |
| 65 | CONFIG_OF_CONTROL=y |
| 66 | CONFIG_SPL_OF_CONTROL=y |
| 67 | CONFIG_SPL_MULTI_DTB_FIT=y |
| 68 | CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y |
| 69 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 70 | CONFIG_SPL_DM=y |
| 71 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 72 | CONFIG_REGMAP=y |
| 73 | CONFIG_SPL_REGMAP=y |
| 74 | CONFIG_SPL_OF_TRANSLATE=y |
| 75 | CONFIG_CLK=y |
| 76 | CONFIG_SPL_CLK=y |
| 77 | CONFIG_SPL_CLK_CCF=y |
| 78 | CONFIG_SPL_CLK_K3_PLL=y |
| 79 | CONFIG_SPL_CLK_K3=y |
| 80 | CONFIG_TI_SCI_PROTOCOL=y |
| 81 | CONFIG_DA8XX_GPIO=y |
| 82 | CONFIG_DM_MAILBOX=y |
| 83 | CONFIG_K3_SEC_PROXY=y |
| Tom Rini | 0fc5c49 | 2022-07-25 17:19:18 -0400 | [diff] [blame] | 84 | CONFIG_SPL_MISC=y |
| 85 | CONFIG_ESM_K3=y |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 86 | CONFIG_MMC_SDHCI=y |
| 87 | CONFIG_MMC_SDHCI_ADMA=y |
| 88 | CONFIG_SPL_MMC_SDHCI_ADMA=y |
| 89 | CONFIG_MMC_SDHCI_AM654=y |
| Sjoerd Simons | 21d39eb | 2022-12-20 16:21:44 +0100 | [diff] [blame] | 90 | CONFIG_DM_SPI_FLASH=y |
| 91 | CONFIG_SF_DEFAULT_MODE=0 |
| 92 | CONFIG_SF_DEFAULT_SPEED=25000000 |
| 93 | CONFIG_SPI_FLASH_SFDP_SUPPORT=y |
| 94 | CONFIG_SPI_FLASH_SOFT_RESET=y |
| 95 | CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y |
| 96 | CONFIG_SPI_FLASH_SPANSION=y |
| 97 | CONFIG_SPI_FLASH_S28HX_T=y |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 98 | CONFIG_PINCTRL=y |
| 99 | # CONFIG_PINCTRL_GENERIC is not set |
| 100 | CONFIG_SPL_PINCTRL=y |
| 101 | # CONFIG_SPL_PINCTRL_GENERIC is not set |
| 102 | CONFIG_PINCTRL_SINGLE=y |
| 103 | CONFIG_POWER_DOMAIN=y |
| 104 | CONFIG_TI_POWER_DOMAIN=y |
| 105 | CONFIG_K3_SYSTEM_CONTROLLER=y |
| 106 | CONFIG_REMOTEPROC_TI_K3_ARM64=y |
| 107 | CONFIG_DM_RESET=y |
| 108 | CONFIG_RESET_TI_SCI=y |
| 109 | CONFIG_SPECIFY_CONSOLE_INDEX=y |
| 110 | CONFIG_DM_SERIAL=y |
| 111 | CONFIG_SOC_DEVICE=y |
| 112 | CONFIG_SOC_DEVICE_TI_K3=y |
| 113 | CONFIG_SOC_TI=y |
| Sjoerd Simons | 21d39eb | 2022-12-20 16:21:44 +0100 | [diff] [blame] | 114 | CONFIG_SPI=y |
| 115 | CONFIG_DM_SPI=y |
| 116 | CONFIG_CADENCE_QSPI=y |
| Vignesh Raghavendra | 2d257d9 | 2022-05-25 13:38:49 +0530 | [diff] [blame] | 117 | CONFIG_TIMER=y |
| 118 | CONFIG_SPL_TIMER=y |
| 119 | CONFIG_OMAP_TIMER=y |
| 120 | CONFIG_LIB_RATIONAL=y |
| 121 | CONFIG_SPL_LIB_RATIONAL=y |