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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 19a387f85d3643ec052903223bfdcffe0ab227a6 / . / arch / arm / dts / imx6qdl-gw5904.dtsi
blob: 5b7bd5693286a1defbdc82db1a352d6858272bc4 [file] [log] [blame]
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]1/*
2 * Copyright 2017 Gateworks Corporation
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include <dt-bindings/gpio/gpio.h>
49#include <dt-bindings/input/linux-event-codes.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51
52/ {
53 /* these are used by bootloader for disabling nodes */
54 aliases {
55 led0 = &led0;
56 led1 = &led1;
57 led2 = &led2;
Tim Harvey19a387f2021-03-01 14:33:35 -0800[diff] [blame^]58 mmc0 = &usdhc3;
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]59 usb0 = &usbh1;
60 usb1 = &usbotg;
61 };
62
63 chosen {
64 stdout-path = &uart2;
65 };
66
67 backlight {
68 compatible = "pwm-backlight";
69 pwms = <&pwm4 0 5000000>;
70 brightness-levels = <0 4 8 16 32 64 128 255>;
71 default-brightness-level = <7>;
72 };
73
74 gpio-keys {
75 compatible = "gpio-keys";
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 user-pb {
80 label = "user_pb";
81 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
82 linux,code = <BTN_0>;
83 };
84
85 user-pb1x {
86 label = "user_pb1x";
87 linux,code = <BTN_1>;
88 interrupt-parent = <&gsc>;
89 interrupts = <0>;
90 };
91
92 key-erased {
93 label = "key-erased";
94 linux,code = <BTN_2>;
95 interrupt-parent = <&gsc>;
96 interrupts = <1>;
97 };
98
99 eeprom-wp {
100 label = "eeprom_wp";
101 linux,code = <BTN_3>;
102 interrupt-parent = <&gsc>;
103 interrupts = <2>;
104 };
105
106 tamper {
107 label = "tamper";
108 linux,code = <BTN_4>;
109 interrupt-parent = <&gsc>;
110 interrupts = <5>;
111 };
112
113 switch-hold {
114 label = "switch_hold";
115 linux,code = <BTN_5>;
116 interrupt-parent = <&gsc>;
117 interrupts = <7>;
118 };
119 };
120
121 leds {
122 compatible = "gpio-leds";
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_gpio_leds>;
125
126 led0: user1 {
127 label = "user1";
128 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
129 default-state = "on";
130 linux,default-trigger = "heartbeat";
131 };
132
133 led1: user2 {
134 label = "user2";
135 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
136 default-state = "off";
137 };
138
139 led2: user3 {
140 label = "user3";
141 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
142 default-state = "off";
143 };
144 };
145
146 memory@10000000 {
147 device_type = "memory";
148 reg = <0x10000000 0x40000000>;
149 };
150
151 pps {
152 compatible = "pps-gpio";
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_pps>;
155 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
156 };
157
158 reg_1p0v: regulator-1p0v {
159 compatible = "regulator-fixed";
160 regulator-name = "1P0V";
161 regulator-min-microvolt = <1000000>;
162 regulator-max-microvolt = <1000000>;
163 regulator-always-on;
164 };
165
166 reg_3p3v: regulator-3p3v {
167 compatible = "regulator-fixed";
168 regulator-name = "3P3V";
169 regulator-min-microvolt = <3300000>;
170 regulator-max-microvolt = <3300000>;
171 regulator-always-on;
172 };
173
174 reg_usb_h1_vbus: regulator-usb-h1-vbus {
175 compatible = "regulator-fixed";
176 regulator-name = "usb_h1_vbus";
177 regulator-min-microvolt = <5000000>;
178 regulator-max-microvolt = <5000000>;
179 regulator-always-on;
180 };
181
182 reg_usb_otg_vbus: regulator-usb-otg-vbus {
183 compatible = "regulator-fixed";
184 regulator-name = "usb_otg_vbus";
185 regulator-min-microvolt = <5000000>;
186 regulator-max-microvolt = <5000000>;
187 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
188 enable-active-high;
189 };
190};
191
192&clks {
193 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
194 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
195 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
196 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
197};
198
199&fec {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_enet>;
202 phy-mode = "rgmii-id";
203 status = "okay";
204
205 fixed-link {
206 speed = <1000>;
207 full-duplex;
208 };
209
210 mdio {
211 #address-cells = <1>;
212 #size-cells = <0>;
213
214 switch@0 {
215 compatible = "marvell,mv88e6085";
216 reg = <0>;
217
218 ports {
219 #address-cells = <1>;
220 #size-cells = <0>;
221
222 port@0 {
223 reg = <0>;
224 label = "lan4";
225 };
226
227 port@1 {
228 reg = <1>;
229 label = "lan3";
230 };
231
232 port@2 {
233 reg = <2>;
234 label = "lan2";
235 };
236
237 port@3 {
238 reg = <3>;
239 label = "lan1";
240 };
241
242 port@5 {
243 reg = <5>;
244 label = "cpu";
245 ethernet = <&fec>;
246 };
247 };
248 };
249 };
250};
251
252&i2c1 {
253 clock-frequency = <100000>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_i2c1>;
256 status = "okay";
257
258 gsc: gsc@20 {
259 compatible = "gw,gsc";
260 reg = <0x20>;
261 interrupt-parent = <&gpio1>;
262 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
263 interrupt-controller;
264 #interrupt-cells = <1>;
265 #size-cells = <0>;
266
267 adc {
268 compatible = "gw,gsc-adc";
269 #address-cells = <1>;
270 #size-cells = <0>;
271
272 channel@0 {
273 gw,mode = <0>;
274 reg = <0x00>;
275 label = "temp";
276 };
277
278 channel@2 {
279 gw,mode = <1>;
280 reg = <0x02>;
281 label = "vdd_vin";
282 };
283
284 channel@5 {
285 gw,mode = <1>;
286 reg = <0x05>;
287 label = "vdd_3p3";
288 };
289
290 channel@8 {
291 gw,mode = <1>;
292 reg = <0x08>;
293 label = "vdd_bat";
294 };
295
296 channel@b {
297 gw,mode = <1>;
298 reg = <0x0b>;
299 label = "vdd_5p0";
300 };
301
302 channel@e {
303 gw,mode = <1>;
304 reg = <0xe>;
305 label = "vdd_arm";
306 };
307
308 channel@11 {
309 gw,mode = <1>;
310 reg = <0x11>;
311 label = "vdd_soc";
312 };
313
314 channel@14 {
315 gw,mode = <1>;
316 reg = <0x14>;
317 label = "vdd_3p0";
318 };
319
320 channel@17 {
321 gw,mode = <1>;
322 reg = <0x17>;
323 label = "vdd_1p5";
324 };
325
326 channel@1d {
327 gw,mode = <1>;
328 reg = <0x1d>;
329 label = "vdd_1p8";
330 };
331
332 channel@20 {
333 gw,mode = <1>;
334 reg = <0x20>;
335 label = "vdd_an1";
336 };
337
338 channel@23 {
339 gw,mode = <1>;
340 reg = <0x23>;
341 label = "vdd_2p5";
342 };
343 };
344 };
345
346 gsc_gpio: gpio@23 {
347 compatible = "nxp,pca9555";
348 reg = <0x23>;
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-parent = <&gsc>;
352 interrupts = <4>;
353 };
354
355 eeprom1: eeprom@50 {
356 compatible = "atmel,24c02";
357 reg = <0x50>;
358 pagesize = <16>;
359 };
360
361 eeprom2: eeprom@51 {
362 compatible = "atmel,24c02";
363 reg = <0x51>;
364 pagesize = <16>;
365 };
366
367 eeprom3: eeprom@52 {
368 compatible = "atmel,24c02";
369 reg = <0x52>;
370 pagesize = <16>;
371 };
372
373 eeprom4: eeprom@53 {
374 compatible = "atmel,24c02";
375 reg = <0x53>;
376 pagesize = <16>;
377 };
378
379 dts1672: rtc@68 {
380 compatible = "dallas,ds1672";
381 reg = <0x68>;
382 };
383};
384
385&i2c2 {
386 clock-frequency = <100000>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_i2c2>;
389 status = "okay";
390
391 magn@1c {
392 compatible = "st,lsm9ds1-magn";
393 reg = <0x1c>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_mag>;
396 interrupt-parent = <&gpio5>;
397 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
398 };
399
400 ltc3676: pmic@3c {
401 compatible = "lltc,ltc3676";
402 reg = <0x3c>;
403 interrupt-parent = <&gpio1>;
404 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
405
406 regulators {
407 /* VDD_SOC (1+R1/R2 = 1.635) */
408 reg_vdd_soc: sw1 {
409 regulator-name = "vddsoc";
410 regulator-min-microvolt = <674400>;
411 regulator-max-microvolt = <1308000>;
412 lltc,fb-voltage-divider = <127000 200000>;
413 regulator-ramp-delay = <7000>;
414 regulator-boot-on;
415 regulator-always-on;
416 };
417
418 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
419 reg_1p8v: sw2 {
420 regulator-name = "vdd1p8";
421 regulator-min-microvolt = <1033310>;
422 regulator-max-microvolt = <2004000>;
423 lltc,fb-voltage-divider = <301000 200000>;
424 regulator-ramp-delay = <7000>;
425 regulator-boot-on;
426 regulator-always-on;
427 };
428
429 /* VDD_ARM (1+R1/R2 = 1.635) */
430 reg_vdd_arm: sw3 {
431 regulator-name = "vddarm";
432 regulator-min-microvolt = <674400>;
433 regulator-max-microvolt = <1308000>;
434 lltc,fb-voltage-divider = <127000 200000>;
435 regulator-ramp-delay = <7000>;
436 regulator-boot-on;
437 regulator-always-on;
438 };
439
440 /* VDD_DDR (1+R1/R2 = 2.105) */
441 reg_vdd_ddr: sw4 {
442 regulator-name = "vddddr";
443 regulator-min-microvolt = <868310>;
444 regulator-max-microvolt = <1684000>;
445 lltc,fb-voltage-divider = <221000 200000>;
446 regulator-ramp-delay = <7000>;
447 regulator-boot-on;
448 regulator-always-on;
449 };
450
451 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
452 reg_2p5v: ldo2 {
453 regulator-name = "vdd2p5";
454 regulator-min-microvolt = <2490375>;
455 regulator-max-microvolt = <2490375>;
456 lltc,fb-voltage-divider = <487000 200000>;
457 regulator-boot-on;
458 regulator-always-on;
459 };
460
461 /* VDD_HIGH (1+R1/R2 = 4.17) */
462 reg_3p0v: ldo4 {
463 regulator-name = "vdd3p0";
464 regulator-min-microvolt = <3023250>;
465 regulator-max-microvolt = <3023250>;
466 lltc,fb-voltage-divider = <634000 200000>;
467 regulator-boot-on;
468 regulator-always-on;
469 };
470 };
471 };
472
473 imu@6a {
474 compatible = "st,lsm9ds1-imu";
475 reg = <0x6a>;
476 st,drdy-int-pin = <1>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_imu>;
479 interrupt-parent = <&gpio4>;
480 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
481 };
482};
483
484&i2c3 {
485 clock-frequency = <100000>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_i2c3>;
488 status = "okay";
489
490 egalax_ts: touchscreen@4 {
491 compatible = "eeti,egalax_ts";
492 reg = <0x04>;
493 interrupt-parent = <&gpio1>;
494 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
495 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
496 };
497};
498
499&ldb {
500 status = "okay";
501
502 lvds-channel@0 {
503 fsl,data-mapping = "spwg";
504 fsl,data-width = <18>;
505 status = "okay";
506
507 display-timings {
508 native-mode = <&timing0>;
509 timing0: hsd100pxn1 {
510 clock-frequency = <65000000>;
511 hactive = <1024>;
512 vactive = <768>;
513 hback-porch = <220>;
514 hfront-porch = <40>;
515 vback-porch = <21>;
516 vfront-porch = <7>;
517 hsync-len = <60>;
518 vsync-len = <10>;
519 };
520 };
521 };
522};
523
524&pcie {
525 pinctrl-names = "default";
526 pinctrl-0 = <&pinctrl_pcie>;
527 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
528 status = "okay";
529};
530
531&pwm2 {
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
534 status = "disabled";
535};
536
537&pwm3 {
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
540 status = "disabled";
541};
542
543&pwm4 {
544 #pwm-cells = <2>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_pwm4>;
547 status = "okay";
548};
549
550&uart1 {
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_uart1>;
553 status = "okay";
554};
555
556&uart2 {
557 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_uart2>;
559 status = "okay";
560};
561
562&uart3 {
563 pinctrl-names = "default";
564 pinctrl-0 = <&pinctrl_uart3>;
565 uart-has-rtscts;
566 status = "okay";
567};
568
569&uart4 {
570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_uart4>;
572 uart-has-rtscts;
573 status = "okay";
574};
575
576&uart5 {
577 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_uart5>;
579 status = "okay";
580};
581
582&usbotg {
583 vbus-supply = <&reg_usb_otg_vbus>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&pinctrl_usbotg>;
586 disable-over-current;
Tim Harvey13acc632021-03-01 14:33:31 -0800[diff] [blame]587 dr_mode = "otg";
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]588 status = "okay";
589};
590
591&usbh1 {
592 vbus-supply = <&reg_usb_h1_vbus>;
593 status = "okay";
594};
595
596&usdhc3 {
597 pinctrl-names = "default", "state_100mhz", "state_200mhz";
598 pinctrl-0 = <&pinctrl_usdhc3>;
599 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
600 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
601 non-removable;
602 vmmc-supply = <&reg_3p3v>;
603 keep-power-in-suspend;
604 status = "okay";
605};
606
607&wdog1 {
608 pinctrl-names = "default";
609 pinctrl-0 = <&pinctrl_wdog>;
610 fsl,ext-reset-output;
611};
612
613&iomuxc {
614 pinctrl_enet: enetgrp {
615 fsl,pins = <
616 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
617 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
618 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
619 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
620 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
621 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
622 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
623 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
624 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
625 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
626 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
627 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
628 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
629 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
630 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
631 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
632 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */
633 >;
634 };
635
636 pinctrl_gpio_leds: gpioledsgrp {
637 fsl,pins = <
638 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
639 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
640 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
641 >;
642 };
643
644 pinctrl_i2c1: i2c1grp {
645 fsl,pins = <
646 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
647 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
648 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
649 >;
650 };
651
652 pinctrl_i2c2: i2c2grp {
653 fsl,pins = <
654 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
655 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
656 >;
657 };
658
659 pinctrl_i2c3: i2c3grp {
660 fsl,pins = <
661 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
662 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
663 >;
664 };
665
666 pinctrl_imu: imugrp {
667 fsl,pins = <
668 MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
669 >;
670 };
671
672 pinctrl_mag: maggrp {
673 fsl,pins = <
674 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
675 >;
676 };
677
678 pinctrl_pcie: pciegrp {
679 fsl,pins = <
680 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
681 >;
682 };
683
684 pinctrl_pmic: pmicgrp {
685 fsl,pins = <
686 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */
687 >;
688 };
689
690 pinctrl_pps: ppsgrp {
691 fsl,pins = <
692 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
693 >;
694 };
695
696 pinctrl_pwm2: pwm2grp {
697 fsl,pins = <
698 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
699 >;
700 };
701
702 pinctrl_pwm3: pwm3grp {
703 fsl,pins = <
704 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
705 >;
706 };
707
708 pinctrl_pwm4: pwm4grp {
709 fsl,pins = <
710 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
711 >;
712 };
713
714 pinctrl_uart1: uart1grp {
715 fsl,pins = <
716 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
717 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
718 >;
719 };
720
721 pinctrl_uart2: uart2grp {
722 fsl,pins = <
723 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
724 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
725 >;
726 };
727
728 pinctrl_uart3: uart3grp {
729 fsl,pins = <
730 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
731 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
732 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
733 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
734 >;
735 };
736
737 pinctrl_uart4: uart4grp {
738 fsl,pins = <
739 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
740 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
741 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
742 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
743 >;
744 };
745
746 pinctrl_uart5: uart5grp {
747 fsl,pins = <
748 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
749 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
750 >;
751 };
752
753 pinctrl_usbotg: usbotggrp {
754 fsl,pins = <
755 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
756 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
757 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
758 >;
759 };
760
761 pinctrl_usdhc3: usdhc3grp {
762 fsl,pins = <
763 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
764 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
765 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059
766 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
767 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
768 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
769 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
770 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
771 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
772 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
773 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
774 >;
775 };
776
777 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
778 fsl,pins = <
779 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
780 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
781 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9
782 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
783 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
784 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
785 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
786 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
787 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
788 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
789 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
790 >;
791 };
792
793 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
794 fsl,pins = <
795 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
796 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
797 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9
798 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
799 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
800 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
801 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
802 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
803 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
804 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
805 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
806 >;
807 };
808
809 pinctrl_wdog: wdoggrp {
810 fsl,pins = <
811 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
812 >;
813 };
814};