blob: 2dfd87c78e596c6267a21ddab7ba01a6d05a27c2 [file] [log] [blame]
stroeseaee2fa22004-12-16 18:17:50 +00001/*
2 * (C) Copyright 2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27
stroeseaee2fa22004-12-16 18:17:50 +000028#define MEM_MCOPT1_INIT_VAL 0x00800000
29#define MEM_RTR_INIT_VAL 0x04070000
30#define MEM_PMIT_INIT_VAL 0x07c00000
31#define MEM_MB0CF_INIT_VAL 0x00082001
32#define MEM_MB1CF_INIT_VAL 0x04082000
33#define MEM_SDTR1_INIT_VAL 0x00854005
34#define SDRAM0_CFG_ENABLE 0x80000000
35
stroeseaee2fa22004-12-16 18:17:50 +000036#define CFG_SDRAM_SIZE 0x04000000 /* 64 MB */
37
stroeseaee2fa22004-12-16 18:17:50 +000038int board_early_init_f (void)
39{
40#if 0 /* test-only */
41 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
42 mtdcr (uicer, 0x00000000); /* disable all ints */
43 mtdcr (uiccr, 0x00000010);
44 mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
45 mtdcr (uictr, 0x00000010); /* set int trigger levels */
46 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
47#else
48 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
49 mtdcr(uicer, 0x00000000); /* disable all ints */
50 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
51 mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */
52 mtdcr(uictr, 0x10000000); /* set int trigger levels */
53 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
54 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
55#endif
56
57#if 1 /* test-only */
58 /*
59 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
60 */
61 mtebc (epcr, 0xa8400000); /* ebc always driven */
62#endif
63
64 return 0;
65}
66
67
68int misc_init_f (void)
69{
70 return 0; /* dummy implementation */
71}
72
73
74int misc_init_r (void)
75{
Jon Loeligerc508a4c2007-07-09 18:31:28 -050076#if defined(CONFIG_CMD_NAND)
stroeseaee2fa22004-12-16 18:17:50 +000077 /*
78 * Set NAND-FLASH GPIO signals to default
79 */
80 out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
81 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
82#endif
83
84 return (0);
85}
86
87
88/*
89 * Check Board Identity:
90 */
91int checkboard (void)
92{
Wolfgang Denk77ddac92005-10-13 16:45:02 +020093 char str[64];
stroeseaee2fa22004-12-16 18:17:50 +000094 int i = getenv_r ("serial#", str, sizeof(str));
95
96 puts ("Board: ");
97
98 if (i == -1) {
99 puts ("### No HW ID - assuming G2000");
100 } else {
101 puts(str);
102 }
103
104 putc ('\n');
105
106 return 0;
107}
108
109
110/* -------------------------------------------------------------------------
111 G2000 rev B is an embeded design. we don't read for spd of this version.
112 Doing static SDRAM controller configuration in the following section.
113 ------------------------------------------------------------------------- */
114
115long int init_sdram_static_settings(void)
116{
117#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
wdenkefe2a4d2004-12-16 21:44:03 +0000118 /* disable memcontroller so updates work */
119 mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
120 mtsdram0( mem_rtr , MEM_RTR_INIT_VAL );
121 mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL );
122 mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL );
123 mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL );
124 mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL );
stroeseaee2fa22004-12-16 18:17:50 +0000125
wdenkefe2a4d2004-12-16 21:44:03 +0000126 /* SDRAM have a power on delay, 500 micro should do */
127 udelay(500);
128 mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
stroeseaee2fa22004-12-16 18:17:50 +0000129
wdenkefe2a4d2004-12-16 21:44:03 +0000130 return (CFG_SDRAM_SIZE); /* CFG_SDRAM_SIZE is in G2000.h */
stroeseaee2fa22004-12-16 18:17:50 +0000131 }
132
133
134long int initdram (int board_type)
135{
136 long int ret;
137
138/* flzt, we can still turn this on in the future */
139/* #ifdef CONFIG_SPD_EEPROM
wdenkefe2a4d2004-12-16 21:44:03 +0000140 ret = spd_sdram ();
stroeseaee2fa22004-12-16 18:17:50 +0000141#else
wdenkefe2a4d2004-12-16 21:44:03 +0000142 ret = init_sdram_static_settings();
stroeseaee2fa22004-12-16 18:17:50 +0000143#endif
144*/
145
146 ret = init_sdram_static_settings();
147
148 return ret;
149}
150
151
152#if 1 /* test-only */
153void sdram_init(void)
154{
155 init_sdram_static_settings();
156}
157#endif
158
159
160#if 0 /* test-only */
161long int initdram (int board_type)
162{
163 unsigned long val;
164
165 mtdcr(memcfga, mem_mb0cf);
166 val = mfdcr(memcfgd);
167
168#if 0
169 printf("\nmb0cf=%x\n", val); /* test-only */
170 printf("strap=%x\n", mfdcr(strap)); /* test-only */
171#endif
172
173 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
174}
175#endif
176
177
178int testdram (void)
179{
180 /* TODO: XXX XXX XXX */
181 printf ("test: 16 MB - ok\n");
182
183 return (0);
184}
185
186
Jon Loeligerc508a4c2007-07-09 18:31:28 -0500187#if defined(CONFIG_CMD_NAND)
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100188#include <linux/mtd/nand_legacy.h>
stroeseaee2fa22004-12-16 18:17:50 +0000189extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
190
191void nand_init(void)
192{
193 nand_probe(CFG_NAND_BASE);
194 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
195 print_size(nand_dev_desc[0].totlen, "\n");
196 }
197}
198#endif
199
200
201#if 0 /* test-only !!! */
202int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
203{
204 ulong ap, cr;
205
206 printf("\nEBC registers for PPC405GP:\n");
207 mfebc(pb0ap, ap); mfebc(pb0cr, cr);
208 printf("0: AP=%08lx CP=%08lx\n", ap, cr);
209 mfebc(pb1ap, ap); mfebc(pb1cr, cr);
210 printf("1: AP=%08lx CP=%08lx\n", ap, cr);
211 mfebc(pb2ap, ap); mfebc(pb2cr, cr);
212 printf("2: AP=%08lx CP=%08lx\n", ap, cr);
213 mfebc(pb3ap, ap); mfebc(pb3cr, cr);
214 printf("3: AP=%08lx CP=%08lx\n", ap, cr);
215 mfebc(pb4ap, ap); mfebc(pb4cr, cr);
216 printf("4: AP=%08lx CP=%08lx\n", ap, cr);
217 printf("\n");
218
219 return 0;
220}
221U_BOOT_CMD(
222 dumpebc, 1, 1, do_dumpebc,
223 "dumpebc - Dump all EBC registers\n",
224 NULL
225);
226
227
228int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
229{
230 int i;
231
232 printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
233 for (i=0; i<=0x1e0; i++) {
234 if (!(i % 0x8)) {
235 printf("\n%04x ", i);
236 }
237 printf("%08lx ", get_dcr(i));
238 }
239 printf("\n");
240
241 return 0;
242}
243U_BOOT_CMD(
244 dumpdcr, 1, 1, do_dumpdcr,
245 "dumpdcr - Dump all DCR registers\n",
246 NULL
247);
248
249
250int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
251{
252 printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
253 printf("\n%04x %08x ", 947, mfspr(947));
254 printf("\n%04x %08x ", 9, mfspr(9));
255 printf("\n%04x %08x ", 1014, mfspr(1014));
256 printf("\n%04x %08x ", 1015, mfspr(1015));
257 printf("\n%04x %08x ", 1010, mfspr(1010));
258 printf("\n%04x %08x ", 957, mfspr(957));
259 printf("\n%04x %08x ", 1008, mfspr(1008));
260 printf("\n%04x %08x ", 1018, mfspr(1018));
261 printf("\n%04x %08x ", 954, mfspr(954));
262 printf("\n%04x %08x ", 950, mfspr(950));
263 printf("\n%04x %08x ", 951, mfspr(951));
264 printf("\n%04x %08x ", 981, mfspr(981));
265 printf("\n%04x %08x ", 980, mfspr(980));
266 printf("\n%04x %08x ", 982, mfspr(982));
267 printf("\n%04x %08x ", 1012, mfspr(1012));
268 printf("\n%04x %08x ", 1013, mfspr(1013));
269 printf("\n%04x %08x ", 948, mfspr(948));
270 printf("\n%04x %08x ", 949, mfspr(949));
271 printf("\n%04x %08x ", 1019, mfspr(1019));
272 printf("\n%04x %08x ", 979, mfspr(979));
273 printf("\n%04x %08x ", 8, mfspr(8));
274 printf("\n%04x %08x ", 945, mfspr(945));
275 printf("\n%04x %08x ", 987, mfspr(987));
276 printf("\n%04x %08x ", 287, mfspr(287));
277 printf("\n%04x %08x ", 953, mfspr(953));
278 printf("\n%04x %08x ", 955, mfspr(955));
279 printf("\n%04x %08x ", 272, mfspr(272));
280 printf("\n%04x %08x ", 273, mfspr(273));
281 printf("\n%04x %08x ", 274, mfspr(274));
282 printf("\n%04x %08x ", 275, mfspr(275));
283 printf("\n%04x %08x ", 260, mfspr(260));
284 printf("\n%04x %08x ", 276, mfspr(276));
285 printf("\n%04x %08x ", 261, mfspr(261));
286 printf("\n%04x %08x ", 277, mfspr(277));
287 printf("\n%04x %08x ", 262, mfspr(262));
288 printf("\n%04x %08x ", 278, mfspr(278));
289 printf("\n%04x %08x ", 263, mfspr(263));
290 printf("\n%04x %08x ", 279, mfspr(279));
291 printf("\n%04x %08x ", 26, mfspr(26));
292 printf("\n%04x %08x ", 27, mfspr(27));
293 printf("\n%04x %08x ", 990, mfspr(990));
294 printf("\n%04x %08x ", 991, mfspr(991));
295 printf("\n%04x %08x ", 956, mfspr(956));
296 printf("\n%04x %08x ", 284, mfspr(284));
297 printf("\n%04x %08x ", 285, mfspr(285));
298 printf("\n%04x %08x ", 986, mfspr(986));
299 printf("\n%04x %08x ", 984, mfspr(984));
300 printf("\n%04x %08x ", 256, mfspr(256));
301 printf("\n%04x %08x ", 1, mfspr(1));
302 printf("\n%04x %08x ", 944, mfspr(944));
303 printf("\n");
304
305 return 0;
306}
307U_BOOT_CMD(
308 dumpspr, 1, 1, do_dumpspr,
309 "dumpspr - Dump all SPR registers\n",
310 NULL
311);
312#endif