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Vipin KUMAR7f0730a2012-05-22 00:15:54 +00001/*
2 * (C) Copyright 2010
3 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com.
4 *
5 * (C) Copyright 2012
6 * Amit Virdi, ST Microelectronics, amit.virdi@st.com.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Vipin KUMAR7f0730a2012-05-22 00:15:54 +00009 */
10
11#include <common.h>
12#include <nand.h>
13#include <asm/io.h>
14#include <linux/bitops.h>
15#include <linux/err.h>
Stefan Roese1a103c62015-09-02 14:29:12 +020016#include <linux/mtd/nand_bch.h>
Vipin KUMAR7f0730a2012-05-22 00:15:54 +000017#include <linux/mtd/nand_ecc.h>
18#include <linux/mtd/fsmc_nand.h>
19#include <asm/arch/hardware.h>
20
21static u32 fsmc_version;
22static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *)
23 CONFIG_SYS_FSMC_BASE;
24
25/*
26 * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of
27 * data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can
28 * correct 1 bit in 512 bytes
29 */
30
31static struct nand_ecclayout fsmc_ecc4_lp_layout = {
32 .eccbytes = 104,
33 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
34 9, 10, 11, 12, 13, 14,
35 18, 19, 20, 21, 22, 23, 24,
36 25, 26, 27, 28, 29, 30,
37 34, 35, 36, 37, 38, 39, 40,
38 41, 42, 43, 44, 45, 46,
39 50, 51, 52, 53, 54, 55, 56,
40 57, 58, 59, 60, 61, 62,
41 66, 67, 68, 69, 70, 71, 72,
42 73, 74, 75, 76, 77, 78,
43 82, 83, 84, 85, 86, 87, 88,
44 89, 90, 91, 92, 93, 94,
45 98, 99, 100, 101, 102, 103, 104,
46 105, 106, 107, 108, 109, 110,
47 114, 115, 116, 117, 118, 119, 120,
48 121, 122, 123, 124, 125, 126
49 },
50 .oobfree = {
51 {.offset = 15, .length = 3},
52 {.offset = 31, .length = 3},
53 {.offset = 47, .length = 3},
54 {.offset = 63, .length = 3},
55 {.offset = 79, .length = 3},
56 {.offset = 95, .length = 3},
57 {.offset = 111, .length = 3},
58 {.offset = 127, .length = 1}
59 }
60};
61
62/*
63 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
64 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
65 * bytes are free for use.
66 */
67static struct nand_ecclayout fsmc_ecc4_224_layout = {
68 .eccbytes = 104,
69 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
70 9, 10, 11, 12, 13, 14,
71 18, 19, 20, 21, 22, 23, 24,
72 25, 26, 27, 28, 29, 30,
73 34, 35, 36, 37, 38, 39, 40,
74 41, 42, 43, 44, 45, 46,
75 50, 51, 52, 53, 54, 55, 56,
76 57, 58, 59, 60, 61, 62,
77 66, 67, 68, 69, 70, 71, 72,
78 73, 74, 75, 76, 77, 78,
79 82, 83, 84, 85, 86, 87, 88,
80 89, 90, 91, 92, 93, 94,
81 98, 99, 100, 101, 102, 103, 104,
82 105, 106, 107, 108, 109, 110,
83 114, 115, 116, 117, 118, 119, 120,
84 121, 122, 123, 124, 125, 126
85 },
86 .oobfree = {
87 {.offset = 15, .length = 3},
88 {.offset = 31, .length = 3},
89 {.offset = 47, .length = 3},
90 {.offset = 63, .length = 3},
91 {.offset = 79, .length = 3},
92 {.offset = 95, .length = 3},
93 {.offset = 111, .length = 3},
94 {.offset = 127, .length = 97}
95 }
96};
97
98/*
99 * ECC placement definitions in oobfree type format
100 * There are 13 bytes of ecc for every 512 byte block and it has to be read
101 * consecutively and immediately after the 512 byte data block for hardware to
102 * generate the error bit offsets in 512 byte data
103 * Managing the ecc bytes in the following way makes it easier for software to
104 * read ecc bytes consecutive to data bytes. This way is similar to
105 * oobfree structure maintained already in u-boot nand driver
106 */
107static struct fsmc_eccplace fsmc_eccpl_lp = {
108 .eccplace = {
109 {.offset = 2, .length = 13},
110 {.offset = 18, .length = 13},
111 {.offset = 34, .length = 13},
112 {.offset = 50, .length = 13},
113 {.offset = 66, .length = 13},
114 {.offset = 82, .length = 13},
115 {.offset = 98, .length = 13},
116 {.offset = 114, .length = 13}
117 }
118};
119
120static struct nand_ecclayout fsmc_ecc4_sp_layout = {
121 .eccbytes = 13,
122 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
123 9, 10, 11, 12, 13, 14
124 },
125 .oobfree = {
126 {.offset = 15, .length = 1},
127 }
128};
129
130static struct fsmc_eccplace fsmc_eccpl_sp = {
131 .eccplace = {
132 {.offset = 0, .length = 4},
133 {.offset = 6, .length = 9}
134 }
135};
136
137static struct nand_ecclayout fsmc_ecc1_layout = {
138 .eccbytes = 24,
139 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
140 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
141 .oobfree = {
142 {.offset = 8, .length = 8},
143 {.offset = 24, .length = 8},
144 {.offset = 40, .length = 8},
145 {.offset = 56, .length = 8},
146 {.offset = 72, .length = 8},
147 {.offset = 88, .length = 8},
148 {.offset = 104, .length = 8},
149 {.offset = 120, .length = 8}
150 }
151};
152
153/* Count the number of 0's in buff upto a max of max_bits */
154static int count_written_bits(uint8_t *buff, int size, int max_bits)
155{
156 int k, written_bits = 0;
157
158 for (k = 0; k < size; k++) {
159 written_bits += hweight8(~buff[k]);
160 if (written_bits > max_bits)
161 break;
162 }
163
164 return written_bits;
165}
166
167static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
168{
169 struct nand_chip *this = mtd->priv;
170 ulong IO_ADDR_W;
171
172 if (ctrl & NAND_CTRL_CHANGE) {
173 IO_ADDR_W = (ulong)this->IO_ADDR_W;
174
175 IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
176 if (ctrl & NAND_CLE)
177 IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
178 if (ctrl & NAND_ALE)
179 IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
180
181 if (ctrl & NAND_NCE) {
182 writel(readl(&fsmc_regs_p->pc) |
183 FSMC_ENABLE, &fsmc_regs_p->pc);
184 } else {
185 writel(readl(&fsmc_regs_p->pc) &
186 ~FSMC_ENABLE, &fsmc_regs_p->pc);
187 }
188 this->IO_ADDR_W = (void *)IO_ADDR_W;
189 }
190
191 if (cmd != NAND_CMD_NONE)
192 writeb(cmd, this->IO_ADDR_W);
193}
194
195static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat,
196 u_char *read_ecc, u_char *calc_ecc)
197{
198 /* The calculated ecc is actually the correction index in data */
199 u32 err_idx[8];
200 u32 num_err, i;
201 u32 ecc1, ecc2, ecc3, ecc4;
202
203 num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF;
204
205 if (likely(num_err == 0))
206 return 0;
207
208 if (unlikely(num_err > 8)) {
209 /*
210 * This is a temporary erase check. A newly erased page read
211 * would result in an ecc error because the oob data is also
212 * erased to FF and the calculated ecc for an FF data is not
213 * FF..FF.
214 * This is a workaround to skip performing correction in case
215 * data is FF..FF
216 *
217 * Logic:
218 * For every page, each bit written as 0 is counted until these
219 * number of bits are greater than 8 (the maximum correction
220 * capability of FSMC for each 512 + 13 bytes)
221 */
222
223 int bits_ecc = count_written_bits(read_ecc, 13, 8);
224 int bits_data = count_written_bits(dat, 512, 8);
225
226 if ((bits_ecc + bits_data) <= 8) {
227 if (bits_data)
228 memset(dat, 0xff, 512);
229 return bits_data + bits_ecc;
230 }
231
232 return -EBADMSG;
233 }
234
235 ecc1 = readl(&fsmc_regs_p->ecc1);
236 ecc2 = readl(&fsmc_regs_p->ecc2);
237 ecc3 = readl(&fsmc_regs_p->ecc3);
238 ecc4 = readl(&fsmc_regs_p->sts);
239
240 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
241 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
242 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
243 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
244 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
245 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
246 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
247 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
248
249 i = 0;
250 while (i < num_err) {
251 err_idx[i] ^= 3;
252
253 if (err_idx[i] < 512 * 8)
254 __change_bit(err_idx[i], dat);
255
256 i++;
257 }
258
259 return num_err;
260}
261
262static int fsmc_read_hwecc(struct mtd_info *mtd,
263 const u_char *data, u_char *ecc)
264{
265 u_int ecc_tmp;
266 int timeout = CONFIG_SYS_HZ;
267 ulong start;
268
269 switch (fsmc_version) {
270 case FSMC_VER8:
271 start = get_timer(0);
272 while (get_timer(start) < timeout) {
273 /*
274 * Busy waiting for ecc computation
275 * to finish for 512 bytes
276 */
277 if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY)
278 break;
279 }
280
281 ecc_tmp = readl(&fsmc_regs_p->ecc1);
282 ecc[0] = (u_char) (ecc_tmp >> 0);
283 ecc[1] = (u_char) (ecc_tmp >> 8);
284 ecc[2] = (u_char) (ecc_tmp >> 16);
285 ecc[3] = (u_char) (ecc_tmp >> 24);
286
287 ecc_tmp = readl(&fsmc_regs_p->ecc2);
288 ecc[4] = (u_char) (ecc_tmp >> 0);
289 ecc[5] = (u_char) (ecc_tmp >> 8);
290 ecc[6] = (u_char) (ecc_tmp >> 16);
291 ecc[7] = (u_char) (ecc_tmp >> 24);
292
293 ecc_tmp = readl(&fsmc_regs_p->ecc3);
294 ecc[8] = (u_char) (ecc_tmp >> 0);
295 ecc[9] = (u_char) (ecc_tmp >> 8);
296 ecc[10] = (u_char) (ecc_tmp >> 16);
297 ecc[11] = (u_char) (ecc_tmp >> 24);
298
299 ecc_tmp = readl(&fsmc_regs_p->sts);
300 ecc[12] = (u_char) (ecc_tmp >> 16);
301 break;
302
303 default:
304 ecc_tmp = readl(&fsmc_regs_p->ecc1);
305 ecc[0] = (u_char) (ecc_tmp >> 0);
306 ecc[1] = (u_char) (ecc_tmp >> 8);
307 ecc[2] = (u_char) (ecc_tmp >> 16);
308 break;
309 }
310
311 return 0;
312}
313
314void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
315{
316 writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256,
317 &fsmc_regs_p->pc);
318 writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN,
319 &fsmc_regs_p->pc);
320 writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN,
321 &fsmc_regs_p->pc);
322}
323
324/*
325 * fsmc_read_page_hwecc
326 * @mtd: mtd info structure
327 * @chip: nand chip info structure
328 * @buf: buffer to store read data
Sergey Lapindfe64e22013-01-14 03:46:50 +0000329 * @oob_required: caller expects OOB data read to chip->oob_poi
Vipin KUMAR7f0730a2012-05-22 00:15:54 +0000330 * @page: page number to read
331 *
332 * This routine is needed for fsmc verison 8 as reading from NAND chip has to be
333 * performed in a strict sequence as follows:
334 * data(512 byte) -> ecc(13 byte)
335 * After this read, fsmc hardware generates and reports error data bits(upto a
336 * max of 8 bits)
337 */
338static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
Sergey Lapindfe64e22013-01-14 03:46:50 +0000339 uint8_t *buf, int oob_required, int page)
Vipin KUMAR7f0730a2012-05-22 00:15:54 +0000340{
341 struct fsmc_eccplace *fsmc_eccpl;
342 int i, j, s, stat, eccsize = chip->ecc.size;
343 int eccbytes = chip->ecc.bytes;
344 int eccsteps = chip->ecc.steps;
345 uint8_t *p = buf;
346 uint8_t *ecc_calc = chip->buffers->ecccalc;
347 uint8_t *ecc_code = chip->buffers->ecccode;
348 int off, len, group = 0;
349 uint8_t oob[13] __attribute__ ((aligned (2)));
350
351 /* Differentiate between small and large page ecc place definitions */
352 if (mtd->writesize == 512)
353 fsmc_eccpl = &fsmc_eccpl_sp;
354 else
355 fsmc_eccpl = &fsmc_eccpl_lp;
356
357 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
358
359 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
360 chip->ecc.hwctl(mtd, NAND_ECC_READ);
361 chip->read_buf(mtd, p, eccsize);
362
363 for (j = 0; j < eccbytes;) {
364 off = fsmc_eccpl->eccplace[group].offset;
365 len = fsmc_eccpl->eccplace[group].length;
366 group++;
367
368 /*
369 * length is intentionally kept a higher multiple of 2
370 * to read at least 13 bytes even in case of 16 bit NAND
371 * devices
372 */
373 if (chip->options & NAND_BUSWIDTH_16)
374 len = roundup(len, 2);
375 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
376 chip->read_buf(mtd, oob + j, len);
377 j += len;
378 }
379
380 memcpy(&ecc_code[i], oob, 13);
381 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
382
383 stat = chip->ecc.correct(mtd, p, &ecc_code[i],
384 &ecc_calc[i]);
385 if (stat < 0)
386 mtd->ecc_stats.failed++;
387 else
388 mtd->ecc_stats.corrected += stat;
389 }
390
391 return 0;
392}
393
Stefan Roese1a103c62015-09-02 14:29:12 +0200394#ifndef CONFIG_SPL_BUILD
395/*
396 * fsmc_nand_switch_ecc - switch the ECC operation between different engines
397 *
398 * @eccstrength - the number of bits that could be corrected
399 * (1 - HW, 4 - SW BCH4)
400 */
401int __maybe_unused fsmc_nand_switch_ecc(uint32_t eccstrength)
402{
403 struct nand_chip *nand;
404 struct mtd_info *mtd;
405 int err;
406
407 mtd = &nand_info[nand_curr_device];
408 nand = mtd->priv;
409
410 /* Setup the ecc configurations again */
411 if (eccstrength == 1) {
412 nand->ecc.mode = NAND_ECC_HW;
413 nand->ecc.bytes = 3;
414 nand->ecc.strength = 1;
415 nand->ecc.layout = &fsmc_ecc1_layout;
416 nand->ecc.correct = nand_correct_data;
417 } else {
418 nand->ecc.mode = NAND_ECC_SOFT_BCH;
419 nand->ecc.calculate = nand_bch_calculate_ecc;
420 nand->ecc.correct = nand_bch_correct_data;
421 nand->ecc.bytes = 7;
422 nand->ecc.strength = 4;
423 nand->ecc.layout = NULL;
424 }
425
426 /* Update NAND handling after ECC mode switch */
427 err = nand_scan_tail(mtd);
428
429 return err;
430}
431#endif /* CONFIG_SPL_BUILD */
432
Vipin KUMAR7f0730a2012-05-22 00:15:54 +0000433int fsmc_nand_init(struct nand_chip *nand)
434{
435 static int chip_nr;
436 struct mtd_info *mtd;
437 int i;
438 u32 peripid2 = readl(&fsmc_regs_p->peripid2);
439
440 fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
441 FSMC_REVISION_MSK;
442
443 writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl);
444
445#if defined(CONFIG_SYS_FSMC_NAND_16BIT)
446 writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
447 &fsmc_regs_p->pc);
448#elif defined(CONFIG_SYS_FSMC_NAND_8BIT)
449 writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
450 &fsmc_regs_p->pc);
451#else
452#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT
453#endif
454 writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1,
455 &fsmc_regs_p->pc);
456 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
457 &fsmc_regs_p->comm);
458 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
459 &fsmc_regs_p->attrib);
460
461 nand->options = 0;
462#if defined(CONFIG_SYS_FSMC_NAND_16BIT)
463 nand->options |= NAND_BUSWIDTH_16;
464#endif
465 nand->ecc.mode = NAND_ECC_HW;
466 nand->ecc.size = 512;
467 nand->ecc.calculate = fsmc_read_hwecc;
468 nand->ecc.hwctl = fsmc_enable_hwecc;
469 nand->cmd_ctrl = fsmc_nand_hwcontrol;
470 nand->IO_ADDR_R = nand->IO_ADDR_W =
471 (void __iomem *)CONFIG_SYS_NAND_BASE;
472 nand->badblockbits = 7;
473
474 mtd = &nand_info[chip_nr++];
475 mtd->priv = nand;
476
477 switch (fsmc_version) {
478 case FSMC_VER8:
479 nand->ecc.bytes = 13;
Sergey Lapindfe64e22013-01-14 03:46:50 +0000480 nand->ecc.strength = 8;
Vipin KUMAR7f0730a2012-05-22 00:15:54 +0000481 nand->ecc.correct = fsmc_bch8_correct_data;
482 nand->ecc.read_page = fsmc_read_page_hwecc;
483 if (mtd->writesize == 512)
484 nand->ecc.layout = &fsmc_ecc4_sp_layout;
485 else {
486 if (mtd->oobsize == 224)
487 nand->ecc.layout = &fsmc_ecc4_224_layout;
488 else
489 nand->ecc.layout = &fsmc_ecc4_lp_layout;
490 }
491
492 break;
493 default:
494 nand->ecc.bytes = 3;
Sergey Lapindfe64e22013-01-14 03:46:50 +0000495 nand->ecc.strength = 1;
Vipin KUMAR7f0730a2012-05-22 00:15:54 +0000496 nand->ecc.layout = &fsmc_ecc1_layout;
497 nand->ecc.correct = nand_correct_data;
498 break;
499 }
500
501 /* Detect NAND chips */
502 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
503 return -ENXIO;
504
505 if (nand_scan_tail(mtd))
506 return -ENXIO;
507
508 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
509 if (nand_register(i))
510 return -ENXIO;
511
512 return 0;
513}