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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 1a4596601fd395f3afb8f82f3f840c5e00bdd57a / . / arch / arm / cpu / tegra20-common / pinmux.c
blob: a65e9915194e2d17fe1bf9684bb2161cd74529b7 [file] [log] [blame]
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]1/*
2 * Copyright (c) 2011 The Chromium OS Authors.
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame^]4 * SPDX-License-Identifier: GPL-2.0+
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]5 */
6
Allen Martin00a27492012-08-31 08:30:00 +0000[diff] [blame]7/* Tegra20 pin multiplexing functions */
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]8
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]9#include <common.h>
Tom Warren150c2492012-09-19 15:50:56 -0700[diff] [blame]10#include <asm/io.h>
11#include <asm/arch/tegra.h>
12#include <asm/arch/pinmux.h>
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]13
14
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]15/*
16 * This defines the order of the pin mux control bits in the registers. For
17 * some reason there is no correspendence between the tristate, pin mux and
18 * pullup/pulldown registers.
19 */
20enum pmux_ctlid {
21 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
22 MUXCTL_UAA,
23 MUXCTL_UAB,
24 MUXCTL_UAC,
25 MUXCTL_UAD,
26 MUXCTL_UDA,
27 MUXCTL_RESERVED5,
28 MUXCTL_ATE,
29 MUXCTL_RM,
30
31 MUXCTL_ATB,
32 MUXCTL_RESERVED9,
33 MUXCTL_ATD,
34 MUXCTL_ATC,
35 MUXCTL_ATA,
36 MUXCTL_KBCF,
37 MUXCTL_KBCE,
38 MUXCTL_SDMMC1,
39
40 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
41 MUXCTL_GMA,
42 MUXCTL_GMC,
43 MUXCTL_HDINT,
44 MUXCTL_SLXA,
45 MUXCTL_OWC,
46 MUXCTL_SLXC,
47 MUXCTL_SLXD,
48 MUXCTL_SLXK,
49
50 MUXCTL_UCA,
51 MUXCTL_UCB,
52 MUXCTL_DTA,
53 MUXCTL_DTB,
54 MUXCTL_RESERVED28,
55 MUXCTL_DTC,
56 MUXCTL_DTD,
57 MUXCTL_DTE,
58
59 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
60 MUXCTL_DDC,
61 MUXCTL_CDEV1,
62 MUXCTL_CDEV2,
63 MUXCTL_CSUS,
64 MUXCTL_I2CP,
65 MUXCTL_KBCA,
66 MUXCTL_KBCB,
67 MUXCTL_KBCC,
68
69 MUXCTL_IRTX,
70 MUXCTL_IRRX,
71 MUXCTL_DAP1,
72 MUXCTL_DAP2,
73 MUXCTL_DAP3,
74 MUXCTL_DAP4,
75 MUXCTL_GMB,
76 MUXCTL_GMD,
77
78 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
79 MUXCTL_GME,
80 MUXCTL_GPV,
81 MUXCTL_GPU,
82 MUXCTL_SPDO,
83 MUXCTL_SPDI,
84 MUXCTL_SDB,
85 MUXCTL_SDC,
86 MUXCTL_SDD,
87
88 MUXCTL_SPIH,
89 MUXCTL_SPIG,
90 MUXCTL_SPIF,
91 MUXCTL_SPIE,
92 MUXCTL_SPID,
93 MUXCTL_SPIC,
94 MUXCTL_SPIB,
95 MUXCTL_SPIA,
96
97 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
98 MUXCTL_LPW0,
99 MUXCTL_LPW1,
100 MUXCTL_LPW2,
101 MUXCTL_LSDI,
102 MUXCTL_LSDA,
103 MUXCTL_LSPI,
104 MUXCTL_LCSN,
105 MUXCTL_LDC,
106
107 MUXCTL_LSCK,
108 MUXCTL_LSC0,
109 MUXCTL_LSC1,
110 MUXCTL_LHS,
111 MUXCTL_LVS,
112 MUXCTL_LM0,
113 MUXCTL_LM1,
114 MUXCTL_LVP0,
115
116 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
117 MUXCTL_LD0,
118 MUXCTL_LD1,
119 MUXCTL_LD2,
120 MUXCTL_LD3,
121 MUXCTL_LD4,
122 MUXCTL_LD5,
123 MUXCTL_LD6,
124 MUXCTL_LD7,
125
126 MUXCTL_LD8,
127 MUXCTL_LD9,
128 MUXCTL_LD10,
129 MUXCTL_LD11,
130 MUXCTL_LD12,
131 MUXCTL_LD13,
132 MUXCTL_LD14,
133 MUXCTL_LD15,
134
135 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
136 MUXCTL_LD16,
137 MUXCTL_LD17,
138 MUXCTL_LHP1,
139 MUXCTL_LHP2,
140 MUXCTL_LVP1,
141 MUXCTL_LHP0,
142 MUXCTL_RESERVED102,
143 MUXCTL_LPP,
144
145 MUXCTL_LDI,
146 MUXCTL_PMC,
147 MUXCTL_CRTP,
148 MUXCTL_PTA,
149 MUXCTL_RESERVED108,
150 MUXCTL_KBCD,
151 MUXCTL_GPU7,
152 MUXCTL_DTF,
153
154 MUXCTL_NONE = -1,
155};
156
157/*
158 * And this defines the order of the pullup/pulldown controls which are again
159 * in a different order
160 */
161enum pmux_pullid {
162 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
163 PUCTL_ATA,
164 PUCTL_ATB,
165 PUCTL_ATC,
166 PUCTL_ATD,
167 PUCTL_ATE,
168 PUCTL_DAP1,
169 PUCTL_DAP2,
170 PUCTL_DAP3,
171
172 PUCTL_DAP4,
173 PUCTL_DTA,
174 PUCTL_DTB,
175 PUCTL_DTC,
176 PUCTL_DTD,
177 PUCTL_DTE,
178 PUCTL_DTF,
179 PUCTL_GPV,
180
181 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
182 PUCTL_RM,
183 PUCTL_I2CP,
184 PUCTL_PTA,
185 PUCTL_GPU7,
186 PUCTL_KBCA,
187 PUCTL_KBCB,
188 PUCTL_KBCC,
189 PUCTL_KBCD,
190
191 PUCTL_SPDI,
192 PUCTL_SPDO,
193 PUCTL_GPSLXAU,
194 PUCTL_CRTP,
195 PUCTL_SLXC,
196 PUCTL_SLXD,
197 PUCTL_SLXK,
198
199 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
200 PUCTL_CDEV1,
201 PUCTL_CDEV2,
202 PUCTL_SPIA,
203 PUCTL_SPIB,
204 PUCTL_SPIC,
205 PUCTL_SPID,
206 PUCTL_SPIE,
207 PUCTL_SPIF,
208
209 PUCTL_SPIG,
210 PUCTL_SPIH,
211 PUCTL_IRTX,
212 PUCTL_IRRX,
213 PUCTL_GME,
214 PUCTL_RESERVED45,
215 PUCTL_XM2D,
216 PUCTL_XM2C,
217
218 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
219 PUCTL_UAA,
220 PUCTL_UAB,
221 PUCTL_UAC,
222 PUCTL_UAD,
223 PUCTL_UCA,
224 PUCTL_UCB,
225 PUCTL_LD17,
226 PUCTL_LD19_18,
227
228 PUCTL_LD21_20,
229 PUCTL_LD23_22,
230 PUCTL_LS,
231 PUCTL_LC,
232 PUCTL_CSUS,
233 PUCTL_DDRC,
234 PUCTL_SDC,
235 PUCTL_SDD,
236
237 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
238 PUCTL_KBCF,
239 PUCTL_KBCE,
240 PUCTL_PMCA,
241 PUCTL_PMCB,
242 PUCTL_PMCC,
243 PUCTL_PMCD,
244 PUCTL_PMCE,
245 PUCTL_CK32,
246
247 PUCTL_UDA,
248 PUCTL_SDMMC1,
249 PUCTL_GMA,
250 PUCTL_GMB,
251 PUCTL_GMC,
252 PUCTL_GMD,
253 PUCTL_DDC,
254 PUCTL_OWC,
255
256 PUCTL_NONE = -1
257};
258
259struct tegra_pingroup_desc {
260 const char *name;
261 enum pmux_func funcs[4];
262 enum pmux_func func_safe;
263 enum pmux_vddio vddio;
264 enum pmux_ctlid ctl_id;
265 enum pmux_pullid pull_id;
266};
267
268
269/* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
270#define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
271
272/* Mask value for a tristate (within TRISTATE_REG(id)) */
273#define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
274
275/* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
276#define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
277
278/* Converts a PUCTL id to a shift position */
279#define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
280
281/* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
282#define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
283
284/* Converts a MUXCTL id to a shift position */
285#define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
286
287/* Convenient macro for defining pin group properties */
288#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
289 { \
290 .vddio = PMUX_VDDIO_ ## vdd, \
291 .funcs = { \
292 PMUX_FUNC_ ## f0, \
293 PMUX_FUNC_ ## f1, \
294 PMUX_FUNC_ ## f2, \
295 PMUX_FUNC_ ## f3, \
296 }, \
297 .func_safe = PMUX_FUNC_ ## f_safe, \
298 .ctl_id = mux, \
299 .pull_id = pupd \
300 }
301
302/* A normal pin group where the mux name and pull-up name match */
303#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
304 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
305 MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
306
307/* A pin group where the pull-up name doesn't have a 1-1 mapping */
308#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
309 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
310 MUXCTL_ ## pg_name, PUCTL_ ## pupd)
311
312/* A pin group number which is not used */
313#define PIN_RESERVED \
314 PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
315
316const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
317 PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
318 PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
319 PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
320 PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
321 PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
322 PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
323 PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
324 PLLC_OUT1),
325 PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
326
327 PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
328 PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
329 PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
330 PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
331 PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
332 PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
333 PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
334 PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
335
336 PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
337 GPSLXAU),
338 PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
339 PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
340 PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
341 PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
342 PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
343 PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
344 PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
345
346 PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
347 PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
348 PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
349 PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
350 PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
351 PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
352 PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
353 PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
354
355 PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
356 PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
357 PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
358 PIN_RESERVED,
359 PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
360 PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
361 PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
362 PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
363
364 PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
365 PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
366 PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
367 PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
368 PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
369 PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
370 PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
371 PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
372
373 PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
374 PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
375 PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
376 PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
377 PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
Allen Martind08b9e92013-01-09 10:52:23 +0000[diff] [blame]378 PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]379 PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
380 PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
381
382 PIN_RESERVED,
383 PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
384 PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
385 PIN_RESERVED,
386 PIN_RESERVED,
387 PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
388 PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
389 PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
390
391 /* 64 */
392 PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
393 PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
394 PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
395 PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
396 PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
397 PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
398 PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
399 PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
400
401 PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
402 PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
403 PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
404 PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
405 PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
406 PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
407 PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
408 PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
409
410 PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
411 PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
412 PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
413 PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
414 PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
415 PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
416 PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
417 PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
418
419 PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
420 PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
421 PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
422 PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
423 PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
424 PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
425 PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
426 PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
427
428 /* 96 */
429 PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
430 PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
431 PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
432 PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
433 PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
434 PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
435 PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
436 PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
437
438 PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
439 PIN_RESERVED,
440 PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
441 PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
442 PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
443 PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
444 PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
445 PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
446
447 /* these pin groups only have pullup and pull down control */
448 PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
449 PUCTL_NONE),
450 PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
451 PUCTL_NONE),
452 PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
453 PUCTL_NONE),
454 PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
455 PUCTL_NONE),
456 PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
457 PUCTL_NONE),
458 PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
459 PUCTL_NONE),
460 PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
461 PUCTL_NONE),
462 PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
463 PUCTL_NONE),
464 PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
465 PUCTL_NONE),
466};
467
Simon Glassc3cf49d2011-09-21 12:40:05 +0000[diff] [blame]468void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]469{
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]470 struct pmux_tri_ctlr *pmt =
471 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]472 u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
473 u32 reg;
474
475 reg = readl(tri);
476 if (enable)
477 reg |= TRISTATE_MASK(pin);
478 else
479 reg &= ~TRISTATE_MASK(pin);
480 writel(reg, tri);
481}
482
Simon Glassc3cf49d2011-09-21 12:40:05 +0000[diff] [blame]483void pinmux_tristate_enable(enum pmux_pingrp pin)
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]484{
485 pinmux_set_tristate(pin, 1);
486}
487
Simon Glassc3cf49d2011-09-21 12:40:05 +0000[diff] [blame]488void pinmux_tristate_disable(enum pmux_pingrp pin)
Simon Glass858bd092011-08-30 06:23:14 +0000[diff] [blame]489{
490 pinmux_set_tristate(pin, 0);
491}
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]492
493void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
494{
495 struct pmux_tri_ctlr *pmt =
496 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
497 enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
498 u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
499 u32 mask_bit;
500 u32 reg;
501 mask_bit = PULL_SHIFT(pull_id);
502
503 reg = readl(pull);
504 reg &= ~(0x3 << mask_bit);
505 reg |= pupd << mask_bit;
506 writel(reg, pull);
507}
508
509void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
510{
511 struct pmux_tri_ctlr *pmt =
512 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
513 enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
514 u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
515 u32 mask_bit;
516 int i, mux = -1;
517 u32 reg;
518
519 assert(pmux_func_isvalid(func));
520
521 /* Handle special values */
522 if (func >= PMUX_FUNC_RSVD1) {
523 mux = (func - PMUX_FUNC_RSVD1) & 0x3;
524 } else {
525 /* Search for the appropriate function */
526 for (i = 0; i < 4; i++) {
527 if (tegra_soc_pingroups[pin].funcs[i] == func) {
528 mux = i;
529 break;
530 }
531 }
532 }
533 assert(mux != -1);
534
535 mask_bit = MUXCTL_SHIFT(mux_id);
536 reg = readl(muxctl);
537 reg &= ~(0x3 << mask_bit);
538 reg |= mux << mask_bit;
539 writel(reg, muxctl);
540}
541
Simon Glass95be58c2012-10-17 13:24:45 +0000[diff] [blame]542void pinmux_config_pingroup(const struct pingroup_config *config)
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]543{
544 enum pmux_pingrp pin = config->pingroup;
545
546 pinmux_set_func(pin, config->func);
547 pinmux_set_pullupdown(pin, config->pull);
548 pinmux_set_tristate(pin, config->tristate);
549}
550
Simon Glass95be58c2012-10-17 13:24:45 +0000[diff] [blame]551void pinmux_config_table(const struct pingroup_config *config, int len)
Simon Glass20e18e02011-09-21 12:40:06 +0000[diff] [blame]552{
553 int i;
554
555 for (i = 0; i < len; i++)
556 pinmux_config_pingroup(&config[i]);
557}