blob: 8a86819fb52ab0010cd1975af4e36328fada5761 [file] [log] [blame]
Kumar Gala2a6c2d72008-08-26 21:34:55 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/fsl_ddr_sdram.h>
12
13#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
14#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
15#endif
16
17void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
18 unsigned int ctrl_num)
19{
20 unsigned int i;
Andy Fleminge76cd5d2012-10-23 19:03:46 -050021 volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
Kumar Gala2a6c2d72008-08-26 21:34:55 -050022
23 if (ctrl_num != 0) {
24 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
25 return;
26 }
27
28 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
29 if (i == 0) {
30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
31 out_be32(&ddr->cs0_config, regs->cs[i].config);
32
33 } else if (i == 1) {
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
35 out_be32(&ddr->cs1_config, regs->cs[i].config);
36
37 } else if (i == 2) {
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
39 out_be32(&ddr->cs2_config, regs->cs[i].config);
40
41 } else if (i == 3) {
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
43 out_be32(&ddr->cs3_config, regs->cs[i].config);
44 }
45 }
46
47 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
48 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
49 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
50 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
51#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
52 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
53#endif
54
55 /*
56 * 200 painful micro-seconds must elapse between
57 * the DDR clock setup and the DDR config enable.
58 */
59 udelay(200);
60 asm volatile("sync;isync");
61
62 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
63
64 asm("sync;isync;msync");
65 udelay(500);
66}
67
68#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
Kumar Gala2a6c2d72008-08-26 21:34:55 -050069/*
70 * Initialize all of memory for ECC, then enable errors.
71 */
72
73void
74ddr_enable_ecc(unsigned int dram_size)
75{
Andy Fleminge76cd5d2012-10-23 19:03:46 -050076 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
Kumar Gala2a6c2d72008-08-26 21:34:55 -050077
Peter Tyser0d595f72009-06-30 17:15:48 -050078 dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
Kumar Gala2a6c2d72008-08-26 21:34:55 -050079
80 /*
81 * Enable errors for ECC.
82 */
83 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
84 ddr->err_disable = 0x00000000;
85 asm("sync;isync;msync");
86 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
87}
88
89#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */