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Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09001/*
Wolfgang Denk1a459662013-07-08 09:37:19 +02002 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09003 */
4
5#include <common.h>
6#include <asm/processor.h>
Nobuhiro Iwamatsu754613f2010-06-16 16:55:26 +09007#include <asm/system.h>
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +09008#include <asm/io.h>
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09009
10#define WDT_BASE WTCNT
11
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090012#define WDT_WD (1 << 6)
13#define WDT_RST_P (0)
14#define WDT_RST_M (1 << 5)
15#define WDT_ENABLE (1 << 7)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090016
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090017#if defined(CONFIG_WATCHDOG)
18static unsigned char csr_read(void)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090019{
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090020 return inb(WDT_BASE + 0x04);
21}
22
23static void cnt_write(unsigned char value)
24{
25 outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
26}
27
28static void csr_write(unsigned char value)
29{
30 outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
31}
32
33void watchdog_reset(void)
34{
35 outl(0x55000000, WDT_BASE + 0x08);
36}
37
38int watchdog_init(void)
39{
40 /* Set overflow time*/
41 cnt_write(0);
42 /* Power on reset */
43 csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
44
45 return 0;
46}
47
48int watchdog_disable(void)
49{
50 csr_write(csr_read() & ~WDT_ENABLE);
51 return 0;
52}
53#endif
54
55void reset_cpu(unsigned long ignored)
56{
Nobuhiro Iwamatsu754613f2010-06-16 16:55:26 +090057 /* Address error with SR.BL=1 first. */
58 trigger_address_error();
59
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090060 while (1)
61 ;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090062}