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Stefan Roese16c0cc12007-03-21 13:39:57 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese16c0cc12007-03-21 13:39:57 +01006 */
7
8#include <common.h>
9#include <asm/processor.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020010#include <asm/ppc405.h>
Stefan Roese16c0cc12007-03-21 13:39:57 +010011
12/* test-only: move into cpu directory!!! */
13
14#if defined(PLLMR0_200_133_66)
15void board_pll_init_f(void)
16{
17 /*
18 * set PLL clocks based on input sysclk is 33M
19 *
20 * ----------------------------------
21 * | CLK | FREQ (MHz) | DIV RATIO |
22 * ----------------------------------
23 * | CPU | 200.0 | 4 (0x02)|
24 * | PLB | 133.3 | 6 (0x06)|
25 * | OPB | 66.6 | 12 (0x0C)|
26 * | EBC | 66.6 | 12 (0x0C)|
27 * | SPI | 66.6 | 12 (0x0C)|
28 * | UART0 | 10.0 | 40 (0x28)|
29 * | UART1 | 10.0 | 40 (0x28)|
30 * | DAC | 2.0 | 200 (0xC8)|
31 * | ADC | 2.0 | 200 (0xC8)|
32 * | PWM | 100.0 | 4 (0x04)|
33 * | EMAC | 25.0 | 16 (0x10)|
34 * -----------------------------------
35 */
36
37 /* Initialize PLL */
Stefan Roesed1c3b272009-09-09 16:25:29 +020038 mtcpr(CPR0_PLLC, 0x0000033c);
39 mtcpr(CPR0_PLLD, 0x0c010200);
Stefan Roeseafabb492010-09-12 06:21:37 +020040 mtcpr(CPR0_PRIMAD, 0x04060c0c);
41 mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
42 mtcpr(CPR0_CLKUPD, 0x40000000);
Stefan Roese16c0cc12007-03-21 13:39:57 +010043}
44
45#elif defined(PLLMR0_266_160_80)
46
47void board_pll_init_f(void)
48{
49 /*
50 * set PLL clocks based on input sysclk is 33M
51 *
52 * ----------------------------------
53 * | CLK | FREQ (MHz) | DIV RATIO |
54 * ----------------------------------
55 * | CPU | 266.64 | 3 |
56 * | PLB | 159.98 | 5 (0x05)|
57 * | OPB | 79.99 | 10 (0x0A)|
58 * | EBC | 79.99 | 10 (0x0A)|
59 * | SPI | 79.99 | 10 (0x0A)|
60 * | UART0 | 28.57 | 7 (0x07)|
61 * | UART1 | 28.57 | 7 (0x07)|
62 * | DAC | 28.57 | 7 (0xA7)|
Stefan Roese3cb86f32007-03-24 15:45:34 +010063 * | ADC | 4 | 50 (0x32)|
Stefan Roese16c0cc12007-03-21 13:39:57 +010064 * | PWM | 28.57 | 7 (0x07)|
65 * | EMAC | 4 | 50 (0x32)|
66 * -----------------------------------
67 */
68
69 /* Initialize PLL */
Stefan Roesed1c3b272009-09-09 16:25:29 +020070 mtcpr(CPR0_PLLC, 0x20000238);
71 mtcpr(CPR0_PLLD, 0x03010400);
Stefan Roeseafabb492010-09-12 06:21:37 +020072 mtcpr(CPR0_PRIMAD, 0x03050a0a);
73 mtcpr(CPR0_PERC0, 0x00000000);
74 mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
75 mtcpr(CPR0_PERD1, 0x07323200);
Stefan Roesed1c3b272009-09-09 16:25:29 +020076 mtcpr(CPR0_CLKUP, 0x40000000);
Stefan Roese16c0cc12007-03-21 13:39:57 +010077}
78
79#elif defined(PLLMR0_333_166_83)
80
81void board_pll_init_f(void)
82{
83 /*
84 * set PLL clocks based on input sysclk is 33M
85 *
86 * ----------------------------------
87 * | CLK | FREQ (MHz) | DIV RATIO |
88 * ----------------------------------
89 * | CPU | 333.33 | 2 |
90 * | PLB | 166.66 | 4 (0x04)|
91 * | OPB | 83.33 | 8 (0x08)|
92 * | EBC | 83.33 | 8 (0x08)|
93 * | SPI | 83.33 | 8 (0x08)|
94 * | UART0 | 16.66 | 5 (0x05)|
95 * | UART1 | 16.66 | 5 (0x05)|
96 * | DAC | ???? | 166 (0xA6)|
97 * | ADC | ???? | 166 (0xA6)|
98 * | PWM | 41.66 | 3 (0x03)|
99 * | EMAC | ???? | 3 (0x03)|
100 * -----------------------------------
101 */
102
103 /* Initialize PLL */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200104 mtcpr(CPR0_PLLC, 0x0000033C);
105 mtcpr(CPR0_PLLD, 0x0a010000);
Stefan Roeseafabb492010-09-12 06:21:37 +0200106 mtcpr(CPR0_PRIMAD, 0x02040808);
107 mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
108 mtcpr(CPR0_PERD1, 0xA6A60300);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200109 mtcpr(CPR0_CLKUP, 0x40000000);
Stefan Roese16c0cc12007-03-21 13:39:57 +0100110}
111
112#elif defined(PLLMR0_100_100_12)
113
114void board_pll_init_f(void)
115{
116 /*
117 * set PLL clocks based on input sysclk is 33M
118 *
119 * ----------------------
120 * | CLK | FREQ (MHz) |
121 * ----------------------
122 * | CPU | 100.00 |
123 * | PLB | 100.00 |
124 * | OPB | 12.00 |
125 * | EBC | 49.00 |
126 * ----------------------
127 */
128
129 /* Initialize PLL */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200130 mtcpr(CPR0_PLLC, 0x000003BC);
131 mtcpr(CPR0_PLLD, 0x06060600);
Stefan Roeseafabb492010-09-12 06:21:37 +0200132 mtcpr(CPR0_PRIMAD, 0x02020004);
133 mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
134 mtcpr(CPR0_PERD1, 0xC8C81600);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200135 mtcpr(CPR0_CLKUP, 0x40000000);
Stefan Roese16c0cc12007-03-21 13:39:57 +0100136}
Stefan Roese3cb86f32007-03-24 15:45:34 +0100137#endif /* CPU_<speed>_405EZ */
Stefan Roese16c0cc12007-03-21 13:39:57 +0100138
139#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
140/*
141 * Get timebase clock frequency
142 */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100143unsigned long get_tbclk(void)
Stefan Roese16c0cc12007-03-21 13:39:57 +0100144{
145 unsigned long cpr_plld;
146 unsigned long cpr_primad;
147 unsigned long primad_cpudv;
148 unsigned long pllFbkDiv;
149 unsigned long freqProcessor;
150
151 /*
152 * Read PLL Mode registers
153 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200154 mfcpr(CPR0_PLLD, cpr_plld);
Stefan Roese16c0cc12007-03-21 13:39:57 +0100155
156 /*
157 * Read CPR_PRIMAD register
158 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200159 mfcpr(CPR0_PRIMAD, cpr_primad);
Stefan Roese16c0cc12007-03-21 13:39:57 +0100160
161 /*
162 * Determine CPU clock frequency
163 */
164 primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
165 if (primad_cpudv == 0)
166 primad_cpudv = 16;
167
168 /*
169 * Determine FBK_DIV.
170 */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100171 pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
172 if (pllFbkDiv == 0)
173 pllFbkDiv = 256;
Stefan Roese16c0cc12007-03-21 13:39:57 +0100174
175 freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
176
177 return (freqProcessor);
178}
Stefan Roese3cb86f32007-03-24 15:45:34 +0100179#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */