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Sergey Kubushync74b2102007-08-10 20:26:18 +02001/*
2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3 *
4 * Board-specific low level initialization code. Called at the very end
Peter Tyser84ad6882010-04-12 22:28:11 -05005 * of arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
Sergey Kubushync74b2102007-08-10 20:26:18 +02006 * initialization required.
7 *
8 * For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
9 * Sonata boards, AFAIK, don't use this so it's just return by default. Ask
10 * Visioneering if they reinvented the wheel once again to make sure :)
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Sergey Kubushync74b2102007-08-10 20:26:18 +020013 */
14
15#include <config.h>
16
17.globl dv_board_init
18dv_board_init:
19#ifdef SONATA_BOARD_GPIOWP
20 /* Set PINMUX0 to enable GPIO4 */
21 ldr r0, _PINMUX0
22 ldr r1, GPIO4_EN_MASK
23 ldr r2, [r0]
24 and r2, r2, r1
25 str r2, [r0]
26
27 /* Enable GPIO LPSC module */
28 ldr r0, PTSTAT
29
30gpio_ptstat_loop1:
31 ldr r2, [r0]
32 tst r2, $0x00000001
33 bne gpio_ptstat_loop1
34
35 ldr r1, MDCTL_GPIO
36 ldr r2, [r1]
37 and r2, r2, $0xfffffff8
38 orr r2, r2, $0x00000003
39 str r2, [r1]
40
41 orr r2, r2, $0x00000200
42 str r2, [r1]
43
44 ldr r1, PTCMD
45 mov r2, $0x00000001
46 str r2, [r1]
47
48gpio_ptstat_loop2:
49 ldr r2, [r0]
50 tst r2, $0x00000001
51 bne gpio_ptstat_loop2
52
53 ldr r0, MDSTAT_GPIO
54gpio_mdstat_loop:
55 ldr r2, [r0]
56 and r2, r2, $0x0000001f
57 teq r2, $0x00000003
58 bne gpio_mdstat_loop
59
60 /* GPIO4 -> output */
61 ldr r0, GPIO_DIR01
62 mov r1, $0x10
63 ldr r2, [r0]
64 bic r2, r2, r0
65 str r2, [r0]
66
67 /* Set it to 0 (Write Protect) */
68 ldr r0, GPIO_CLR_DATA01
69 str r1, [r0]
70#endif
71
72 mov pc, lr
73
74#ifdef SONATA_BOARD_GPIOWP
75.ltorg
76
77GPIO4_EN_MASK:
78 .word 0xf77fffff
79MDCTL_GPIO:
80 .word 0x01c41a68
81MDSTAT_GPIO:
82 .word 0x01c41868
83GPIO_DIR01:
84 .word 0x01c67010
85GPIO_CLR_DATA01:
86 .word 0x01c6701c
87#endif