Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007-2008 |
Stelian Pop | c9e798d | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 3 | * Stelian Pop <stelian@popies.net> |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 4 | * Lead Tech Design <www.leadtechdesign.com> |
| 5 | * |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 6 | * (C) Copyright 2009-2011 |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 7 | * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> |
| 8 | * esd electronic system design gmbh <www.esd.eu> |
| 9 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #include <common.h> |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 14 | #include <asm/io.h> |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 15 | #include <asm/arch/at91sam9_smc.h> |
| 16 | #include <asm/arch/at91_common.h> |
| 17 | #include <asm/arch/at91_pmc.h> |
| 18 | #include <asm/arch/at91_rstc.h> |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 19 | #include <asm/arch/at91_matrix.h> |
| 20 | #include <asm/arch/at91_pio.h> |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 21 | #include <asm/arch/clk.h> |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 22 | #include <netdev.h> |
| 23 | |
| 24 | DECLARE_GLOBAL_DATA_PTR; |
| 25 | |
| 26 | /* |
| 27 | * Miscelaneous platform dependent initialisations |
| 28 | */ |
| 29 | |
| 30 | static int hw_rev = -1; /* hardware revision */ |
| 31 | |
| 32 | int get_hw_rev(void) |
| 33 | { |
| 34 | if (hw_rev >= 0) |
| 35 | return hw_rev; |
| 36 | |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 37 | hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); |
| 38 | hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; |
| 39 | hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; |
| 40 | hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 41 | |
| 42 | if (hw_rev == 15) |
| 43 | hw_rev = 0; |
| 44 | |
| 45 | return hw_rev; |
| 46 | } |
| 47 | |
| 48 | #ifdef CONFIG_CMD_NAND |
| 49 | static void meesc_nand_hw_init(void) |
| 50 | { |
| 51 | unsigned long csa; |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 52 | at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; |
| 53 | at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 54 | |
| 55 | /* Enable CS3 */ |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 56 | csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; |
| 57 | writel(csa, &matrix->csa[0]); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 58 | |
| 59 | /* Configure SMC CS3 for NAND/SmartMedia */ |
Daniel Gorsulowski | dd80264 | 2012-01-25 03:19:49 +0000 | [diff] [blame] | 60 | writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | |
| 61 | AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2), |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 62 | &smc->cs[3].setup); |
| 63 | |
| 64 | writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | |
| 65 | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), |
| 66 | &smc->cs[3].pulse); |
| 67 | |
Daniel Gorsulowski | dd80264 | 2012-01-25 03:19:49 +0000 | [diff] [blame] | 68 | writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 69 | &smc->cs[3].cycle); |
| 70 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | |
| 71 | AT91_SMC_MODE_EXNW_DISABLE | |
| 72 | AT91_SMC_MODE_DBW_8 | |
Daniel Gorsulowski | dd80264 | 2012-01-25 03:19:49 +0000 | [diff] [blame] | 73 | AT91_SMC_MODE_TDF_CYCLE(12), |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 74 | &smc->cs[3].mode); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 75 | |
| 76 | /* Configure RDY/BSY */ |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 77 | at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 78 | |
| 79 | /* Enable NandFlash */ |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 80 | at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 81 | } |
| 82 | #endif /* CONFIG_CMD_NAND */ |
| 83 | |
| 84 | #ifdef CONFIG_MACB |
| 85 | static void meesc_macb_hw_init(void) |
| 86 | { |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 87 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 88 | /* Enable clock */ |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 89 | writel(1 << ATMEL_ID_EMAC, &pmc->pcer); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 90 | at91_macb_hw_init(); |
| 91 | } |
| 92 | #endif |
| 93 | |
| 94 | /* |
| 95 | * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT |
| 96 | * controller debugging |
| 97 | * The ET1100 is located at physical address 0x70000000 |
| 98 | * Its process memory is located at physical address 0x70001000 |
| 99 | */ |
| 100 | static void meesc_ethercat_hw_init(void) |
| 101 | { |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 102 | at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 103 | |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 104 | /* Configure SMC EBI1_CS0 for EtherCAT */ |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 105 | writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | |
| 106 | AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), |
| 107 | &smc1->cs[0].setup); |
| 108 | writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | |
| 109 | AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), |
| 110 | &smc1->cs[0].pulse); |
| 111 | writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), |
| 112 | &smc1->cs[0].cycle); |
Daniel Gorsulowski | a380279 | 2009-09-29 08:03:12 +0200 | [diff] [blame] | 113 | /* |
| 114 | * Configure behavior at external wait signal, byte-select mode, 16 bit |
| 115 | * data bus width, none data float wait states and TDF optimization |
| 116 | */ |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 117 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | |
| 118 | AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | |
| 119 | AT91_SMC_MODE_TDF, &smc1->cs[0].mode); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 120 | |
| 121 | /* Configure RDY/BSY */ |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 122 | at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | int dram_init(void) |
| 126 | { |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 127 | gd->ram_size = get_ram_size( |
| 128 | (void *)CONFIG_SYS_SDRAM_BASE, |
| 129 | CONFIG_SYS_SDRAM_SIZE); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | int board_eth_init(bd_t *bis) |
| 134 | { |
| 135 | int rc = 0; |
| 136 | #ifdef CONFIG_MACB |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 137 | rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 138 | #endif |
| 139 | return rc; |
| 140 | } |
| 141 | |
| 142 | int checkboard(void) |
| 143 | { |
| 144 | char str[32]; |
Daniel Gorsulowski | a380279 | 2009-09-29 08:03:12 +0200 | [diff] [blame] | 145 | u_char hw_type; /* hardware type */ |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 146 | |
Daniel Gorsulowski | a380279 | 2009-09-29 08:03:12 +0200 | [diff] [blame] | 147 | /* read the "Type" register of the ET1100 controller */ |
| 148 | hw_type = readb(CONFIG_ET1100_BASE); |
| 149 | |
| 150 | switch (hw_type) { |
| 151 | case 0x11: |
| 152 | case 0x3F: |
| 153 | /* ET1100 present, arch number of MEESC-Board */ |
| 154 | gd->bd->bi_arch_number = MACH_TYPE_MEESC; |
| 155 | puts("Board: CAN-EtherCAT Gateway"); |
| 156 | break; |
| 157 | case 0xFF: |
| 158 | /* no ET1100 present, arch number of EtherCAN/2-Board */ |
| 159 | gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; |
| 160 | puts("Board: EtherCAN/2 Gateway"); |
| 161 | /* switch on LED1D */ |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 162 | at91_set_pio_output(AT91_PIO_PORTB, 12, 1); |
Daniel Gorsulowski | a380279 | 2009-09-29 08:03:12 +0200 | [diff] [blame] | 163 | break; |
| 164 | default: |
| 165 | /* assume, no ET1100 present, arch number of EtherCAN/2-Board */ |
| 166 | gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; |
| 167 | printf("ERROR! Read invalid hw_type: %02X\n", hw_type); |
| 168 | puts("Board: EtherCAN/2 Gateway"); |
| 169 | break; |
| 170 | } |
Wolfgang Denk | cdb7497 | 2010-07-24 21:55:43 +0200 | [diff] [blame] | 171 | if (getenv_f("serial#", str, sizeof(str)) > 0) { |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 172 | puts(", serial# "); |
| 173 | puts(str); |
| 174 | } |
| 175 | printf("\nHardware-revision: 1.%d\n", get_hw_rev()); |
| 176 | printf("Mach-type: %lu\n", gd->bd->bi_arch_number); |
| 177 | return 0; |
| 178 | } |
| 179 | |
Daniel Gorsulowski | a380279 | 2009-09-29 08:03:12 +0200 | [diff] [blame] | 180 | #ifdef CONFIG_SERIAL_TAG |
| 181 | void get_board_serial(struct tag_serialnr *serialnr) |
| 182 | { |
| 183 | char *str; |
| 184 | |
| 185 | char *serial = getenv("serial#"); |
| 186 | if (serial) { |
| 187 | str = strchr(serial, '_'); |
| 188 | if (str && (strlen(str) >= 4)) { |
| 189 | serialnr->high = (*(str + 1) << 8) | *(str + 2); |
| 190 | serialnr->low = simple_strtoul(str + 3, NULL, 16); |
| 191 | } |
| 192 | } else { |
| 193 | serialnr->high = 0; |
| 194 | serialnr->low = 0; |
| 195 | } |
| 196 | } |
| 197 | #endif |
| 198 | |
| 199 | #ifdef CONFIG_REVISION_TAG |
| 200 | u32 get_board_rev(void) |
| 201 | { |
| 202 | return hw_rev | 0x100; |
| 203 | } |
| 204 | #endif |
| 205 | |
Daniel Gorsulowski | a3f3897 | 2010-01-20 08:00:11 +0100 | [diff] [blame] | 206 | #ifdef CONFIG_MISC_INIT_R |
| 207 | int misc_init_r(void) |
| 208 | { |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 209 | char *str; |
| 210 | char buf[32]; |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 211 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
Daniel Gorsulowski | a3f3897 | 2010-01-20 08:00:11 +0100 | [diff] [blame] | 212 | |
| 213 | /* |
| 214 | * Normally the processor clock has a divisor of 2. |
| 215 | * In some cases this this needs to be set to 4. |
| 216 | * Check the user has set environment mdiv to 4 to change the divisor. |
| 217 | */ |
| 218 | if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) { |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 219 | writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | |
| 220 | AT91SAM9_PMC_MDIV_4, &pmc->mckr); |
| 221 | at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); |
Daniel Gorsulowski | a3f3897 | 2010-01-20 08:00:11 +0100 | [diff] [blame] | 222 | serial_setbrg(); |
| 223 | /* Notify the user that the clock is not default */ |
| 224 | printf("Setting master clock to %s MHz\n", |
| 225 | strmhz(buf, get_mck_clk_rate())); |
| 226 | } |
| 227 | |
| 228 | return 0; |
| 229 | } |
| 230 | #endif /* CONFIG_MISC_INIT_R */ |
| 231 | |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 232 | int board_early_init_f(void) |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 233 | { |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 234 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 235 | |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 236 | /* enable all clocks */ |
| 237 | writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | |
| 238 | (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP), |
Daniel Gorsulowski | d4562e0 | 2010-08-09 11:17:14 +0200 | [diff] [blame] | 239 | &pmc->pcer); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 240 | |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 241 | at91_seriald_hw_init(); |
| 242 | |
| 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | int board_init(void) |
| 247 | { |
Daniel Gorsulowski | a380279 | 2009-09-29 08:03:12 +0200 | [diff] [blame] | 248 | /* initialize ET1100 Controller */ |
| 249 | meesc_ethercat_hw_init(); |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 250 | |
| 251 | /* adress of boot parameters */ |
Matthias Fuchs | 0cb77bf | 2011-07-19 01:56:06 +0000 | [diff] [blame] | 252 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 253 | |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 254 | #ifdef CONFIG_CMD_NAND |
| 255 | meesc_nand_hw_init(); |
| 256 | #endif |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 257 | #ifdef CONFIG_HAS_DATAFLASH |
| 258 | at91_spi0_hw_init(1 << 0); |
| 259 | #endif |
| 260 | #ifdef CONFIG_MACB |
| 261 | meesc_macb_hw_init(); |
| 262 | #endif |
| 263 | #ifdef CONFIG_AT91_CAN |
| 264 | at91_can_hw_init(); |
| 265 | #endif |
Daniel Gorsulowski | 64037fb | 2010-08-09 11:17:15 +0200 | [diff] [blame] | 266 | #ifdef CONFIG_USB_OHCI_NEW |
| 267 | at91_uhp_hw_init(); |
| 268 | #endif |
Daniel Gorsulowski | 33b1d3f | 2009-06-30 21:03:37 +0200 | [diff] [blame] | 269 | return 0; |
| 270 | } |