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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 1a4596601fd395f3afb8f82f3f840c5e00bdd57a / . / board / freescale / b4860qds / tlb.c
blob: f71aca4092000d2d6dc2463f6ab5961bfef9e7fe [file] [log] [blame]
York Sunb5b06fb2012-12-23 19:25:27 +0000[diff] [blame]1/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame^]4 * SPDX-License-Identifier: GPL-2.0+
York Sunb5b06fb2012-12-23 19:25:27 +0000[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/mmu.h>
9
10struct fsl_e_tlb_entry tlb_table[] = {
11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
13 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
14 MAS3_SX|MAS3_SW|MAS3_SR, 0,
15 0, 0, BOOKE_PAGESZ_4K, 0),
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
22 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
26 MAS3_SX|MAS3_SW|MAS3_SR, 0,
27 0, 0, BOOKE_PAGESZ_4K, 0),
28
29 /* TLB 1 */
30 /* *I*** - Covers boot page */
31#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
32 /*
33 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
34 * SRAM is at 0xfff00000, it covered the 0xfffff000.
35 */
36 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
37 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
38 0, 0, BOOKE_PAGESZ_1M, 1),
Liu Gang5870fe42013-05-07 16:30:48 +0800[diff] [blame]39#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
40 /*
41 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
42 * space is at 0xfff00000, it covered the 0xfffff000.
43 */
44 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
45 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
46 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
47 0, 0, BOOKE_PAGESZ_1M, 1),
York Sunb5b06fb2012-12-23 19:25:27 +0000[diff] [blame]48#else
49 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
51 0, 0, BOOKE_PAGESZ_4K, 1),
52#endif
53
54 /* *I*G* - CCSRBAR */
55 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
57 0, 1, BOOKE_PAGESZ_16M, 1),
58
59 /* *I*G* - Flash, localbus */
60 /* This will be changed to *I*G* after relocation to RAM. */
61 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
62 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
63 0, 2, BOOKE_PAGESZ_256M, 1),
64
65 /* *I*G* - PCI */
66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 0, 3, BOOKE_PAGESZ_256M, 1),
69
70 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
71 CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, 4, BOOKE_PAGESZ_256M, 1),
74
75 /* *I*G* - PCI I/O */
76 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
77 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
78 0, 5, BOOKE_PAGESZ_64K, 1),
79
80 /* Bman/Qman */
81#ifdef CONFIG_SYS_BMAN_MEM_PHYS
82 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
83 MAS3_SX|MAS3_SW|MAS3_SR, 0,
84 0, 6, BOOKE_PAGESZ_16M, 1),
85 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
86 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
87 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
88 0, 7, BOOKE_PAGESZ_16M, 1),
89#endif
90#ifdef CONFIG_SYS_QMAN_MEM_PHYS
91 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
92 MAS3_SX|MAS3_SW|MAS3_SR, 0,
93 0, 8, BOOKE_PAGESZ_16M, 1),
94 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
95 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
96 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
97 0, 9, BOOKE_PAGESZ_16M, 1),
98#endif
99#ifdef CONFIG_SYS_DCSRBAR_PHYS
100 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
101 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Stephen George49e946c2013-03-25 07:40:12 +0000[diff] [blame]102 0, 10, BOOKE_PAGESZ_32M, 1),
York Sunb5b06fb2012-12-23 19:25:27 +0000[diff] [blame]103#endif
104#ifdef CONFIG_SYS_NAND_BASE
105 /*
106 * *I*G - NAND
York Sunb5b06fb2012-12-23 19:25:27 +0000[diff] [blame]107 */
108 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
109 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
110 0, 11, BOOKE_PAGESZ_64K, 1),
111#endif
112 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
113 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
114 0, 12, BOOKE_PAGESZ_4K, 1),
115
Liu Gang57966102013-03-07 22:41:02 +0000[diff] [blame]116 /*
117 * *I*G - SRIO
118 * entry 14 and 15 has been used hard coded, they will be disabled
119 * in cpu_init_f, so we use entry 16 for SRIO2.
120 */
121#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
122 /* *I*G* - SRIO1 */
123 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
124 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
125 0, 13, BOOKE_PAGESZ_256M, 1),
126#endif
127#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
128 /* *I*G* - SRIO2 */
129 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
130 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
131 0, 16, BOOKE_PAGESZ_256M, 1),
132#endif
Liu Gang5870fe42013-05-07 16:30:48 +0800[diff] [blame]133#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
134 /*
135 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
136 * fetching ucode and ENV from master
137 */
138 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
139 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
140 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
141 0, 17, BOOKE_PAGESZ_1M, 1),
142#endif
York Sunb5b06fb2012-12-23 19:25:27 +0000[diff] [blame]143};
144
145int num_tlb_entries = ARRAY_SIZE(tlb_table);