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wdenk4a5b6a32001-04-28 17:59:11 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk4a5b6a32001-04-28 17:59:11 +00006 */
7
8/*-----------------------------------------------------------------------
9 * Timer value for timer 2, ICLK = 10
10 *
11 * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
12 * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
13 *
14 * SPEED_FCOUNT2 timer 2 counting frequency
Wolfgang Denk53677ef2008-05-20 16:00:29 +020015 * GCLK CPU clock
wdenk4a5b6a32001-04-28 17:59:11 +000016 * SPEED_TMR2_PS prescaler
17 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020018#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
wdenk4a5b6a32001-04-28 17:59:11 +000019
20/*-----------------------------------------------------------------------
21 * Timer value for PIT
22 *
23 * PIT_TIME = SPEED_PITC / PITRTCLK
24 * PITRTCLK = 8192
25 */
26#define SPEED_PITC (82 << 16) /* start counting from 82 */
27
28/*
29 * The new value for PTA is calculated from
30 *
31 * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
32 *
33 * gclk CPU clock (not bus clock !)
34 * Trefresh Refresh cycle * 4 (four word bursts used)
35 * DFBRG For normal mode (no clock reduction) always 0
36 * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
37 * NCS Number of SDRAM banks (chip selects) on this UPM.
38 */