| Matthias Weisser | 39f0023e | 2011-07-06 00:28:33 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2011 |
| 3 | * Matthias Weisser <weisserm@arcor.de> |
| 4 | * |
| 5 | * (C) Copyright 2009 DENX Software Engineering |
| 6 | * Author: John Rigby <jrigby@gmail.com> |
| 7 | * |
| 8 | * Based on U-Boot and RedBoot sources for several different i.mx |
| 9 | * platforms. |
| 10 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 11 | * SPDX-License-Identifier: GPL-2.0+ |
| Matthias Weisser | 39f0023e | 2011-07-06 00:28:33 +0000 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #include <asm/macro.h> |
| 15 | #include <asm/arch/macro.h> |
| 16 | #include <asm/arch/imx-regs.h> |
| Stefano Babic | a4814a6 | 2011-09-05 04:32:28 +0000 | [diff] [blame] | 17 | #include <generated/asm-offsets.h> |
| Matthias Weisser | 39f0023e | 2011-07-06 00:28:33 +0000 | [diff] [blame] | 18 | |
| 19 | /* |
| 20 | * clocks |
| 21 | */ |
| 22 | .macro init_clocks |
| 23 | |
| 24 | /* disable clock output */ |
| 25 | write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 |
| 26 | write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 |
| 27 | |
| 28 | /* |
| 29 | * enable all implemented clocks in all three |
| 30 | * clock control registers |
| 31 | */ |
| 32 | write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff |
| 33 | write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff |
| 34 | write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff |
| 35 | |
| 36 | /* Devide NAND clock by 32 */ |
| 37 | write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F |
| 38 | .endm |
| 39 | |
| 40 | /* |
| 41 | * sdram controller init |
| 42 | */ |
| 43 | .macro init_lpddr |
| 44 | ldr r0, =IMX_ESDRAMC_BASE |
| 45 | ldr r2, =IMX_SDRAM_BANK0_BASE |
| 46 | |
| 47 | /* |
| 48 | * reset SDRAM controller |
| 49 | * then wait for initialization to complete |
| 50 | */ |
| 51 | ldr r1, =(1 << 1) | (1 << 2) |
| 52 | str r1, [r0, #ESDRAMC_ESDMISC] |
| 53 | 1: ldr r3, [r0, #ESDRAMC_ESDMISC] |
| 54 | tst r3, #(1 << 31) |
| 55 | beq 1b |
| 56 | ldr r1, =(1 << 2) |
| 57 | str r1, [r0, #ESDRAMC_ESDMISC] |
| 58 | |
| 59 | ldr r1, =0x002a7420 |
| 60 | str r1, [r0, #ESDRAMC_ESDCFG0] |
| 61 | |
| 62 | /* control | precharge */ |
| 63 | ldr r1, =0x92216008 |
| 64 | str r1, [r0, #ESDRAMC_ESDCTL0] |
| 65 | /* dram command encoded in address */ |
| 66 | str r1, [r2, #0x400] |
| 67 | |
| 68 | /* auto refresh */ |
| 69 | ldr r1, =0xa2216008 |
| 70 | str r1, [r0, #ESDRAMC_ESDCTL0] |
| 71 | /* read dram twice to auto refresh */ |
| 72 | ldr r3, [r2] |
| 73 | ldr r3, [r2] |
| 74 | |
| 75 | /* control | load mode */ |
| 76 | ldr r1, =0xb2216008 |
| 77 | str r1, [r0, #ESDRAMC_ESDCTL0] |
| 78 | |
| 79 | /* mode register of lpddram */ |
| 80 | strb r1, [r2, #0x33] |
| 81 | |
| 82 | /* extended mode register of lpddrram */ |
| 83 | ldr r2, =0x81000000 |
| 84 | strb r1, [r2] |
| 85 | |
| 86 | /* control | normal */ |
| 87 | ldr r1, =0x82216008 |
| 88 | str r1, [r0, #ESDRAMC_ESDCTL0] |
| 89 | .endm |
| 90 | |
| 91 | .globl lowlevel_init |
| 92 | lowlevel_init: |
| 93 | init_aips |
| 94 | init_max |
| 95 | init_clocks |
| 96 | init_lpddr |
| 97 | mov pc, lr |