wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * MII Utilities |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
| 13 | #include <command.h> |
wdenk | e35745b | 2004-04-18 23:32:11 +0000 | [diff] [blame] | 14 | #include <miiphy.h> |
| 15 | |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 16 | typedef struct _MII_reg_desc_t { |
| 17 | ushort regno; |
| 18 | char * name; |
| 19 | } MII_reg_desc_t; |
| 20 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 21 | static const MII_reg_desc_t reg_0_5_desc_tbl[] = { |
Mike Frysinger | 8ef583a | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 22 | { MII_BMCR, "PHY control register" }, |
| 23 | { MII_BMSR, "PHY status register" }, |
| 24 | { MII_PHYSID1, "PHY ID 1 register" }, |
| 25 | { MII_PHYSID2, "PHY ID 2 register" }, |
| 26 | { MII_ADVERTISE, "Autonegotiation advertisement register" }, |
| 27 | { MII_LPA, "Autonegotiation partner abilities register" }, |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | typedef struct _MII_field_desc_t { |
| 31 | ushort hi; |
| 32 | ushort lo; |
| 33 | ushort mask; |
| 34 | char * name; |
| 35 | } MII_field_desc_t; |
| 36 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 37 | static const MII_field_desc_t reg_0_desc_tbl[] = { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 38 | { 15, 15, 0x01, "reset" }, |
| 39 | { 14, 14, 0x01, "loopback" }, |
| 40 | { 13, 6, 0x81, "speed selection" }, /* special */ |
| 41 | { 12, 12, 0x01, "A/N enable" }, |
| 42 | { 11, 11, 0x01, "power-down" }, |
| 43 | { 10, 10, 0x01, "isolate" }, |
| 44 | { 9, 9, 0x01, "restart A/N" }, |
| 45 | { 8, 8, 0x01, "duplex" }, /* special */ |
| 46 | { 7, 7, 0x01, "collision test enable" }, |
| 47 | { 5, 0, 0x3f, "(reserved)" } |
| 48 | }; |
| 49 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 50 | static const MII_field_desc_t reg_1_desc_tbl[] = { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 51 | { 15, 15, 0x01, "100BASE-T4 able" }, |
| 52 | { 14, 14, 0x01, "100BASE-X full duplex able" }, |
| 53 | { 13, 13, 0x01, "100BASE-X half duplex able" }, |
| 54 | { 12, 12, 0x01, "10 Mbps full duplex able" }, |
| 55 | { 11, 11, 0x01, "10 Mbps half duplex able" }, |
| 56 | { 10, 10, 0x01, "100BASE-T2 full duplex able" }, |
| 57 | { 9, 9, 0x01, "100BASE-T2 half duplex able" }, |
| 58 | { 8, 8, 0x01, "extended status" }, |
| 59 | { 7, 7, 0x01, "(reserved)" }, |
| 60 | { 6, 6, 0x01, "MF preamble suppression" }, |
| 61 | { 5, 5, 0x01, "A/N complete" }, |
| 62 | { 4, 4, 0x01, "remote fault" }, |
| 63 | { 3, 3, 0x01, "A/N able" }, |
| 64 | { 2, 2, 0x01, "link status" }, |
| 65 | { 1, 1, 0x01, "jabber detect" }, |
| 66 | { 0, 0, 0x01, "extended capabilities" }, |
| 67 | }; |
| 68 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 69 | static const MII_field_desc_t reg_2_desc_tbl[] = { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 70 | { 15, 0, 0xffff, "OUI portion" }, |
| 71 | }; |
| 72 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 73 | static const MII_field_desc_t reg_3_desc_tbl[] = { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 74 | { 15, 10, 0x3f, "OUI portion" }, |
| 75 | { 9, 4, 0x3f, "manufacturer part number" }, |
| 76 | { 3, 0, 0x0f, "manufacturer rev. number" }, |
| 77 | }; |
| 78 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 79 | static const MII_field_desc_t reg_4_desc_tbl[] = { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 80 | { 15, 15, 0x01, "next page able" }, |
| 81 | { 14, 14, 0x01, "reserved" }, |
| 82 | { 13, 13, 0x01, "remote fault" }, |
| 83 | { 12, 12, 0x01, "reserved" }, |
| 84 | { 11, 11, 0x01, "asymmetric pause" }, |
| 85 | { 10, 10, 0x01, "pause enable" }, |
| 86 | { 9, 9, 0x01, "100BASE-T4 able" }, |
| 87 | { 8, 8, 0x01, "100BASE-TX full duplex able" }, |
| 88 | { 7, 7, 0x01, "100BASE-TX able" }, |
| 89 | { 6, 6, 0x01, "10BASE-T full duplex able" }, |
| 90 | { 5, 5, 0x01, "10BASE-T able" }, |
| 91 | { 4, 0, 0x1f, "xxx to do" }, |
| 92 | }; |
| 93 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 94 | static const MII_field_desc_t reg_5_desc_tbl[] = { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 95 | { 15, 15, 0x01, "next page able" }, |
| 96 | { 14, 14, 0x01, "acknowledge" }, |
| 97 | { 13, 13, 0x01, "remote fault" }, |
| 98 | { 12, 12, 0x01, "(reserved)" }, |
| 99 | { 11, 11, 0x01, "asymmetric pause able" }, |
| 100 | { 10, 10, 0x01, "pause able" }, |
| 101 | { 9, 9, 0x01, "100BASE-T4 able" }, |
| 102 | { 8, 8, 0x01, "100BASE-X full duplex able" }, |
| 103 | { 7, 7, 0x01, "100BASE-TX able" }, |
| 104 | { 6, 6, 0x01, "10BASE-T full duplex able" }, |
| 105 | { 5, 5, 0x01, "10BASE-T able" }, |
| 106 | { 4, 0, 0x1f, "xxx to do" }, |
| 107 | }; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 108 | typedef struct _MII_field_desc_and_len_t { |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 109 | const MII_field_desc_t *pdesc; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 110 | ushort len; |
| 111 | } MII_field_desc_and_len_t; |
| 112 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 113 | static const MII_field_desc_and_len_t desc_and_len_tbl[] = { |
| 114 | { reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl) }, |
| 115 | { reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl) }, |
| 116 | { reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl) }, |
| 117 | { reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl) }, |
| 118 | { reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl) }, |
| 119 | { reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl) }, |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 120 | }; |
| 121 | |
| 122 | static void dump_reg( |
| 123 | ushort regval, |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 124 | const MII_reg_desc_t *prd, |
| 125 | const MII_field_desc_and_len_t *pdl); |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 126 | |
| 127 | static int special_field( |
| 128 | ushort regno, |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 129 | const MII_field_desc_t *pdesc, |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 130 | ushort regval); |
| 131 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 132 | static void MII_dump_0_to_5( |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 133 | ushort regvals[6], |
| 134 | uchar reglo, |
| 135 | uchar reghi) |
| 136 | { |
| 137 | ulong i; |
| 138 | |
| 139 | for (i = 0; i < 6; i++) { |
| 140 | if ((reglo <= i) && (i <= reghi)) |
| 141 | dump_reg(regvals[i], ®_0_5_desc_tbl[i], |
| 142 | &desc_and_len_tbl[i]); |
| 143 | } |
| 144 | } |
| 145 | |
| 146 | static void dump_reg( |
| 147 | ushort regval, |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 148 | const MII_reg_desc_t *prd, |
| 149 | const MII_field_desc_and_len_t *pdl) |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 150 | { |
| 151 | ulong i; |
| 152 | ushort mask_in_place; |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 153 | const MII_field_desc_t *pdesc; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 154 | |
| 155 | printf("%u. (%04hx) -- %s --\n", |
| 156 | prd->regno, regval, prd->name); |
| 157 | |
| 158 | for (i = 0; i < pdl->len; i++) { |
| 159 | pdesc = &pdl->pdesc[i]; |
| 160 | |
| 161 | mask_in_place = pdesc->mask << pdesc->lo; |
| 162 | |
| 163 | printf(" (%04hx:%04hx) %u.", |
| 164 | mask_in_place, |
| 165 | regval & mask_in_place, |
| 166 | prd->regno); |
| 167 | |
| 168 | if (special_field(prd->regno, pdesc, regval)) { |
| 169 | } |
| 170 | else { |
| 171 | if (pdesc->hi == pdesc->lo) |
| 172 | printf("%2u ", pdesc->lo); |
| 173 | else |
| 174 | printf("%2u-%2u", pdesc->hi, pdesc->lo); |
| 175 | printf(" = %5u %s", |
| 176 | (regval & mask_in_place) >> pdesc->lo, |
| 177 | pdesc->name); |
| 178 | } |
| 179 | printf("\n"); |
| 180 | |
| 181 | } |
| 182 | printf("\n"); |
| 183 | } |
| 184 | |
| 185 | /* Special fields: |
| 186 | ** 0.6,13 |
| 187 | ** 0.8 |
| 188 | ** 2.15-0 |
| 189 | ** 3.15-0 |
| 190 | ** 4.4-0 |
| 191 | ** 5.4-0 |
| 192 | */ |
| 193 | |
| 194 | static int special_field( |
| 195 | ushort regno, |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 196 | const MII_field_desc_t *pdesc, |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 197 | ushort regval) |
| 198 | { |
Mike Frysinger | 8ef583a | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 199 | if ((regno == MII_BMCR) && (pdesc->lo == 6)) { |
| 200 | ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100); |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 201 | printf("%2u,%2u = b%u%u speed selection = %s Mbps", |
| 202 | 6, 13, |
| 203 | (regval >> 6) & 1, |
| 204 | (regval >> 13) & 1, |
Mike Frysinger | 8ef583a | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 205 | speed_bits == BMCR_SPEED1000 ? "1000" : |
| 206 | speed_bits == BMCR_SPEED100 ? "100" : |
| 207 | "10"); |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 208 | return 1; |
| 209 | } |
| 210 | |
Mike Frysinger | 8ef583a | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 211 | else if ((regno == MII_BMCR) && (pdesc->lo == 8)) { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 212 | printf("%2u = %5u duplex = %s", |
| 213 | pdesc->lo, |
| 214 | (regval >> pdesc->lo) & 1, |
| 215 | ((regval >> pdesc->lo) & 1) ? "full" : "half"); |
| 216 | return 1; |
| 217 | } |
| 218 | |
Mike Frysinger | 8ef583a | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 219 | else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 220 | ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; |
| 221 | printf("%2u-%2u = %5u selector = %s", |
| 222 | pdesc->hi, pdesc->lo, sel_bits, |
wdenk | b9711de | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 223 | sel_bits == PHY_ANLPAR_PSB_802_3 ? |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 224 | "IEEE 802.3" : |
wdenk | b9711de | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 225 | sel_bits == PHY_ANLPAR_PSB_802_9 ? |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 226 | "IEEE 802.9 ISLAN-16T" : |
| 227 | "???"); |
| 228 | return 1; |
| 229 | } |
| 230 | |
Mike Frysinger | 8ef583a | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 231 | else if ((regno == MII_LPA) && (pdesc->lo == 0)) { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 232 | ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; |
| 233 | printf("%2u-%2u = %u selector = %s", |
| 234 | pdesc->hi, pdesc->lo, sel_bits, |
wdenk | b9711de | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 235 | sel_bits == PHY_ANLPAR_PSB_802_3 ? |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 236 | "IEEE 802.3" : |
wdenk | b9711de | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 237 | sel_bits == PHY_ANLPAR_PSB_802_9 ? |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 238 | "IEEE 802.9 ISLAN-16T" : |
| 239 | "???"); |
| 240 | return 1; |
| 241 | } |
| 242 | |
| 243 | return 0; |
| 244 | } |
| 245 | |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 246 | static char last_op[2]; |
| 247 | static uint last_data; |
| 248 | static uint last_addr_lo; |
| 249 | static uint last_addr_hi; |
| 250 | static uint last_reg_lo; |
| 251 | static uint last_reg_hi; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 252 | |
| 253 | static void extract_range( |
| 254 | char * input, |
| 255 | unsigned char * plo, |
| 256 | unsigned char * phi) |
| 257 | { |
| 258 | char * end; |
| 259 | *plo = simple_strtoul(input, &end, 16); |
| 260 | if (*end == '-') { |
| 261 | end++; |
| 262 | *phi = simple_strtoul(end, NULL, 16); |
| 263 | } |
| 264 | else { |
| 265 | *phi = *plo; |
| 266 | } |
| 267 | } |
| 268 | |
wdenk | 5cf91d6 | 2004-04-23 20:32:05 +0000 | [diff] [blame] | 269 | /* ---------------------------------------------------------------- */ |
Mike Frysinger | 3a5ee0b | 2010-10-20 01:06:48 -0400 | [diff] [blame] | 270 | static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 271 | { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 272 | char op[2]; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 273 | unsigned char addrlo, addrhi, reglo, reghi; |
Wolfgang Denk | 2b792af | 2005-09-24 21:54:50 +0200 | [diff] [blame] | 274 | unsigned char addr, reg; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 275 | unsigned short data; |
| 276 | int rcode = 0; |
Mike Frysinger | 5700bb6 | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 277 | const char *devname; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 278 | |
Wolfgang Denk | 47e26b1 | 2010-07-17 01:06:04 +0200 | [diff] [blame] | 279 | if (argc < 2) |
Simon Glass | 4c12eeb | 2011-12-10 08:44:01 +0000 | [diff] [blame] | 280 | return CMD_RET_USAGE; |
Shinya Kuribayashi | b9173af | 2007-12-27 15:39:54 +0900 | [diff] [blame] | 281 | |
TsiChung Liew | 0f3ba7e | 2008-03-30 01:22:13 -0500 | [diff] [blame] | 282 | #if defined(CONFIG_MII_INIT) |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 283 | mii_init (); |
| 284 | #endif |
| 285 | |
| 286 | /* |
| 287 | * We use the last specified parameters, unless new ones are |
| 288 | * entered. |
| 289 | */ |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 290 | op[0] = last_op[0]; |
| 291 | op[1] = last_op[1]; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 292 | addrlo = last_addr_lo; |
| 293 | addrhi = last_addr_hi; |
| 294 | reglo = last_reg_lo; |
| 295 | reghi = last_reg_hi; |
| 296 | data = last_data; |
| 297 | |
| 298 | if ((flag & CMD_FLAG_REPEAT) == 0) { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 299 | op[0] = argv[1][0]; |
| 300 | if (strlen(argv[1]) > 1) |
| 301 | op[1] = argv[1][1]; |
| 302 | else |
| 303 | op[1] = '\0'; |
| 304 | |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 305 | if (argc >= 3) |
| 306 | extract_range(argv[2], &addrlo, &addrhi); |
| 307 | if (argc >= 4) |
| 308 | extract_range(argv[3], ®lo, ®hi); |
| 309 | if (argc >= 5) |
| 310 | data = simple_strtoul (argv[4], NULL, 16); |
| 311 | } |
| 312 | |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 313 | /* use current device */ |
| 314 | devname = miiphy_get_current_dev(); |
| 315 | |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 316 | /* |
| 317 | * check info/read/write. |
| 318 | */ |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 319 | if (op[0] == 'i') { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 320 | unsigned char j, start, end; |
| 321 | unsigned int oui; |
| 322 | unsigned char model; |
| 323 | unsigned char rev; |
| 324 | |
| 325 | /* |
| 326 | * Look for any and all PHYs. Valid addresses are 0..31. |
| 327 | */ |
| 328 | if (argc >= 3) { |
Wolfgang Denk | 2b792af | 2005-09-24 21:54:50 +0200 | [diff] [blame] | 329 | start = addrlo; end = addrhi; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 330 | } else { |
Wolfgang Denk | 2b792af | 2005-09-24 21:54:50 +0200 | [diff] [blame] | 331 | start = 0; end = 31; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 332 | } |
| 333 | |
Wolfgang Denk | 2b792af | 2005-09-24 21:54:50 +0200 | [diff] [blame] | 334 | for (j = start; j <= end; j++) { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 335 | if (miiphy_info (devname, j, &oui, &model, &rev) == 0) { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 336 | printf("PHY 0x%02X: " |
| 337 | "OUI = 0x%04X, " |
| 338 | "Model = 0x%02X, " |
| 339 | "Rev = 0x%02X, " |
Larry Johnson | 71bc6e6 | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 340 | "%3dbase%s, %s\n", |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 341 | j, oui, model, rev, |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 342 | miiphy_speed (devname, j), |
Larry Johnson | 71bc6e6 | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 343 | miiphy_is_1000base_x (devname, j) |
| 344 | ? "X" : "T", |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 345 | (miiphy_duplex (devname, j) == FULL) |
| 346 | ? "FDX" : "HDX"); |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 347 | } |
| 348 | } |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 349 | } else if (op[0] == 'r') { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 350 | for (addr = addrlo; addr <= addrhi; addr++) { |
| 351 | for (reg = reglo; reg <= reghi; reg++) { |
| 352 | data = 0xffff; |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 353 | if (miiphy_read (devname, addr, reg, &data) != 0) { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 354 | printf( |
| 355 | "Error reading from the PHY addr=%02x reg=%02x\n", |
| 356 | addr, reg); |
| 357 | rcode = 1; |
Wolfgang Denk | 2b792af | 2005-09-24 21:54:50 +0200 | [diff] [blame] | 358 | } else { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 359 | if ((addrlo != addrhi) || (reglo != reghi)) |
| 360 | printf("addr=%02x reg=%02x data=", |
| 361 | (uint)addr, (uint)reg); |
| 362 | printf("%04X\n", data & 0x0000FFFF); |
| 363 | } |
| 364 | } |
| 365 | if ((addrlo != addrhi) && (reglo != reghi)) |
| 366 | printf("\n"); |
| 367 | } |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 368 | } else if (op[0] == 'w') { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 369 | for (addr = addrlo; addr <= addrhi; addr++) { |
| 370 | for (reg = reglo; reg <= reghi; reg++) { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 371 | if (miiphy_write (devname, addr, reg, data) != 0) { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 372 | printf("Error writing to the PHY addr=%02x reg=%02x\n", |
| 373 | addr, reg); |
| 374 | rcode = 1; |
| 375 | } |
| 376 | } |
| 377 | } |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 378 | } else if (strncmp(op, "du", 2) == 0) { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 379 | ushort regs[6]; |
| 380 | int ok = 1; |
| 381 | if ((reglo > 5) || (reghi > 5)) { |
| 382 | printf( |
| 383 | "The MII dump command only formats the " |
| 384 | "standard MII registers, 0-5.\n"); |
| 385 | return 1; |
| 386 | } |
| 387 | for (addr = addrlo; addr <= addrhi; addr++) { |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 388 | for (reg = reglo; reg < reghi + 1; reg++) { |
| 389 | if (miiphy_read(devname, addr, reg, ®s[reg]) != 0) { |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 390 | ok = 0; |
| 391 | printf( |
| 392 | "Error reading from the PHY addr=%02x reg=%02x\n", |
| 393 | addr, reg); |
| 394 | rcode = 1; |
| 395 | } |
| 396 | } |
| 397 | if (ok) |
| 398 | MII_dump_0_to_5(regs, reglo, reghi); |
| 399 | printf("\n"); |
| 400 | } |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 401 | } else if (strncmp(op, "de", 2) == 0) { |
| 402 | if (argc == 2) |
| 403 | miiphy_listdev (); |
| 404 | else |
| 405 | miiphy_set_current_dev (argv[2]); |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 406 | } else { |
Simon Glass | 4c12eeb | 2011-12-10 08:44:01 +0000 | [diff] [blame] | 407 | return CMD_RET_USAGE; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | /* |
| 411 | * Save the parameters for repeats. |
| 412 | */ |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 413 | last_op[0] = op[0]; |
| 414 | last_op[1] = op[1]; |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 415 | last_addr_lo = addrlo; |
| 416 | last_addr_hi = addrhi; |
| 417 | last_reg_lo = reglo; |
| 418 | last_reg_hi = reghi; |
| 419 | last_data = data; |
| 420 | |
| 421 | return rcode; |
| 422 | } |
| 423 | |
| 424 | /***************************************************/ |
| 425 | |
| 426 | U_BOOT_CMD( |
| 427 | mii, 5, 1, do_mii, |
Peter Tyser | 2fb2604 | 2009-01-27 18:03:12 -0600 | [diff] [blame] | 428 | "MII utility commands", |
Marian Balakowicz | 63ff004 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 429 | "device - list available devices\n" |
| 430 | "mii device <devname> - set current device\n" |
| 431 | "mii info <addr> - display MII PHY info\n" |
| 432 | "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n" |
| 433 | "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n" |
| 434 | "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n" |
Wolfgang Denk | a89c33d | 2009-05-24 17:06:54 +0200 | [diff] [blame] | 435 | "Addr and/or reg may be ranges, e.g. 2-7." |
wdenk | 2471111 | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 436 | ); |