blob: 422c2c691ed31216ae60c2e2b0768bc251ce464a [file] [log] [blame]
Kumar Galac916d7c2011-04-13 08:37:44 -05001/*
Roy Zang111fd192012-10-08 07:44:21 +00002 * Copyright 2009-2012 Freescale Semiconductor, Inc.
Kumar Galac916d7c2011-04-13 08:37:44 -05003 * Dave Liu <daveliu@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Kumar Galac916d7c2011-04-13 08:37:44 -05006 */
7#include <common.h>
8#include <asm/io.h>
9#include <malloc.h>
10#include <net.h>
11#include <hwconfig.h>
12#include <fm_eth.h>
13#include <fsl_mdio.h>
14#include <miiphy.h>
15#include <phy.h>
16#include <asm/fsl_dtsec.h>
17#include <asm/fsl_tgec.h>
Roy Zang111fd192012-10-08 07:44:21 +000018#include <asm/fsl_memac.h>
Kumar Galac916d7c2011-04-13 08:37:44 -050019
20#include "fm.h"
21
22static struct eth_device *devlist[NUM_FM_PORTS];
23static int num_controllers;
24
25#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
26
27#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
28 TBIANA_FULL_DUPLEX)
29
30#define TBIANA_SGMII_ACK 0x4001
31
32#define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
33 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
34
35/* Configure the TBI for SGMII operation */
Kim Phillips960d70c2012-10-29 13:34:34 +000036static void dtsec_configure_serdes(struct fm_eth *priv)
Kumar Galac916d7c2011-04-13 08:37:44 -050037{
Roy Zang111fd192012-10-08 07:44:21 +000038#ifdef CONFIG_SYS_FMAN_V3
39 u32 value;
40 struct mii_dev bus;
41 bus.priv = priv->mac->phyregs;
42
43 /* SGMII IF mode + AN enable */
44 value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII;
45 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
46
47 /* Dev ability according to SGMII specification */
48 value = PHY_SGMII_DEV_ABILITY_SGMII;
49 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
50
51 /* Adjust link timer for SGMII -
52 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
53 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
54 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
55
56 /* Restart AN */
57 value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
58 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
59#else
Kumar Galac916d7c2011-04-13 08:37:44 -050060 struct dtsec *regs = priv->mac->base;
61 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
62
63 /*
64 * Access TBI PHY registers at given TSEC register offset as
65 * opposed to the register offset used for external PHY accesses
66 */
67 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
68 TBICON_CLK_SELECT);
69 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
70 TBIANA_SGMII_ACK);
71 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
72 TBI_CR, TBICR_SETTINGS);
Roy Zang111fd192012-10-08 07:44:21 +000073#endif
Kumar Galac916d7c2011-04-13 08:37:44 -050074}
75
76static void dtsec_init_phy(struct eth_device *dev)
77{
78 struct fm_eth *fm_eth = dev->priv;
Roy Zang111fd192012-10-08 07:44:21 +000079#ifndef CONFIG_SYS_FMAN_V3
shaohui xie1f3bd3e2012-10-11 20:25:36 +000080 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
81
Kumar Galac916d7c2011-04-13 08:37:44 -050082 /* Assign a Physical address to the TBI */
83 out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
Roy Zang111fd192012-10-08 07:44:21 +000084#endif
Kumar Galac916d7c2011-04-13 08:37:44 -050085
86 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
87 dtsec_configure_serdes(fm_eth);
88}
89
90static int tgec_is_fibre(struct eth_device *dev)
91{
92 struct fm_eth *fm = dev->priv;
93 char phyopt[20];
94
95 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
96
97 return hwconfig_arg_cmp(phyopt, "xfi");
98}
99#endif
100
101static u16 muram_readw(u16 *addr)
102{
103 u32 base = (u32)addr & ~0x3;
104 u32 val32 = *(u32 *)base;
105 int byte_pos;
106 u16 ret;
107
108 byte_pos = (u32)addr & 0x3;
109 if (byte_pos)
110 ret = (u16)(val32 & 0x0000ffff);
111 else
112 ret = (u16)((val32 & 0xffff0000) >> 16);
113
114 return ret;
115}
116
117static void muram_writew(u16 *addr, u16 val)
118{
119 u32 base = (u32)addr & ~0x3;
120 u32 org32 = *(u32 *)base;
121 u32 val32;
122 int byte_pos;
123
124 byte_pos = (u32)addr & 0x3;
125 if (byte_pos)
126 val32 = (org32 & 0xffff0000) | val;
127 else
128 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
129
130 *(u32 *)base = val32;
131}
132
133static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
134{
135 int timeout = 1000000;
136
137 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
138
139 /* wait until the rx port is not busy */
140 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
141 ;
142}
143
144static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
145{
146 /* set BMI to independent mode, Rx port disable */
147 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
148 /* clear FOF in IM case */
149 out_be32(&rx_port->fmbm_rim, 0);
150 /* Rx frame next engine -RISC */
151 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
152 /* Rx command attribute - no order, MR[3] = 1 */
153 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
154 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
155 /* enable Rx statistic counters */
156 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
157 /* disable Rx performance counters */
158 out_be32(&rx_port->fmbm_rpc, 0);
159}
160
161static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
162{
163 int timeout = 1000000;
164
165 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
166
167 /* wait until the tx port is not busy */
168 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
169 ;
170}
171
172static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
173{
174 /* set BMI to independent mode, Tx port disable */
175 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
176 /* Tx frame next engine -RISC */
177 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
178 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
179 /* Tx command attribute - no order, MR[3] = 1 */
180 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
181 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
182 /* enable Tx statistic counters */
183 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
184 /* disable Tx performance counters */
185 out_be32(&tx_port->fmbm_tpc, 0);
186}
187
188static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
189{
190 struct fm_port_global_pram *pram;
191 u32 pram_page_offset;
192 void *rx_bd_ring_base;
193 void *rx_buf_pool;
194 struct fm_port_bd *rxbd;
195 struct fm_port_qd *rxqd;
196 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
197 int i;
198
199 /* alloc global parameter ram at MURAM */
200 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
201 FM_PRAM_SIZE, FM_PRAM_ALIGN);
202 fm_eth->rx_pram = pram;
203
204 /* parameter page offset to MURAM */
205 pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
206
207 /* enable global mode- snooping data buffers and BDs */
208 pram->mode = PRAM_MODE_GLOBAL;
209
210 /* init the Rx queue descriptor pionter */
211 pram->rxqd_ptr = pram_page_offset + 0x20;
212
213 /* set the max receive buffer length, power of 2 */
214 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
215
216 /* alloc Rx buffer descriptors from main memory */
217 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
218 * RX_BD_RING_SIZE);
219 if (!rx_bd_ring_base)
220 return 0;
221 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
222 * RX_BD_RING_SIZE);
223
224 /* alloc Rx buffer from main memory */
225 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
226 if (!rx_buf_pool)
227 return 0;
228 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
229
230 /* save them to fm_eth */
231 fm_eth->rx_bd_ring = rx_bd_ring_base;
232 fm_eth->cur_rxbd = rx_bd_ring_base;
233 fm_eth->rx_buf = rx_buf_pool;
234
235 /* init Rx BDs ring */
236 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
237 for (i = 0; i < RX_BD_RING_SIZE; i++) {
238 rxbd->status = RxBD_EMPTY;
239 rxbd->len = 0;
240 rxbd->buf_ptr_hi = 0;
241 rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
242 rxbd++;
243 }
244
245 /* set the Rx queue descriptor */
246 rxqd = &pram->rxqd;
247 muram_writew(&rxqd->gen, 0);
248 muram_writew(&rxqd->bd_ring_base_hi, 0);
249 rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
250 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
251 * RX_BD_RING_SIZE);
252 muram_writew(&rxqd->offset_in, 0);
253 muram_writew(&rxqd->offset_out, 0);
254
255 /* set IM parameter ram pointer to Rx Frame Queue ID */
256 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
257
258 return 1;
259}
260
261static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
262{
263 struct fm_port_global_pram *pram;
264 u32 pram_page_offset;
265 void *tx_bd_ring_base;
266 struct fm_port_bd *txbd;
267 struct fm_port_qd *txqd;
268 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
269 int i;
270
271 /* alloc global parameter ram at MURAM */
272 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
273 FM_PRAM_SIZE, FM_PRAM_ALIGN);
274 fm_eth->tx_pram = pram;
275
276 /* parameter page offset to MURAM */
277 pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
278
279 /* enable global mode- snooping data buffers and BDs */
280 pram->mode = PRAM_MODE_GLOBAL;
281
282 /* init the Tx queue descriptor pionter */
283 pram->txqd_ptr = pram_page_offset + 0x40;
284
285 /* alloc Tx buffer descriptors from main memory */
286 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
287 * TX_BD_RING_SIZE);
288 if (!tx_bd_ring_base)
289 return 0;
290 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
291 * TX_BD_RING_SIZE);
292 /* save it to fm_eth */
293 fm_eth->tx_bd_ring = tx_bd_ring_base;
294 fm_eth->cur_txbd = tx_bd_ring_base;
295
296 /* init Tx BDs ring */
297 txbd = (struct fm_port_bd *)tx_bd_ring_base;
298 for (i = 0; i < TX_BD_RING_SIZE; i++) {
299 txbd->status = TxBD_LAST;
300 txbd->len = 0;
301 txbd->buf_ptr_hi = 0;
302 txbd->buf_ptr_lo = 0;
303 }
304
305 /* set the Tx queue decriptor */
306 txqd = &pram->txqd;
307 muram_writew(&txqd->bd_ring_base_hi, 0);
308 txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
309 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
310 * TX_BD_RING_SIZE);
311 muram_writew(&txqd->offset_in, 0);
312 muram_writew(&txqd->offset_out, 0);
313
314 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
315 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
316
317 return 1;
318}
319
320static int fm_eth_init(struct fm_eth *fm_eth)
321{
322
323 if (!fm_eth_rx_port_parameter_init(fm_eth))
324 return 0;
325
326 if (!fm_eth_tx_port_parameter_init(fm_eth))
327 return 0;
328
329 return 1;
330}
331
332static int fm_eth_startup(struct fm_eth *fm_eth)
333{
334 struct fsl_enet_mac *mac;
335 mac = fm_eth->mac;
336
337 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
338 if (!fm_eth_init(fm_eth))
339 return 0;
340 /* setup the MAC controller */
341 mac->init_mac(mac);
342
343 /* For some reason we need to set SPEED_100 */
344 if ((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) && mac->set_if_mode)
345 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
346
347 /* init bmi rx port, IM mode and disable */
348 bmi_rx_port_init(fm_eth->rx_port);
349 /* init bmi tx port, IM mode and disable */
350 bmi_tx_port_init(fm_eth->tx_port);
351
352 return 1;
353}
354
355static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
356{
357 struct fm_port_global_pram *pram;
358
359 pram = fm_eth->tx_pram;
360 /* graceful stop transmission of frames */
361 pram->mode |= PRAM_MODE_GRACEFUL_STOP;
362 sync();
363}
364
365static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
366{
367 struct fm_port_global_pram *pram;
368
369 pram = fm_eth->tx_pram;
370 /* re-enable transmission of frames */
371 pram->mode &= ~PRAM_MODE_GRACEFUL_STOP;
372 sync();
373}
374
375static int fm_eth_open(struct eth_device *dev, bd_t *bd)
376{
377 struct fm_eth *fm_eth;
378 struct fsl_enet_mac *mac;
Timur Tabi11af8d62012-07-09 08:52:43 +0000379#ifdef CONFIG_PHYLIB
380 int ret;
381#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500382
383 fm_eth = (struct fm_eth *)dev->priv;
384 mac = fm_eth->mac;
385
386 /* setup the MAC address */
387 if (dev->enetaddr[0] & 0x01) {
388 printf("%s: MacAddress is multcast address\n", __func__);
389 return 1;
390 }
391 mac->set_mac_addr(mac, dev->enetaddr);
392
393 /* enable bmi Rx port */
394 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
395 /* enable MAC rx/tx port */
396 mac->enable_mac(mac);
397 /* enable bmi Tx port */
398 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
399 /* re-enable transmission of frame */
400 fmc_tx_port_graceful_stop_disable(fm_eth);
401
402#ifdef CONFIG_PHYLIB
Timur Tabi11af8d62012-07-09 08:52:43 +0000403 ret = phy_startup(fm_eth->phydev);
404 if (ret) {
405 printf("%s: Could not initialize\n", fm_eth->phydev->dev->name);
406 return ret;
407 }
Kumar Galac916d7c2011-04-13 08:37:44 -0500408#else
409 fm_eth->phydev->speed = SPEED_1000;
410 fm_eth->phydev->link = 1;
411 fm_eth->phydev->duplex = DUPLEX_FULL;
412#endif
413
414 /* set the MAC-PHY mode */
415 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
416
417 if (!fm_eth->phydev->link)
418 printf("%s: No link.\n", fm_eth->phydev->dev->name);
419
420 return fm_eth->phydev->link ? 0 : -1;
421}
422
423static void fm_eth_halt(struct eth_device *dev)
424{
425 struct fm_eth *fm_eth;
426 struct fsl_enet_mac *mac;
427
428 fm_eth = (struct fm_eth *)dev->priv;
429 mac = fm_eth->mac;
430
431 /* graceful stop the transmission of frames */
432 fmc_tx_port_graceful_stop_enable(fm_eth);
433 /* disable bmi Tx port */
434 bmi_tx_port_disable(fm_eth->tx_port);
435 /* disable MAC rx/tx port */
436 mac->disable_mac(mac);
437 /* disable bmi Rx port */
438 bmi_rx_port_disable(fm_eth->rx_port);
439
440 phy_shutdown(fm_eth->phydev);
441}
442
Joe Hershbergere9df2012012-05-22 07:56:15 +0000443static int fm_eth_send(struct eth_device *dev, void *buf, int len)
Kumar Galac916d7c2011-04-13 08:37:44 -0500444{
445 struct fm_eth *fm_eth;
446 struct fm_port_global_pram *pram;
447 struct fm_port_bd *txbd, *txbd_base;
448 u16 offset_in;
449 int i;
450
451 fm_eth = (struct fm_eth *)dev->priv;
452 pram = fm_eth->tx_pram;
453 txbd = fm_eth->cur_txbd;
454
455 /* find one empty TxBD */
456 for (i = 0; txbd->status & TxBD_READY; i++) {
457 udelay(100);
458 if (i > 0x1000) {
459 printf("%s: Tx buffer not ready\n", dev->name);
460 return 0;
461 }
462 }
463 /* setup TxBD */
464 txbd->buf_ptr_hi = 0;
465 txbd->buf_ptr_lo = (u32)buf;
466 txbd->len = len;
467 sync();
468 txbd->status = TxBD_READY | TxBD_LAST;
469 sync();
470
471 /* update TxQD, let RISC to send the packet */
472 offset_in = muram_readw(&pram->txqd.offset_in);
473 offset_in += sizeof(struct fm_port_bd);
474 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
475 offset_in = 0;
476 muram_writew(&pram->txqd.offset_in, offset_in);
477 sync();
478
479 /* wait for buffer to be transmitted */
480 for (i = 0; txbd->status & TxBD_READY; i++) {
481 udelay(100);
482 if (i > 0x10000) {
483 printf("%s: Tx error\n", dev->name);
484 return 0;
485 }
486 }
487
488 /* advance the TxBD */
489 txbd++;
490 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
491 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
492 txbd = txbd_base;
493 /* update current txbd */
494 fm_eth->cur_txbd = (void *)txbd;
495
496 return 1;
497}
498
499static int fm_eth_recv(struct eth_device *dev)
500{
501 struct fm_eth *fm_eth;
502 struct fm_port_global_pram *pram;
503 struct fm_port_bd *rxbd, *rxbd_base;
504 u16 status, len;
505 u8 *data;
506 u16 offset_out;
507
508 fm_eth = (struct fm_eth *)dev->priv;
509 pram = fm_eth->rx_pram;
510 rxbd = fm_eth->cur_rxbd;
511 status = rxbd->status;
512
513 while (!(status & RxBD_EMPTY)) {
514 if (!(status & RxBD_ERROR)) {
515 data = (u8 *)rxbd->buf_ptr_lo;
516 len = rxbd->len;
517 NetReceive(data, len);
518 } else {
519 printf("%s: Rx error\n", dev->name);
520 return 0;
521 }
522
523 /* clear the RxBDs */
524 rxbd->status = RxBD_EMPTY;
525 rxbd->len = 0;
526 sync();
527
528 /* advance RxBD */
529 rxbd++;
530 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
531 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
532 rxbd = rxbd_base;
533 /* read next status */
534 status = rxbd->status;
535
536 /* update RxQD */
537 offset_out = muram_readw(&pram->rxqd.offset_out);
538 offset_out += sizeof(struct fm_port_bd);
539 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
540 offset_out = 0;
541 muram_writew(&pram->rxqd.offset_out, offset_out);
542 sync();
543 }
544 fm_eth->cur_rxbd = (void *)rxbd;
545
546 return 1;
547}
548
549static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
550{
551 struct fsl_enet_mac *mac;
552 int num;
553 void *base, *phyregs = NULL;
554
555 num = fm_eth->num;
556
Roy Zang111fd192012-10-08 07:44:21 +0000557#ifdef CONFIG_SYS_FMAN_V3
Shaohui Xie944b6cc2013-03-25 07:33:17 +0000558 if (fm_eth->type == FM_ETH_10G_E)
559 num += 8;
Roy Zang111fd192012-10-08 07:44:21 +0000560 base = &reg->memac[num].fm_memac;
561 phyregs = &reg->memac[num].fm_memac_mdio;
562#else
Kumar Galac916d7c2011-04-13 08:37:44 -0500563 /* Get the mac registers base address */
564 if (fm_eth->type == FM_ETH_1G_E) {
565 base = &reg->mac_1g[num].fm_dtesc;
Timur Tabi30381712011-10-04 16:44:43 -0500566 phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
Kumar Galac916d7c2011-04-13 08:37:44 -0500567 } else {
568 base = &reg->mac_10g[num].fm_10gec;
569 phyregs = &reg->mac_10g[num].fm_10gec_mdio;
570 }
Roy Zang111fd192012-10-08 07:44:21 +0000571#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500572
573 /* alloc mac controller */
574 mac = malloc(sizeof(struct fsl_enet_mac));
575 if (!mac)
576 return 0;
577 memset(mac, 0, sizeof(struct fsl_enet_mac));
578
579 /* save the mac to fm_eth struct */
580 fm_eth->mac = mac;
581
Roy Zang111fd192012-10-08 07:44:21 +0000582#ifdef CONFIG_SYS_FMAN_V3
583 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
584#else
Kumar Galac916d7c2011-04-13 08:37:44 -0500585 if (fm_eth->type == FM_ETH_1G_E)
Timur Tabi30381712011-10-04 16:44:43 -0500586 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
Kumar Galac916d7c2011-04-13 08:37:44 -0500587 else
588 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
Roy Zang111fd192012-10-08 07:44:21 +0000589#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500590
591 return 1;
592}
593
594static int init_phy(struct eth_device *dev)
595{
596 struct fm_eth *fm_eth = dev->priv;
597 struct phy_device *phydev = NULL;
598 u32 supported;
599
600#ifdef CONFIG_PHYLIB
601 if (fm_eth->type == FM_ETH_1G_E)
602 dtsec_init_phy(dev);
603
604 if (fm_eth->bus) {
605 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
606 fm_eth->enet_if);
607 }
608
609 if (!phydev) {
610 printf("Failed to connect\n");
611 return -1;
612 }
613
614 if (fm_eth->type == FM_ETH_1G_E) {
615 supported = (SUPPORTED_10baseT_Half |
616 SUPPORTED_10baseT_Full |
617 SUPPORTED_100baseT_Half |
618 SUPPORTED_100baseT_Full |
619 SUPPORTED_1000baseT_Full);
620 } else {
621 supported = SUPPORTED_10000baseT_Full;
622
623 if (tgec_is_fibre(dev))
624 phydev->port = PORT_FIBRE;
625 }
626
627 phydev->supported &= supported;
628 phydev->advertising = phydev->supported;
629
630 fm_eth->phydev = phydev;
631
632 phy_config(phydev);
633#endif
634
635 return 0;
636}
637
638int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
639{
640 struct eth_device *dev;
641 struct fm_eth *fm_eth;
642 int i, num = info->num;
643
644 /* alloc eth device */
645 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
646 if (!dev)
647 return 0;
648 memset(dev, 0, sizeof(struct eth_device));
649
650 /* alloc the FMan ethernet private struct */
651 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
652 if (!fm_eth)
653 return 0;
654 memset(fm_eth, 0, sizeof(struct fm_eth));
655
656 /* save off some things we need from the info struct */
657 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
658 fm_eth->num = num;
659 fm_eth->type = info->type;
660
661 fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
662 fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
663
664 /* set the ethernet max receive length */
665 fm_eth->max_rx_len = MAX_RXBUF_LEN;
666
667 /* init global mac structure */
668 if (!fm_eth_init_mac(fm_eth, reg))
669 return 0;
670
671 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
672 if (fm_eth->type == FM_ETH_1G_E)
673 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
674 else
675 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
676
677 devlist[num_controllers++] = dev;
678 dev->iobase = 0;
679 dev->priv = (void *)fm_eth;
680 dev->init = fm_eth_open;
681 dev->halt = fm_eth_halt;
682 dev->send = fm_eth_send;
683 dev->recv = fm_eth_recv;
684 fm_eth->dev = dev;
685 fm_eth->bus = info->bus;
686 fm_eth->phyaddr = info->phy_addr;
687 fm_eth->enet_if = info->enet_if;
688
689 /* startup the FM im */
690 if (!fm_eth_startup(fm_eth))
691 return 0;
692
693 if (init_phy(dev))
694 return 0;
695
696 /* clear the ethernet address */
697 for (i = 0; i < 6; i++)
698 dev->enetaddr[i] = 0;
699 eth_register(dev);
700
701 return 1;
702}