blob: 407354fc4cdf2acac18fee8d014e4d92f63078f3 [file] [log] [blame]
TsiChung Liew8e585f02007-06-18 13:50:13 -05001/*
TsiChungLiew2bd806f2007-07-05 23:17:36 -05002 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
TsiChung Liew8e585f02007-06-18 13:50:13 -05003 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liew8e585f02007-06-18 13:50:13 -05006 */
7
8/*
9 * Minimal serial functions needed to use one of the uart ports
10 * as serial console interface.
11 */
12
13#include <common.h>
Alison Wang39c7a262012-10-18 16:54:38 +000014#include <serial.h>
15#include <linux/compiler.h>
Wolfgang Denk3e66c072007-08-19 10:27:34 +020016
TsiChungLiew2bd806f2007-07-05 23:17:36 -050017#include <asm/immap.h>
18#include <asm/uart.h>
TsiChung Liew8e585f02007-06-18 13:50:13 -050019
20DECLARE_GLOBAL_DATA_PTR;
21
TsiChung Liewfa9da592010-03-09 19:24:43 -060022extern void uart_port_conf(int port);
TsiChungLiew8d1d66a2007-08-05 03:55:21 -050023
Marek Vasutabaef692012-09-13 16:51:38 +020024static int mcf_serial_init(void)
TsiChung Liew8e585f02007-06-18 13:50:13 -050025{
26 volatile uart_t *uart;
27 u32 counter;
28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029 uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050030
TsiChung Liewfa9da592010-03-09 19:24:43 -060031 uart_port_conf(CONFIG_SYS_UART_PORT);
TsiChungLiew8d1d66a2007-08-05 03:55:21 -050032
TsiChung Liew8e585f02007-06-18 13:50:13 -050033 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
34 uart->ucr = UART_UCR_RESET_RX;
35 uart->ucr = UART_UCR_RESET_TX;
36 uart->ucr = UART_UCR_RESET_ERROR;
37 uart->ucr = UART_UCR_RESET_MR;
38 __asm__("nop");
39
40 uart->uimr = 0;
41
42 /* write to CSR: RX/TX baud rate from timers */
43 uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
44
45 uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
46 uart->umr = UART_UMR_SB_STOP_BITS_1;
47
48 /* Setting up BaudRate */
TsiChung Liew81cc3232008-05-29 12:21:54 -050049 counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
50 counter = counter / gd->baudrate;
TsiChung Liew8e585f02007-06-18 13:50:13 -050051
52 /* write to CTUR: divide counter upper byte */
53 uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
54 /* write to CTLR: divide counter lower byte */
55 uart->ubg2 = (u8) (counter & 0x00ff);
56
57 uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
58
59 return (0);
60}
61
Marek Vasutabaef692012-09-13 16:51:38 +020062static void mcf_serial_putc(const char c)
TsiChung Liew8e585f02007-06-18 13:50:13 -050063{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064 volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050065
66 if (c == '\n')
67 serial_putc('\r');
68
69 /* Wait for last character to go. */
70 while (!(uart->usr & UART_USR_TXRDY)) ;
71
72 uart->utb = c;
73}
74
Marek Vasutabaef692012-09-13 16:51:38 +020075static int mcf_serial_getc(void)
TsiChung Liew8e585f02007-06-18 13:50:13 -050076{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050078
79 /* Wait for a character to arrive. */
80 while (!(uart->usr & UART_USR_RXRDY)) ;
81 return uart->urb;
82}
83
Marek Vasutabaef692012-09-13 16:51:38 +020084static int mcf_serial_tstc(void)
TsiChung Liew8e585f02007-06-18 13:50:13 -050085{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050087
88 return (uart->usr & UART_USR_RXRDY);
89}
90
Marek Vasutabaef692012-09-13 16:51:38 +020091static void mcf_serial_setbrg(void)
TsiChung Liew8e585f02007-06-18 13:50:13 -050092{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050094 u32 counter;
95
Richard Retanubun92d3e6e2009-01-23 11:44:30 -050096 /* Setting up BaudRate */
97 counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
98 counter = counter / gd->baudrate;
TsiChung Liew8e585f02007-06-18 13:50:13 -050099
100 /* write to CTUR: divide counter upper byte */
101 uart->ubg1 = ((counter & 0xff00) >> 8);
102 /* write to CTLR: divide counter lower byte */
103 uart->ubg2 = (counter & 0x00ff);
104
105 uart->ucr = UART_UCR_RESET_RX;
106 uart->ucr = UART_UCR_RESET_TX;
107
108 uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
109}
Marek Vasutabaef692012-09-13 16:51:38 +0200110
Marek Vasutabaef692012-09-13 16:51:38 +0200111static struct serial_device mcf_serial_drv = {
112 .name = "mcf_serial",
113 .start = mcf_serial_init,
114 .stop = NULL,
115 .setbrg = mcf_serial_setbrg,
116 .putc = mcf_serial_putc,
Marek Vasutec3fd682012-10-06 14:07:02 +0000117 .puts = default_serial_puts,
Marek Vasutabaef692012-09-13 16:51:38 +0200118 .getc = mcf_serial_getc,
119 .tstc = mcf_serial_tstc,
120};
121
122void mcf_serial_initialize(void)
123{
124 serial_register(&mcf_serial_drv);
125}
126
127__weak struct serial_device *default_serial_console(void)
128{
129 return &mcf_serial_drv;
130}