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wdenk3bac3512003-03-12 10:41:04 +00001/*
2**=====================================================================
3**
4** Copyright (C) 2000, 2001, 2002, 2003
5** The LEOX team <team@leox.org>, http://www.leox.org
6**
7** LEOX.org is about the development of free hardware and software resources
8** for system on chip.
9**
10** Description: U-Boot port on the LEOX's ELPT860 CPU board
11** ~~~~~~~~~~~
12**
13**=====================================================================
14**
Wolfgang Denk1a459662013-07-08 09:37:19 +020015 * SPDX-License-Identifier: GPL-2.0+
wdenk3bac3512003-03-12 10:41:04 +000016**
17**=====================================================================
18*/
19
20/*
21 * board/config.h - configuration options, board specific
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27
28/*
29 * High Level Configuration Options
30 * (easy to change)
31 */
32
33#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */
34#define CONFIG_MPC860T 1
35#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */
36
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#define CONFIG_SYS_TEXT_BASE 0x02000000
38
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenk3bac3512003-03-12 10:41:04 +000040#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42
wdenkc837dcb2004-01-20 23:12:12 +000043#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */
44#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */
wdenk3bac3512003-03-12 10:41:04 +000045
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47
wdenkc837dcb2004-01-20 23:12:12 +000048#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050049#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk3bac3512003-03-12 10:41:04 +000050
51/* BOOT arguments */
wdenkc837dcb2004-01-20 23:12:12 +000052#define CONFIG_PREBOOT \
53 "echo;" \
54 "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
wdenk3bac3512003-03-12 10:41:04 +000055 "echo"
56
wdenk8bde7f72003-06-27 21:31:46 +000057#undef CONFIG_BOOTARGS
wdenk3bac3512003-03-12 10:41:04 +000058
wdenkc837dcb2004-01-20 23:12:12 +000059#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk3bac3512003-03-12 10:41:04 +000060 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "rootargs=setenv rootpath /tftp/${ipaddr}\0" \
wdenk3bac3512003-03-12 10:41:04 +000062 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010063 "nfsroot=${serverip}:${rootpath}\0" \
64 "addip=setenv bootargs ${bootargs} " \
65 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
66 ":${hostname}:eth0:off panic=1\0" \
wdenk3bac3512003-03-12 10:41:04 +000067 "ramboot=tftp 400000 /home/paugaml/pMulti;" \
wdenk8bde7f72003-06-27 21:31:46 +000068 "run ramargs;bootm\0" \
wdenk3bac3512003-03-12 10:41:04 +000069 "nfsboot=tftp 400000 /home/paugaml/uImage;" \
wdenk8bde7f72003-06-27 21:31:46 +000070 "run rootargs;run nfsargs;run addip;bootm\0" \
wdenk3bac3512003-03-12 10:41:04 +000071 ""
72#define CONFIG_BOOTCOMMAND "run ramboot"
73
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050074/*
75 * BOOTP options
76 */
77#define CONFIG_BOOTP_SUBNETMASK
78#define CONFIG_BOOTP_GATEWAY
79#define CONFIG_BOOTP_HOSTNAME
80#define CONFIG_BOOTP_BOOTPATH
81#define CONFIG_BOOTP_BOOTFILESIZE
82
wdenk3bac3512003-03-12 10:41:04 +000083
84#undef CONFIG_WATCHDOG /* watchdog disabled */
85#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
86#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */
wdenkc837dcb2004-01-20 23:12:12 +000087#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */
wdenk3bac3512003-03-12 10:41:04 +000088
89#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk3bac3512003-03-12 10:41:04 +000091
wdenk3bac3512003-03-12 10:41:04 +000092
Jon Loeligerdcaa7152007-07-07 20:56:05 -050093/*
94 * Command line configuration.
95 */
96#include <config_cmd_default.h>
97
98#define CONFIG_CMD_ASKENV
99#define CONFIG_CMD_DATE
100
wdenk3bac3512003-03-12 10:41:04 +0000101
102/*
103 * Miscellaneous configurable options
104 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_LONGHELP /* undef to save memory */
106#define CONFIG_SYS_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
wdenk3bac3512003-03-12 10:41:04 +0000107
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500108#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk3bac3512003-03-12 10:41:04 +0000110#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk3bac3512003-03-12 10:41:04 +0000112#endif
113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
115#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
116#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk3bac3512003-03-12 10:41:04 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
119#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
wdenk3bac3512003-03-12 10:41:04 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenk3bac3512003-03-12 10:41:04 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk3bac3512003-03-12 10:41:04 +0000124
125/*
126 * Environment Variables and Storages
127 */
wdenkc837dcb2004-01-20 23:12:12 +0000128#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */
wdenk3bac3512003-03-12 10:41:04 +0000129
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200130#undef CONFIG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200131#undef CONFIG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200132#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */
wdenk3bac3512003-03-12 10:41:04 +0000133
wdenkc837dcb2004-01-20 23:12:12 +0000134#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */
wdenk3bac3512003-03-12 10:41:04 +0000135
wdenkc837dcb2004-01-20 23:12:12 +0000136#define CONFIG_ETHADDR 00:01:77:00:60:40
137#define CONFIG_IPADDR 192.168.0.30
138#define CONFIG_NETMASK 255.255.255.0
wdenk3bac3512003-03-12 10:41:04 +0000139
wdenkc837dcb2004-01-20 23:12:12 +0000140#define CONFIG_SERVERIP 192.168.0.1
141#define CONFIG_GATEWAYIP 192.168.0.1
wdenk3bac3512003-03-12 10:41:04 +0000142
143/*
144 * Low Level Configuration Settings
145 * (address mappings, register initial values, etc.)
146 * You should know what you are doing if you make changes here.
147 */
148
149/*-----------------------------------------------------------------------
150 * Internal Memory Mapped Register
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_IMMR 0xFF000000
wdenk3bac3512003-03-12 10:41:04 +0000153
154/*-----------------------------------------------------------------------
155 * Definitions for initial stack pointer and data area (in DPRAM)
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200158#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200159#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk3bac3512003-03-12 10:41:04 +0000161
162/*-----------------------------------------------------------------------
163 * Start addresses for the final memory configuration
164 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk3bac3512003-03-12 10:41:04 +0000166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_SDRAM_BASE 0x00000000
168#define CONFIG_SYS_FLASH_BASE 0x02000000
169#define CONFIG_SYS_NVRAM_BASE 0x03000000
wdenk3bac3512003-03-12 10:41:04 +0000170
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200171#if defined(CONFIG_ENV_IS_IN_FLASH)
wdenk3bac3512003-03-12 10:41:04 +0000172# if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173# define CONFIG_SYS_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */
wdenk3bac3512003-03-12 10:41:04 +0000174# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk3bac3512003-03-12 10:41:04 +0000176# endif
177#else
178# if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk3bac3512003-03-12 10:41:04 +0000180# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
wdenk3bac3512003-03-12 10:41:04 +0000182# endif
183#endif
184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
186#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk3bac3512003-03-12 10:41:04 +0000187
188/*
189 * For booting Linux, the board info and command line data
190 * have to be in the first 8 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization.
192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk3bac3512003-03-12 10:41:04 +0000194
195/*-----------------------------------------------------------------------
196 * FLASH organization
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
199#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
wdenk3bac3512003-03-12 10:41:04 +0000200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
202#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk3bac3512003-03-12 10:41:04 +0000203
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200204#if defined(CONFIG_ENV_IS_IN_FLASH)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200205# define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
206# define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
wdenk3bac3512003-03-12 10:41:04 +0000207#endif
208
209/*-----------------------------------------------------------------------
210 * NVRAM organization
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
213#define CONFIG_SYS_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */
wdenk8bde7f72003-06-27 21:31:46 +0000214 /* 8 top NVRAM locations */
wdenk3bac3512003-03-12 10:41:04 +0000215
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200216#if defined(CONFIG_ENV_IS_IN_NVRAM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217# define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200218# define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenk3bac3512003-03-12 10:41:04 +0000219#endif
220
221/*-----------------------------------------------------------------------
222 * Cache Configuration
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
wdenk3bac3512003-03-12 10:41:04 +0000225
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500226#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227# define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk3bac3512003-03-12 10:41:04 +0000228#endif
229
230/*-----------------------------------------------------------------------
231 * SYPCR - System Protection Control 11-9
232 * SYPCR can only be written once after reset!
233 *-----------------------------------------------------------------------
234 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
235 */
236#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000238 SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
wdenk3bac3512003-03-12 10:41:04 +0000239#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240# define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000241 SYPCR_SWP)
wdenk3bac3512003-03-12 10:41:04 +0000242#endif
243
244/*-----------------------------------------------------------------------
245 * SUMCR - SIU Module Configuration 11-6
246 *-----------------------------------------------------------------------
247 * PCMCIA config., multi-function pin tri-state
248 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11)
wdenk3bac3512003-03-12 10:41:04 +0000250
251/*-----------------------------------------------------------------------
252 * TBSCR - Time Base Status and Control 11-26
253 *-----------------------------------------------------------------------
254 * Clear Reference Interrupt Status, Timebase freezing enabled
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk3bac3512003-03-12 10:41:04 +0000257
258/*-----------------------------------------------------------------------
259 * RTCSC - Real-Time Clock Status and Control Register 11-27
260 *-----------------------------------------------------------------------
261 * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
262 * enabled
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk3bac3512003-03-12 10:41:04 +0000265
266/*-----------------------------------------------------------------------
267 * PISCR - Periodic Interrupt Status and Control 11-31
268 *-----------------------------------------------------------------------
269 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk3bac3512003-03-12 10:41:04 +0000272
273/*-----------------------------------------------------------------------
274 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
275 *-----------------------------------------------------------------------
276 * Reset PLL lock status sticky bit, timer expired status bit and timer
277 * interrupt status bit - leave PLL multiplication factor unchanged !
278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenk3bac3512003-03-12 10:41:04 +0000280
281/*-----------------------------------------------------------------------
282 * SCCR - System Clock and reset Control Register 15-27
283 *-----------------------------------------------------------------------
284 * Set clock output, timebase and RTC source and divider,
285 * power management and some other internal clocks
286 */
287#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk3bac3512003-03-12 10:41:04 +0000289 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
290 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
291 SCCR_DFALCD00)
292
293/*-----------------------------------------------------------------------
294 * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
295 *-----------------------------------------------------------------------
296 *
297 */
298#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299# define CONFIG_SYS_DER 0xFFE7400F /* Debug Enable Register */
wdenk3bac3512003-03-12 10:41:04 +0000300#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301# define CONFIG_SYS_DER 0
wdenk3bac3512003-03-12 10:41:04 +0000302#endif
303
304/*
305 * Init Memory Controller:
306 * ~~~~~~~~~~~~~~~~~~~~~~
307 *
308 * BR0 and OR0 (FLASH)
309 */
310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
wdenk3bac3512003-03-12 10:41:04 +0000312
313/* used to re-map FLASH both when starting from SRAM or FLASH:
314 * restrict access enough to keep SRAM working (if any)
315 * but not too much to meddle with FLASH accesses
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */
wdenk3bac3512003-03-12 10:41:04 +0000318
319/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
wdenk3bac3512003-03-12 10:41:04 +0000321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
323#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenk3bac3512003-03-12 10:41:04 +0000324
325/*
326 * BR1 and OR1 (SDRAM)
327 *
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define SDRAM_BASE1_PRELIM CONFIG_SYS_SDRAM_BASE /* SDRAM bank #0 */
wdenkc837dcb2004-01-20 23:12:12 +0000330#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */
wdenk3bac3512003-03-12 10:41:04 +0000331
wdenkc837dcb2004-01-20 23:12:12 +0000332/* SDRAM timing: */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000000
wdenk3bac3512003-03-12 10:41:04 +0000334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_OR1_PRELIM ((2 * CONFIG_SYS_PRELIM_OR_AM) | CONFIG_SYS_OR_TIMING_SDRAM )
336#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk3bac3512003-03-12 10:41:04 +0000337
338/*
339 * BR2 and OR2 (NVRAM)
340 *
341 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define NVRAM_BASE1_PRELIM CONFIG_SYS_NVRAM_BASE /* NVRAM bank #0 */
wdenkc837dcb2004-01-20 23:12:12 +0000343#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */
wdenk3bac3512003-03-12 10:41:04 +0000344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_OR2_PRELIM 0xFFF80160
346#define CONFIG_SYS_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
wdenk3bac3512003-03-12 10:41:04 +0000347
348/*
349 * Memory Periodic Timer Prescaler
350 */
351
352/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenk3bac3512003-03-12 10:41:04 +0000354
355/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
357#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk3bac3512003-03-12 10:41:04 +0000358
wdenkc837dcb2004-01-20 23:12:12 +0000359/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
361#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk3bac3512003-03-12 10:41:04 +0000362
363/*
364 * MAMR settings for SDRAM
365 */
366
367/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk3bac3512003-03-12 10:41:04 +0000369 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
370 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
371/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk3bac3512003-03-12 10:41:04 +0000373 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
374 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
375
wdenk3bac3512003-03-12 10:41:04 +0000376#endif /* __CONFIG_H */