Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 1 | /* |
Kumar Gala | 8b47d7e | 2011-01-04 17:57:59 -0600 | [diff] [blame] | 2 | * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * mpc8548cds board configuration file |
| 9 | * |
| 10 | * Please refer to doc/README.mpc85xxcds for more info. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __CONFIG_H |
| 14 | #define __CONFIG_H |
| 15 | |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 16 | #ifdef CONFIG_36BIT |
| 17 | #define CONFIG_PHYS_64BIT |
| 18 | #endif |
| 19 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 20 | /* High Level Configuration Options */ |
| 21 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 22 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 23 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
| 24 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ |
| 25 | #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ |
| 26 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 27 | #ifndef CONFIG_SYS_TEXT_BASE |
| 28 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
| 29 | #endif |
| 30 | |
Kumar Gala | 8b47d7e | 2011-01-04 17:57:59 -0600 | [diff] [blame] | 31 | #define CONFIG_SYS_SRIO |
| 32 | #define CONFIG_SRIO1 /* SRIO port 1 */ |
| 33 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 34 | #define CONFIG_PCI /* enable any pci type devices */ |
| 35 | #define CONFIG_PCI1 /* PCI controller 1 */ |
| 36 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 37 | #undef CONFIG_PCI2 |
| 38 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Gabor Juhos | 842033e | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 39 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
Kumar Gala | 8ff3de6 | 2007-12-07 12:17:34 -0600 | [diff] [blame] | 40 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
Kumar Gala | 0151cba | 2008-10-21 11:33:58 -0500 | [diff] [blame] | 41 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 42 | |
| 43 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 44 | #define CONFIG_ENV_OVERWRITE |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 45 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
Kumar Gala | 2cfaa1a | 2008-01-16 01:45:10 -0600 | [diff] [blame] | 46 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 47 | |
Jon Loeliger | 25eedb2 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 48 | #define CONFIG_FSL_VIA |
Jon Loeliger | 25eedb2 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 49 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 50 | #ifndef __ASSEMBLY__ |
| 51 | extern unsigned long get_clock_freq(void); |
| 52 | #endif |
| 53 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ |
| 54 | |
| 55 | /* |
| 56 | * These can be toggled for performance analysis, otherwise use default. |
| 57 | */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 58 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 59 | #define CONFIG_BTB /* toggle branch predition */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 60 | |
| 61 | /* |
| 62 | * Only possible on E500 Version 2 or newer cores. |
| 63 | */ |
| 64 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 65 | |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 66 | #ifdef CONFIG_PHYS_64BIT |
| 67 | #define CONFIG_ADDR_MAP |
| 68 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| 69 | #endif |
| 70 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 72 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 73 | |
Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 74 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| 75 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 76 | |
Jon Loeliger | e31d2c1 | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 77 | /* DDR Setup */ |
| 78 | #define CONFIG_FSL_DDR2 |
| 79 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 80 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 81 | #define CONFIG_DDR_SPD |
Jon Loeliger | e31d2c1 | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 82 | |
chenhui zhao | 867b06f | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 83 | #define CONFIG_DDR_ECC |
Dave Liu | 9b0ad1b | 2008-10-28 17:53:38 +0800 | [diff] [blame] | 84 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
Jon Loeliger | e31d2c1 | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 85 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 86 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 87 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 88 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 89 | |
Jon Loeliger | e31d2c1 | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 90 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 91 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 92 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 93 | |
Jon Loeliger | e31d2c1 | 2008-03-18 13:51:06 -0500 | [diff] [blame] | 94 | /* I2C addresses of SPD EEPROMs */ |
| 95 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
| 96 | |
| 97 | /* Make sure required options are set */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 98 | #ifndef CONFIG_SPD_EEPROM |
| 99 | #error ("CONFIG_SPD_EEPROM is required") |
| 100 | #endif |
| 101 | |
| 102 | #undef CONFIG_CLOCKS_IN_MHZ |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 103 | /* |
| 104 | * Physical Address Map |
| 105 | * |
| 106 | * 32bit: |
| 107 | * 0x0000_0000 0x7fff_ffff DDR 2G cacheable |
| 108 | * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable |
| 109 | * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable |
| 110 | * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable |
| 111 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable |
| 112 | * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable |
| 113 | * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable |
| 114 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable |
| 115 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable |
| 116 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable |
| 117 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable |
| 118 | * |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 119 | * 36bit: |
| 120 | * 0x00000_0000 0x07fff_ffff DDR 2G cacheable |
| 121 | * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable |
| 122 | * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable |
| 123 | * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable |
| 124 | * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable |
| 125 | * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable |
| 126 | * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable |
| 127 | * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable |
| 128 | * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable |
| 129 | * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable |
| 130 | * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable |
| 131 | * |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 132 | */ |
| 133 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 134 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 135 | /* |
| 136 | * Local Bus Definitions |
| 137 | */ |
| 138 | |
| 139 | /* |
| 140 | * FLASH on the Local Bus |
| 141 | * Two banks, 8M each, using the CFI driver. |
| 142 | * Boot from BR0/OR0 bank at 0xff00_0000 |
| 143 | * Alternate BR1/OR1 bank at 0xff80_0000 |
| 144 | * |
| 145 | * BR0, BR1: |
| 146 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 |
| 147 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 |
| 148 | * Port Size = 16 bits = BRx[19:20] = 10 |
| 149 | * Use GPCM = BRx[24:26] = 000 |
| 150 | * Valid = BRx[31] = 1 |
| 151 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 152 | * 0 4 8 12 16 20 24 28 |
| 153 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 |
| 154 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 155 | * |
| 156 | * OR0, OR1: |
| 157 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 |
| 158 | * Reserved ORx[17:18] = 11, confusion here? |
| 159 | * CSNT = ORx[20] = 1 |
| 160 | * ACS = half cycle delay = ORx[21:22] = 11 |
| 161 | * SCY = 6 = ORx[24:27] = 0110 |
| 162 | * TRLX = use relaxed timing = ORx[29] = 1 |
| 163 | * EAD = use external address latch delay = OR[31] = 1 |
| 164 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 165 | * 0 4 8 12 16 20 24 28 |
| 166 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 167 | */ |
| 168 | |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 169 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 170 | #ifdef CONFIG_PHYS_64BIT |
| 171 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull |
| 172 | #else |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 173 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 174 | #endif |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 175 | |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 176 | #define CONFIG_SYS_BR0_PRELIM \ |
Timur Tabi | 7ee4110 | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 177 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 178 | #define CONFIG_SYS_BR1_PRELIM \ |
| 179 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 180 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 181 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
| 182 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 183 | |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 184 | #define CONFIG_SYS_FLASH_BANKS_LIST \ |
| 185 | {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 187 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| 188 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 189 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 190 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 191 | |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 193 | |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 194 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | #define CONFIG_SYS_FLASH_CFI |
| 196 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 197 | |
chenhui zhao | 867b06f | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 198 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 199 | |
| 200 | /* |
| 201 | * SDRAM on the Local Bus |
| 202 | */ |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 203 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 204 | #ifdef CONFIG_PHYS_64BIT |
| 205 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull |
| 206 | #else |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 207 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 208 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 209 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 210 | |
| 211 | /* |
| 212 | * Base Register 2 and Option Register 2 configure SDRAM. |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 214 | * |
| 215 | * For BR2, need: |
| 216 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 217 | * port-size = 32-bits = BR2[19:20] = 11 |
| 218 | * no parity checking = BR2[21:22] = 00 |
| 219 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 220 | * Valid = BR[31] = 1 |
| 221 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 222 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 223 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 224 | * |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 225 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 226 | * FIXME: the top 17 bits of BR2. |
| 227 | */ |
| 228 | |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 229 | #define CONFIG_SYS_BR2_PRELIM \ |
| 230 | (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ |
| 231 | | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 232 | |
| 233 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 234 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 235 | * |
| 236 | * For OR2, need: |
| 237 | * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| 238 | * XAM, OR2[17:18] = 11 |
| 239 | * 9 columns OR2[19-21] = 010 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 240 | * 13 rows OR2[23-25] = 100 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 241 | * EAD set for extra time OR[31] = 1 |
| 242 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 243 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 244 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| 245 | */ |
| 246 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 248 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 249 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
| 250 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ |
| 251 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 252 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 253 | |
| 254 | /* |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 255 | * Common settings for all Local Bus SDRAM commands. |
| 256 | * At run time, either BSMA1516 (for CPU 1.1) |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 257 | * or BSMA1617 (for CPU 1.0) (old) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 258 | * is OR'ed in too. |
| 259 | */ |
Kumar Gala | b0fe93ed | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 260 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
| 261 | | LSDMR_PRETOACT7 \ |
| 262 | | LSDMR_ACTTORW7 \ |
| 263 | | LSDMR_BL8 \ |
| 264 | | LSDMR_WRC4 \ |
| 265 | | LSDMR_CL3 \ |
| 266 | | LSDMR_RFEN \ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 267 | ) |
| 268 | |
| 269 | /* |
| 270 | * The CADMUS registers are connected to CS3 on CDS. |
| 271 | * The new memory map places CADMUS at 0xf8000000. |
| 272 | * |
| 273 | * For BR3, need: |
| 274 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 |
| 275 | * port-size = 8-bits = BR[19:20] = 01 |
| 276 | * no parity checking = BR[21:22] = 00 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 277 | * GPMC for MSEL = BR[24:26] = 000 |
| 278 | * Valid = BR[31] = 1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 279 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 280 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 281 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
| 282 | * |
| 283 | * For OR3, need: |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 284 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 285 | * disable buffer ctrl OR[19] = 0 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 286 | * CSNT OR[20] = 1 |
| 287 | * ACS OR[21:22] = 11 |
| 288 | * XACS OR[23] = 1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 289 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 290 | * SETA OR[28] = 0 |
| 291 | * TRLX OR[29] = 1 |
| 292 | * EHTR OR[30] = 1 |
| 293 | * EAD extra time OR[31] = 1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 294 | * |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 295 | * 0 4 8 12 16 20 24 28 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 296 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
| 297 | */ |
| 298 | |
Jon Loeliger | 25eedb2 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 299 | #define CONFIG_FSL_CADMUS |
| 300 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 301 | #define CADMUS_BASE_ADDR 0xf8000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 302 | #ifdef CONFIG_PHYS_64BIT |
| 303 | #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull |
| 304 | #else |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 305 | #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 306 | #endif |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 307 | #define CONFIG_SYS_BR3_PRELIM \ |
| 308 | (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 309 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 310 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 311 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 312 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 313 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 314 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 315 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 316 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 317 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 318 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
chenhui zhao | 867b06f | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 319 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 320 | |
| 321 | /* Serial Port */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 322 | #define CONFIG_CONS_INDEX 2 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 323 | #define CONFIG_SYS_NS16550 |
| 324 | #define CONFIG_SYS_NS16550_SERIAL |
| 325 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 326 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 327 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 328 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 329 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 330 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 331 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 332 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 333 | |
| 334 | /* Use the HUSH parser */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 335 | #define CONFIG_SYS_HUSH_PARSER |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 336 | |
Matthew McClintock | 40d5fa3 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 337 | /* pass open firmware flat tree */ |
Kumar Gala | b90d254 | 2007-11-29 00:11:44 -0600 | [diff] [blame] | 338 | #define CONFIG_OF_LIBFDT 1 |
| 339 | #define CONFIG_OF_BOARD_SETUP 1 |
| 340 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
Matthew McClintock | 40d5fa3 | 2006-06-28 10:43:36 -0500 | [diff] [blame] | 341 | |
Jon Loeliger | 2047672 | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 342 | /* |
| 343 | * I2C |
| 344 | */ |
| 345 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 346 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 347 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 348 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 349 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 350 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
| 351 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 352 | |
Timur Tabi | e8d1854 | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 353 | /* EEPROM */ |
| 354 | #define CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 355 | #define CONFIG_SYS_I2C_EEPROM_CCID |
| 356 | #define CONFIG_SYS_ID_EEPROM |
| 357 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 358 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
Timur Tabi | e8d1854 | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 359 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 360 | /* |
| 361 | * General PCI |
Sergei Shtylyov | 362dd83 | 2006-12-27 22:07:15 +0300 | [diff] [blame] | 362 | * Memory space is mapped 1-1, but I/O space must start from 0. |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 363 | */ |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 364 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 365 | #ifdef CONFIG_PHYS_64BIT |
| 366 | #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 |
| 367 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull |
| 368 | #else |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 369 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 370 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 371 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 372 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | aca5f01 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 373 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 374 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 375 | #ifdef CONFIG_PHYS_64BIT |
| 376 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull |
| 377 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 378 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 379 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 380 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 381 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 382 | #ifdef CONFIG_PCIE1 |
Kumar Gala | f5fa8f3 | 2010-12-17 10:21:22 -0600 | [diff] [blame] | 383 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 384 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 385 | #ifdef CONFIG_PHYS_64BIT |
| 386 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 387 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull |
| 388 | #else |
Kumar Gala | 10795f4 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 389 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
Kumar Gala | 5af0fdd | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 390 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 391 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 392 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | aca5f01 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 393 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 |
Kumar Gala | 5f91ef6 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 394 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 395 | #ifdef CONFIG_PHYS_64BIT |
| 396 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull |
| 397 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 398 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 399 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 400 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 401 | #endif |
Zang Roy-r61911 | 41fb7e0 | 2006-12-14 14:14:55 +0800 | [diff] [blame] | 402 | |
| 403 | /* |
| 404 | * RapidIO MMU |
| 405 | */ |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 406 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 407 | #ifdef CONFIG_PHYS_64BIT |
| 408 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull |
| 409 | #else |
chenhui zhao | fff8097 | 2011-10-13 13:40:59 +0800 | [diff] [blame] | 410 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 |
chenhui zhao | b76aef6 | 2011-10-13 13:41:00 +0800 | [diff] [blame] | 411 | #endif |
Kumar Gala | 8b47d7e | 2011-01-04 17:57:59 -0600 | [diff] [blame] | 412 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 413 | |
Randy Vinson | 7f3f2bd | 2007-02-27 19:42:22 -0700 | [diff] [blame] | 414 | #ifdef CONFIG_LEGACY |
| 415 | #define BRIDGE_ID 17 |
| 416 | #define VIA_ID 2 |
| 417 | #else |
| 418 | #define BRIDGE_ID 28 |
| 419 | #define VIA_ID 4 |
| 420 | #endif |
| 421 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 422 | #if defined(CONFIG_PCI) |
| 423 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 424 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 425 | |
| 426 | #undef CONFIG_EEPRO100 |
| 427 | #undef CONFIG_TULIP |
chenhui zhao | 867b06f | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 428 | #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 429 | |
chenhui zhao | 867b06f | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 430 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 431 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 432 | #endif /* CONFIG_PCI */ |
| 433 | |
| 434 | |
| 435 | #if defined(CONFIG_TSEC_ENET) |
| 436 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 437 | #define CONFIG_MII 1 /* MII PHY management */ |
Kim Phillips | 255a3577 | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 438 | #define CONFIG_TSEC1 1 |
| 439 | #define CONFIG_TSEC1_NAME "eTSEC0" |
| 440 | #define CONFIG_TSEC2 1 |
| 441 | #define CONFIG_TSEC2_NAME "eTSEC1" |
| 442 | #define CONFIG_TSEC3 1 |
| 443 | #define CONFIG_TSEC3_NAME "eTSEC2" |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 444 | #define CONFIG_TSEC4 |
Kim Phillips | 255a3577 | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 445 | #define CONFIG_TSEC4_NAME "eTSEC3" |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 446 | #undef CONFIG_MPC85XX_FEC |
| 447 | |
chenhui zhao | d370122 | 2011-09-06 16:41:18 +0000 | [diff] [blame] | 448 | #define CONFIG_PHY_MARVELL |
| 449 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 450 | #define TSEC1_PHY_ADDR 0 |
| 451 | #define TSEC2_PHY_ADDR 1 |
| 452 | #define TSEC3_PHY_ADDR 2 |
| 453 | #define TSEC4_PHY_ADDR 3 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 454 | |
| 455 | #define TSEC1_PHYIDX 0 |
| 456 | #define TSEC2_PHYIDX 0 |
| 457 | #define TSEC3_PHYIDX 0 |
| 458 | #define TSEC4_PHYIDX 0 |
Andy Fleming | 3a79013 | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 459 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 460 | #define TSEC2_FLAGS TSEC_GIGABIT |
| 461 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 462 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 463 | |
| 464 | /* Options are: eTSEC[0-3] */ |
| 465 | #define CONFIG_ETHPRIME "eTSEC0" |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 466 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 467 | #endif /* CONFIG_TSEC_ENET */ |
| 468 | |
| 469 | /* |
| 470 | * Environment |
| 471 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 472 | #define CONFIG_ENV_IS_IN_FLASH 1 |
chenhui zhao | 867b06f | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 473 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
| 474 | #define CONFIG_ENV_ADDR 0xfff80000 |
| 475 | #else |
| 476 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 477 | #endif |
| 478 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 479 | #define CONFIG_ENV_SIZE 0x2000 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 480 | |
| 481 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 482 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 483 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 484 | /* |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 485 | * BOOTP options |
| 486 | */ |
| 487 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 488 | #define CONFIG_BOOTP_BOOTPATH |
| 489 | #define CONFIG_BOOTP_GATEWAY |
| 490 | #define CONFIG_BOOTP_HOSTNAME |
| 491 | |
| 492 | |
| 493 | /* |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 494 | * Command line configuration. |
| 495 | */ |
| 496 | #include <config_cmd_default.h> |
| 497 | |
| 498 | #define CONFIG_CMD_PING |
| 499 | #define CONFIG_CMD_I2C |
| 500 | #define CONFIG_CMD_MII |
Kumar Gala | 82ac8c9 | 2007-12-07 12:04:30 -0600 | [diff] [blame] | 501 | #define CONFIG_CMD_ELF |
Kumar Gala | 1c9aa76 | 2008-09-22 23:40:42 -0500 | [diff] [blame] | 502 | #define CONFIG_CMD_IRQ |
| 503 | #define CONFIG_CMD_SETEXPR |
Becky Bruce | 199e262 | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 504 | #define CONFIG_CMD_REGINFO |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 505 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 506 | #if defined(CONFIG_PCI) |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 507 | #define CONFIG_CMD_PCI |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 508 | #endif |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 509 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 510 | |
| 511 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 512 | |
| 513 | /* |
| 514 | * Miscellaneous configurable options |
| 515 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 516 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Kim Phillips | 5be58f5 | 2010-07-14 19:47:18 -0500 | [diff] [blame] | 517 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 518 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 519 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 520 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 521 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 522 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 523 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 524 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 525 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 526 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 527 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 528 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 529 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 530 | |
| 531 | /* |
| 532 | * For booting Linux, the board info and command line data |
Kumar Gala | a832ac4 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 533 | * have to be in the first 64 MB of memory, since this is |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 534 | * the maximum mapped by the Linux kernel during initialization. |
| 535 | */ |
Kumar Gala | a832ac4 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 536 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 537 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 538 | |
Jon Loeliger | 2835e51 | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 539 | #if defined(CONFIG_CMD_KGDB) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 540 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 541 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 542 | #endif |
| 543 | |
| 544 | /* |
| 545 | * Environment Configuration |
| 546 | */ |
| 547 | |
| 548 | /* The mac addresses for all ethernet interface */ |
| 549 | #if defined(CONFIG_TSEC_ENET) |
Andy Fleming | 10327dc | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 550 | #define CONFIG_HAS_ETH0 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 551 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 552 | #define CONFIG_HAS_ETH1 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 553 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 554 | #define CONFIG_HAS_ETH2 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 555 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
Andy Fleming | 09f3e09 | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 556 | #define CONFIG_HAS_ETH3 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 557 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 558 | #endif |
| 559 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 560 | #define CONFIG_IPADDR 192.168.1.253 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 561 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 562 | #define CONFIG_HOSTNAME unknown |
Joe Hershberger | 8b3637c | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 563 | #define CONFIG_ROOTPATH "/nfsroot" |
Joe Hershberger | b3f44c2 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 564 | #define CONFIG_BOOTFILE "8548cds/uImage.uboot" |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 565 | #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 566 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 567 | #define CONFIG_SERVERIP 192.168.1.1 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 568 | #define CONFIG_GATEWAYIP 192.168.1.1 |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 569 | #define CONFIG_NETMASK 255.255.255.0 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 570 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 571 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 572 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 573 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
| 574 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 575 | |
| 576 | #define CONFIG_BAUDRATE 115200 |
| 577 | |
chenhui zhao | 867b06f | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 578 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 579 | "hwconfig=fsl_ddr:ecc=off\0" \ |
| 580 | "netdev=eth0\0" \ |
Marek Vasut | 5368c55 | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 581 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
chenhui zhao | 867b06f | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 582 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
Marek Vasut | 5368c55 | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 583 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 584 | " +$filesize; " \ |
| 585 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 586 | " +$filesize; " \ |
| 587 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 588 | " $filesize; " \ |
| 589 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 590 | " +$filesize; " \ |
| 591 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 592 | " $filesize\0" \ |
chenhui zhao | 867b06f | 2011-09-06 16:41:19 +0000 | [diff] [blame] | 593 | "consoledev=ttyS1\0" \ |
| 594 | "ramdiskaddr=2000000\0" \ |
| 595 | "ramdiskfile=ramdisk.uboot\0" \ |
| 596 | "fdtaddr=c00000\0" \ |
| 597 | "fdtfile=mpc8548cds.dtb\0" |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 598 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 599 | #define CONFIG_NFSBOOTCOMMAND \ |
| 600 | "setenv bootargs root=/dev/nfs rw " \ |
| 601 | "nfsroot=$serverip:$rootpath " \ |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 602 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 603 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 604 | "tftp $loadaddr $bootfile;" \ |
Ed Swarthout | 4bf4abb | 2007-08-21 09:38:59 -0500 | [diff] [blame] | 605 | "tftp $fdtaddr $fdtfile;" \ |
| 606 | "bootm $loadaddr - $fdtaddr" |
Andy Fleming | 8272dc2 | 2006-09-13 10:33:35 -0500 | [diff] [blame] | 607 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 608 | |
| 609 | #define CONFIG_RAMBOOTCOMMAND \ |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 610 | "setenv bootargs root=/dev/ram rw " \ |
| 611 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 612 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 613 | "tftp $loadaddr $bootfile;" \ |
Ed Swarthout | 4bf4abb | 2007-08-21 09:38:59 -0500 | [diff] [blame] | 614 | "tftp $fdtaddr $fdtfile;" \ |
| 615 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 616 | |
Ed Swarthout | f2cff6b | 2007-07-27 01:50:52 -0500 | [diff] [blame] | 617 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 618 | |
| 619 | #endif /* __CONFIG_H */ |