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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
21#define CONFIG_MVS 1 /* ...on a MVsensor module */
22#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */
23#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */
24
25#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
26
27#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */
28#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
29#undef CONFIG_8xx_CONS_NONE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020030#define CONFIG_BAUDRATE 115200 /* console baudrate */
wdenkc6097192002-11-03 00:24:07 +000031#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
32
Wolfgang Denk53677ef2008-05-20 16:00:29 +020033#define CONFIG_PREBOOT "echo;" \
34 "echo To mount root over NFS use \"run bootnet\";" \
35 "echo To mount root from FLASH use \"run bootflash\";" \
36 "echo"
wdenkc6097192002-11-03 00:24:07 +000037#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
Wolfgang Denk53677ef2008-05-20 16:00:29 +020038#define CONFIG_BOOTCOMMAND \
39 "bootp; " \
40 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
41 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
42 "bootm"
wdenkc6097192002-11-03 00:24:07 +000043
44#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000046
47#define CONFIG_WATCHDOG /* watchdog disabled/enabled */
48
49#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
50
Wolfgang Denk53677ef2008-05-20 16:00:29 +020051#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
wdenkc6097192002-11-03 00:24:07 +000052
Jon Loeliger7be044e2007-07-09 21:24:19 -050053
54/*
55 * BOOTP options
56 */
57#define CONFIG_BOOTP_SUBNETMASK
58#define CONFIG_BOOTP_GATEWAY
59#define CONFIG_BOOTP_HOSTNAME
60#define CONFIG_BOOTP_BOOTPATH
61#define CONFIG_BOOTP_VENDOREX
wdenkc6097192002-11-03 00:24:07 +000062
63#undef CONFIG_MAC_PARTITION
64#undef CONFIG_DOS_PARTITION
65
66#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
67
wdenkc6097192002-11-03 00:24:07 +000068
Jon Loeliger8353e132007-07-08 14:14:17 -050069/*
70 * Command line configuration.
71 */
72#define CONFIG_CMD_LOADS
73#define CONFIG_CMD_LOADB
74#define CONFIG_CMD_IMI
75#define CONFIG_CMD_FLASH
76#define CONFIG_CMD_MEMORY
77#define CONFIG_CMD_NET
78#define CONFIG_CMD_DHCP
Mike Frysingerbdab39d2009-01-28 19:08:14 -050079#define CONFIG_CMD_SAVEENV
Jon Loeliger8353e132007-07-08 14:14:17 -050080#define CONFIG_CMD_BOOTD
81#define CONFIG_CMD_RUN
82
wdenkc6097192002-11-03 00:24:07 +000083
84/*
85 * Miscellaneous configurable options
86 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#undef CONFIG_SYS_LONGHELP /* undef to save memory */
88#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkc6097192002-11-03 00:24:07 +000089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */
wdenkc6097192002-11-03 00:24:07 +000091
Jon Loeliger8353e132007-07-08 14:14:17 -050092#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000094#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000096#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
98#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
99#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
102#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkc6097192002-11-03 00:24:07 +0000105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000107
wdenkc6097192002-11-03 00:24:07 +0000108/*
109 * Low Level Configuration Settings
110 * (address mappings, register initial values, etc.)
111 * You should know what you are doing if you make changes here.
112 */
113/*-----------------------------------------------------------------------
114 * Internal Memory Mapped Register
115 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_IMMR 0xFFF00000
wdenkc6097192002-11-03 00:24:07 +0000117
118/*-----------------------------------------------------------------------
119 * Definitions for initial stack pointer and data area (in DPRAM)
120 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200122#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200123#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000125
126/*-----------------------------------------------------------------------
127 * Start addresses for the final memory configuration
128 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_SDRAM_BASE 0x00000000
132#define CONFIG_SYS_FLASH_BASE 0x40000000
wdenkc6097192002-11-03 00:24:07 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */
wdenkc6097192002-11-03 00:24:07 +0000135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
137#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000138
139/*
140 * For booting Linux, the board info and command line data
141 * have to be in the first 8 MB of memory, since this is
142 * the maximum mapped by the Linux kernel during initialization.
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000145
146/*-----------------------------------------------------------------------
147 * FLASH organization
148 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
150#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */
wdenkc6097192002-11-03 00:24:07 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
153#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000154
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200155#define CONFIG_ENV_IS_IN_FLASH 1
wdenkc6097192002-11-03 00:24:07 +0000156
157/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200158#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */
159#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */
wdenkc6097192002-11-03 00:24:07 +0000160
161/*-----------------------------------------------------------------------
162 * Cache Configuration
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger8353e132007-07-08 14:14:17 -0500165#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000167#endif
168
169/*-----------------------------------------------------------------------
170 * SYPCR - System Protection Control 11-9
171 * SYPCR can only be written once after reset!
172 *-----------------------------------------------------------------------
173 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
174 */
175#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200177 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
wdenkc6097192002-11-03 00:24:07 +0000178#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkc6097192002-11-03 00:24:07 +0000180#endif
181
182/*-----------------------------------------------------------------------
183 * SIUMCR - SIU Module Configuration 11-6
184 *-----------------------------------------------------------------------
185 * PCMCIA config., multi-function pin tri-state
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkc6097192002-11-03 00:24:07 +0000188
189/*-----------------------------------------------------------------------
190 * TBSCR - Time Base Status and Control 11-26
191 *-----------------------------------------------------------------------
192 * Clear Reference Interrupt Status, Timebase freezing enabled
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkc6097192002-11-03 00:24:07 +0000195
196/*-----------------------------------------------------------------------
197 * RTCSC - Real-Time Clock Status and Control Register 11-27
198 *-----------------------------------------------------------------------
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkc6097192002-11-03 00:24:07 +0000201
202/*-----------------------------------------------------------------------
203 * PISCR - Periodic Interrupt Status and Control 11-31
204 *-----------------------------------------------------------------------
205 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkc6097192002-11-03 00:24:07 +0000208
209/*-----------------------------------------------------------------------
210 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
211 *-----------------------------------------------------------------------
212 * Reset PLL lock status sticky bit, timer expired status bit and timer
213 * interrupt status bit
214 *
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkc6097192002-11-03 00:24:07 +0000217
218/*-----------------------------------------------------------------------
219 * SCCR - System Clock and reset Control Register 15-27
220 *-----------------------------------------------------------------------
221 * Set clock output, timebase and RTC source and divider,
222 * power management and some other internal clocks
223 */
224#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenkc6097192002-11-03 00:24:07 +0000226 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
227 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
228 SCCR_DFALCD00)
229
230/*-----------------------------------------------------------------------
231 * PCMCIA stuff
232 *-----------------------------------------------------------------------
233 *
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
236#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
237#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
238#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
239#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
240#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
241#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
242#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkc6097192002-11-03 00:24:07 +0000243
244/*-----------------------------------------------------------------------
245 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
246 *-----------------------------------------------------------------------
247 */
248
249#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */
250
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200251#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
252#undef CONFIG_IDE_LED /* LED for ide not supported */
wdenkc6097192002-11-03 00:24:07 +0000253#undef CONFIG_IDE_RESET /* reset for ide not supported */
254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */
256#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000257
258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkc6097192002-11-03 00:24:07 +0000262
263/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkc6097192002-11-03 00:24:07 +0000265
266/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkc6097192002-11-03 00:24:07 +0000268
269/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkc6097192002-11-03 00:24:07 +0000271
272/*-----------------------------------------------------------------------
273 *
274 *-----------------------------------------------------------------------
275 *
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277/*#define CONFIG_SYS_DER 0x2002000F*/
278#define CONFIG_SYS_DER 0
wdenkc6097192002-11-03 00:24:07 +0000279
280/*
281 * Init Memory Controller:
282 *
283 * BR0/1 and OR0/1 (FLASH)
284 */
285
286#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
287#undef FLASH_BASE1_PRELIM
288
289/* used to re-map FLASH both when starting from SRAM or FLASH:
290 * restrict access enough to keep SRAM working (if any)
291 * but not too much to meddle with FLASH accesses
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
294#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkc6097192002-11-03 00:24:07 +0000295
296
297/*
298 * FLASH timing:
299 */
300/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkc6097192002-11-03 00:24:07 +0000302 OR_SCY_2_CLK | OR_EHTR | OR_BI)
303/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
304/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
wdenkc6097192002-11-03 00:24:07 +0000306 OR_SCY_5_CLK | OR_EHTR)
307*/
308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
310#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
wdenkc6097192002-11-03 00:24:07 +0000311#ifdef CONFIG_MVS_16BIT_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
wdenkc6097192002-11-03 00:24:07 +0000313#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
wdenkc6097192002-11-03 00:24:07 +0000315#endif
316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#undef CONFIG_SYS_OR1_REMAP
318#undef CONFIG_SYS_OR1_PRELIM
319#undef CONFIG_SYS_BR1_PRELIM
wdenkc6097192002-11-03 00:24:07 +0000320/*
321 * BR2/3 and OR2/3 (SDRAM)
322 *
323 */
324#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
325#undef SDRAM_BASE3_PRELIM
326#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
327
328/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkc6097192002-11-03 00:24:07 +0000330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
332#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkc6097192002-11-03 00:24:07 +0000333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#undef CONFIG_SYS_OR3_PRELIM
335#undef CONFIG_SYS_BR3_PRELIM
wdenkc6097192002-11-03 00:24:07 +0000336
337
338/*
339 * Memory Periodic Timer Prescaler
340 *
341 * The Divider for PTA (refresh timer) configuration is based on an
342 * example SDRAM configuration (64 MBit, one bank). The adjustment to
343 * the number of chip selects (NCS) and the actually needed refresh
344 * rate is done by setting MPTPR.
345 *
346 * PTA is calculated from
347 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
348 *
349 * gclk CPU clock (not bus clock!)
350 * Trefresh Refresh cycle * 4 (four word bursts used)
351 *
352 * 4096 Rows from SDRAM example configuration
353 * 1000 factor s -> ms
354 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
355 * 4 Number of refresh cycles per period
356 * 64 Refresh cycle in ms per number of rows
357 * --------------------------------------------
358 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
359 *
360 * 50 MHz => 50.000.000 / Divider = 98
361 * 66 Mhz => 66.000.000 / Divider = 129
362 * 80 Mhz => 80.000.000 / Divider = 156
363 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_MAMR_PTA 98
wdenkc6097192002-11-03 00:24:07 +0000365
366/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
368#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkc6097192002-11-03 00:24:07 +0000369
370/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
372#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkc6097192002-11-03 00:24:07 +0000373
374/*
375 * MAMR settings for SDRAM
376 */
377
378/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc6097192002-11-03 00:24:07 +0000380 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
381 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
382/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkc6097192002-11-03 00:24:07 +0000384 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \
385 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
386
wdenkc6097192002-11-03 00:24:07 +0000387#endif /* __CONFIG_H */