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Sergey Yanovichc3442c12013-05-21 01:26:00 +04001/*
2 * ICP DAS LP-8x4x configuration file
3 *
4 * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Sergey Yanovichc3442c12013-05-21 01:26:00 +04007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Board Configuration Options
14 */
15#define CONFIG_CPU_PXA27X /* Marvell PXA270 CPU */
16#define MACH_TYPE_LP8X4X 4539 /* ICP DAS LP-8x4x */
17#define CONFIG_MACH_TYPE MACH_TYPE_LP8X4X
18#define CONFIG_SYS_TEXT_BASE 0x00000000
19
20#define CONFIG_SYS_MALLOC_LEN (128*1024)
21#define CONFIG_ARCH_CPU_INIT
22#define CONFIG_BOOTCOMMAND \
23 "bootm 80000;"
24
25#define CONFIG_BOOTARGS \
26 "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
27 "init=/sbin/init rootfstype=ext3"
28
29#define CONFIG_TIMESTAMP
30#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
31#define CONFIG_CMDLINE_TAG
32#define CONFIG_SETUP_MEMORY_TAGS
33#define CONFIG_LZMA /* LZMA compression support */
34#undef CONFIG_OF_LIBFDT
35
36/*
37 * Serial Console Configuration
38 */
39#define CONFIG_PXA_SERIAL
40#define CONFIG_FFUART 1
41#define CONFIG_CONS_INDEX 3
42#define CONFIG_BAUDRATE 115200
43
44/*
45 * Bootloader Components Configuration
46 */
47#include <config_cmd_default.h>
48
49#define CONFIG_CMD_NET
50#define CONFIG_CMD_ENV
51#undef CONFIG_CMD_IMLS
52#define CONFIG_CMD_MMC
53#define CONFIG_CMD_USB
54#undef CONFIG_LCD
55#undef CONFIG_CMD_IDE
56
57/*
58 * Networking Configuration
59 * chip on the ICPDAS LINPAC board
60 */
61#ifdef CONFIG_CMD_NET
62#define CONFIG_CMD_PING
63#define CONFIG_CMD_DHCP
64
65#define CONFIG_DRIVER_DM9000 1
66#define CONFIG_DM9000_BASE 0x0C000000
67#define DM9000_IO 0x0C000000
68#define DM9000_DATA 0x0C004000
69#define DM9000_IO_2 0x0D000000
70#define DM9000_DATA_2 0x0D004000
71#define CONFIG_NET_RETRY_COUNT 10
72
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77#endif
78
79/*
80 * MMC Card Configuration
81 */
82#ifdef CONFIG_CMD_MMC
83#define CONFIG_MMC
84#define CONFIG_GENERIC_MMC
85#define CONFIG_PXA_MMC_GENERIC
86#define CONFIG_CMD_FAT
87#define CONFIG_CMD_EXT2
88#define CONFIG_DOS_PARTITION
89#endif
90
91/*
92 * KGDB
93 */
94#ifdef CONFIG_CMD_KGDB
95#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */
96#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
97#endif
98
99/*
100 * HUSH Shell Configuration
101 */
102#define CONFIG_SYS_HUSH_PARSER 1
103
104#undef CONFIG_SYS_LONGHELP
105#ifdef CONFIG_SYS_HUSH_PARSER
106#define CONFIG_SYS_PROMPT "$ "
107#else
108#define CONFIG_SYS_PROMPT "=> "
109#endif
110#define CONFIG_SYS_CBSIZE 256
111#define CONFIG_SYS_PBSIZE \
112 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
113#define CONFIG_SYS_MAXARGS 16
114#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
115#define CONFIG_SYS_DEVICE_NULLDEV 1
116#define CONFIG_CMDLINE_EDITING 1
117#define CONFIG_AUTO_COMPLETE 1
118
119/*
120 * Clock Configuration
121 */
122#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */
123
124/*
125 * DRAM Map
126 */
127#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
128#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
129#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
130
131#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
132#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */
133
134#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
135#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
136
137#define CONFIG_SYS_LOAD_ADDR 0xa0008000
138#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
139/* Use first 64kb bank of the internal SRAM */
140#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
141
142/*
143 * NOR FLASH
144 */
145#define CONFIG_SYS_MONITOR_BASE 0x0
146#define CONFIG_SYS_MONITOR_LEN 0x40000
147#define CONFIG_ENV_ADDR \
148 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
149#define CONFIG_ENV_SIZE 0x40000
150#define CONFIG_ENV_SECT_SIZE 0x40000
151
152#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
153#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
154
155#define CONFIG_SYS_FLASH_CFI
156#define CONFIG_FLASH_CFI_DRIVER 1
157
158#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
159#define CONFIG_SYS_MAX_FLASH_BANKS 2
160#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
161
162#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
163#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
164
165#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
166#define CONFIG_SYS_FLASH_PROTECTION 1
167
168#define CONFIG_ENV_IS_IN_FLASH 1
169
170/*
171 * GPIO settings
172 */
173#define CONFIG_SYS_GPSR0_VAL 0x0808c014
174#define CONFIG_SYS_GPSR1_VAL 0x00cf0002
175#define CONFIG_SYS_GPSR2_VAL 0x0221c000
176#define CONFIG_SYS_GPSR3_VAL 0x00020000
177
178#define CONFIG_SYS_GPCR0_VAL 0x00000000
179#define CONFIG_SYS_GPCR1_VAL 0x0000ab80
180#define CONFIG_SYS_GPCR2_VAL 0x00100000
181#define CONFIG_SYS_GPCR3_VAL 0x0
182
183#define CONFIG_SYS_GPDR0_VAL 0xc0e9ddf4
184#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
185#define CONFIG_SYS_GPDR2_VAL 0x02f1ffff
186#define CONFIG_SYS_GPDR3_VAL 0x00021b81
187
188#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
189#define CONFIG_SYS_GAFR0_U_VAL 0xa5e54018
190#define CONFIG_SYS_GAFR1_L_VAL 0x999a955a
191#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a00a
192#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
193#define CONFIG_SYS_GAFR2_U_VAL 0x55f0a402
194#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c
195#define CONFIG_SYS_GAFR3_U_VAL 0x00001599
196
197#define CONFIG_SYS_PSSR_VAL 0x32
198
199/*
200 * Clock settings
201 */
202#define CONFIG_SYS_CKEN 0x005002c0
203#define CONFIG_SYS_CCCR 0x02000290
204#define CONFIG_SYS_CLKCFG 0x0000000b
205
206/*
207 * Memory settings
208 */
209#define CONFIG_SYS_MSC0_VAL 0x2bd8aad2
210#define CONFIG_SYS_MSC1_VAL 0xb8c9b8dc
211#define CONFIG_SYS_MSC2_VAL 0xfff9b8c9
212#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
213#define CONFIG_SYS_MDREFR_VAL 0x2093e018
214#define CONFIG_SYS_MDCNFG_VAL 0x890009d1
215#define CONFIG_SYS_MDMRS_VAL 0x00220022
216#define CONFIG_SYS_SXCNFG_VAL 0x40044004
217
218/*
219 * PCMCIA and CF Interfaces
220 */
221#define CONFIG_SYS_MECR_VAL 0x00000001
222#define CONFIG_SYS_MCMEM0_VAL 0x0000c497
223#define CONFIG_SYS_MCMEM1_VAL 0x0000c497
224#define CONFIG_SYS_MCATT0_VAL 0x0000c497
225#define CONFIG_SYS_MCATT1_VAL 0x0000c497
226#define CONFIG_SYS_MCIO0_VAL 0x00008407
227#define CONFIG_SYS_MCIO1_VAL 0x00008407
228
229/*
230 * LCD
231 */
232#ifdef CONFIG_LCD
233#define CONFIG_VOIPAC_LCD
234#endif
235
236/*
237 * USB
238 */
239#ifdef CONFIG_CMD_USB
240#define CONFIG_USB_OHCI_NEW
241#define CONFIG_SYS_USB_OHCI_CPU_INIT
242#define CONFIG_SYS_USB_OHCI_BOARD_INIT
243#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
244#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
245#define CONFIG_SYS_USB_OHCI_SLOT_NAME "lp8x4x"
246#define CONFIG_USB_STORAGE
247#endif
248
249#endif /* __CONFIG_H */