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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Wolfgang Denk74f43042005-09-25 01:48:28 +02002/*
3 * armboot - Startup Code for ARM926EJS CPU-core
4 *
5 * Copyright (c) 2003 Texas Instruments
6 *
7 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 *
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02009 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
10 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
Detlev Zundel792a09e2009-05-13 10:54:10 +020011 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
Wolfgang Denk74f43042005-09-25 01:48:28 +020012 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
13 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
Albert ARIBAUD57b4bce2011-04-22 19:41:02 +020014 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
Wolfgang Denk74f43042005-09-25 01:48:28 +020015 */
16
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020017#include <asm-offsets.h>
Wolfgang Denk74f43042005-09-25 01:48:28 +020018#include <config.h>
Wolfgang Denk74f43042005-09-25 01:48:28 +020019
20/*
21 *************************************************************************
22 *
Wolfgang Denk74f43042005-09-25 01:48:28 +020023 * Startup Code (reset vector)
24 *
25 * do important init only if we don't start from memory!
26 * setup Memory and board specific bits prior to relocation.
27 * relocate armboot to ram
28 * setup stack
29 *
30 *************************************************************************
31 */
32
Albert ARIBAUD41623c92014-04-15 16:13:51 +020033 .globl reset
Heiko Schocher5a8a87e2010-09-17 13:10:45 +020034
35reset:
36 /*
37 * set the cpu to SVC32 mode
38 */
39 mrs r0,cpsr
40 bic r0,r0,#0x1f
41 orr r0,r0,#0xd3
42 msr cpsr,r0
43
44 /*
45 * we do sys-critical inits only at reboot,
46 * not when booting from ram!
47 */
48#ifndef CONFIG_SKIP_LOWLEVEL_INIT
49 bl cpu_init_crit
50#endif
51
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000052 bl _main
Heiko Schocher5a8a87e2010-09-17 13:10:45 +020053
54/*------------------------------------------------------------------------------*/
55
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000056 .globl c_runtime_cpu_setup
57c_runtime_cpu_setup:
58
59 mov pc, lr
60
Wolfgang Denk74f43042005-09-25 01:48:28 +020061/*
62 *************************************************************************
63 *
64 * CPU_init_critical registers
65 *
66 * setup important registers
67 * setup memory timing
68 *
69 *************************************************************************
70 */
71
72
Jean-Christophe PLAGNIOL-VILLARD8fc3bb42009-05-15 23:45:20 +020073#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Wolfgang Denk74f43042005-09-25 01:48:28 +020074cpu_init_crit:
75 /*
76 * flush v4 I/D caches
77 */
78 mov r0, #0
79 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
80 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
81
82 /*
83 * disable MMU stuff and caches
84 */
85 mrc p15, 0, r0, c1, c0, 0
86 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
87 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
Yuichiro Gotoba10b852016-02-25 10:23:34 +090088 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
Wolfgang Denk74f43042005-09-25 01:48:28 +020089 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
90 mcr p15, 0, r0, c1, c0, 0
91
Simon Glassb5bd0982016-05-05 07:28:06 -060092#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
Wolfgang Denk74f43042005-09-25 01:48:28 +020093 /*
94 * Go setup Memory and board specific bits prior to relocation.
95 */
96 mov ip, lr /* perserve link reg across call */
Wolfgang Denk87cb6862005-10-06 17:08:18 +020097 bl lowlevel_init /* go setup memory */
Wolfgang Denk74f43042005-09-25 01:48:28 +020098 mov lr, ip /* restore link */
Simon Glassb5bd0982016-05-05 07:28:06 -060099#endif
Wolfgang Denk74f43042005-09-25 01:48:28 +0200100 mov pc, lr /* back to my caller */
Jean-Christophe PLAGNIOL-VILLARD8fc3bb42009-05-15 23:45:20 +0200101#endif