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Lokesh Vutlafbf27282013-07-30 11:36:27 +05301/*
2 * board.c
3 *
4 * Board functions for TI AM43XX based boards
5 *
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
Sekhar Nori9f1a8cd2013-12-10 15:02:15 +053012#include <i2c.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090013#include <linux/errno.h>
Lokesh Vutlafbf27282013-07-30 11:36:27 +053014#include <spl.h>
Kishon Vijay Abraham I9f81eb72015-02-23 18:40:21 +053015#include <usb.h>
Madan Srinivase29878f2016-06-27 09:19:23 -050016#include <asm/omap_sec_common.h>
Lokesh Vutla3b34ac12013-07-30 11:36:29 +053017#include <asm/arch/clock.h>
Lokesh Vutlafbf27282013-07-30 11:36:27 +053018#include <asm/arch/sys_proto.h>
19#include <asm/arch/mux.h>
Lokesh Vutlad3daba12013-12-10 15:02:22 +053020#include <asm/arch/ddr_defs.h>
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +053021#include <asm/arch/gpio.h>
Lokesh Vutlad3daba12013-12-10 15:02:22 +053022#include <asm/emif.h>
Nishanth Menon5f8bb932016-02-24 12:30:56 -060023#include "../common/board_detect.h"
Lokesh Vutlafbf27282013-07-30 11:36:27 +053024#include "board.h"
Tom Rini7aa55982014-06-23 16:06:29 -040025#include <power/pmic.h>
Tom Rini83bad102014-06-05 11:15:30 -040026#include <power/tps65218.h>
Felipe Balbi403d70a2014-12-22 16:26:17 -060027#include <power/tps62362.h>
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -050028#include <miiphy.h>
29#include <cpsw.h>
Kishon Vijay Abraham I9f81eb72015-02-23 18:40:21 +053030#include <linux/usb/gadget.h>
31#include <dwc3-uboot.h>
32#include <dwc3-omap-uboot.h>
33#include <ti-usb-phy-uboot.h>
Lokesh Vutlafbf27282013-07-30 11:36:27 +053034
35DECLARE_GLOBAL_DATA_PTR;
36
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -050037static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -050038
Sekhar Nori9f1a8cd2013-12-10 15:02:15 +053039/*
40 * Read header information from EEPROM into global structure.
41 */
Lokesh Vutla140d76a2016-10-14 10:35:25 +053042#ifdef CONFIG_TI_I2C_BOARD_DETECT
43void do_board_detect(void)
Sekhar Nori9f1a8cd2013-12-10 15:02:15 +053044{
Lokesh Vutla140d76a2016-10-14 10:35:25 +053045 if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR))
46 printf("ti_i2c_eeprom_init failed\n");
Sekhar Nori9f1a8cd2013-12-10 15:02:15 +053047}
Lokesh Vutla140d76a2016-10-14 10:35:25 +053048#endif
Sekhar Nori9f1a8cd2013-12-10 15:02:15 +053049
Sourav Poddar7a5f71b2014-05-19 16:53:37 -040050#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Lokesh Vutlafbf27282013-07-30 11:36:27 +053051
Lokesh Vutlacf04d032013-12-10 15:02:20 +053052#define NUM_OPPS 6
53
54const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
55 { /* 19.2 MHz */
James Doublesine2a62072014-12-22 16:26:10 -060056 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
Lokesh Vutlacf04d032013-12-10 15:02:20 +053057 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
James Doublesine2a62072014-12-22 16:26:10 -060058 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
59 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
60 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
61 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
Lokesh Vutlacf04d032013-12-10 15:02:20 +053062 },
63 { /* 24 MHz */
64 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
65 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
66 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
67 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
68 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
69 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
70 },
71 { /* 25 MHz */
72 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
73 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
74 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
75 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
76 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
77 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
78 },
79 { /* 26 MHz */
80 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
81 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
82 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
83 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
84 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
85 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
86 },
87};
88
89const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
James Doublesine2a62072014-12-22 16:26:10 -060090 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
Lokesh Vutlacf04d032013-12-10 15:02:20 +053091 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
92 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
93 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
94};
95
96const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
James Doublesine2a62072014-12-22 16:26:10 -060097 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
98 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
James Doublesinc87b6a92014-12-22 16:26:12 -060099 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
James Doublesine2a62072014-12-22 16:26:10 -0600100 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
Lokesh Vutlacf04d032013-12-10 15:02:20 +0530101};
102
James Doublesine2a62072014-12-22 16:26:10 -0600103const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {
104 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/
105 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */
106 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
107 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
108};
Lokesh Vutlacf04d032013-12-10 15:02:20 +0530109
110const struct dpll_params gp_evm_dpll_ddr = {
James Doublesine2a62072014-12-22 16:26:10 -0600111 50, 2, 1, -1, 2, -1, -1};
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530112
Felipe Balbi403d70a2014-12-22 16:26:17 -0600113static const struct dpll_params idk_dpll_ddr = {
114 400, 23, 1, -1, 2, -1, -1
115};
116
Tom Rini7c352cd2015-06-05 15:51:11 +0530117static const u32 ext_phy_ctrl_const_base_lpddr2[] = {
118 0x00500050,
119 0x00350035,
120 0x00350035,
121 0x00350035,
122 0x00350035,
123 0x00350035,
124 0x00000000,
125 0x00000000,
126 0x00000000,
127 0x00000000,
128 0x00000000,
129 0x00000000,
130 0x00000000,
131 0x00000000,
132 0x00000000,
133 0x00000000,
134 0x00000000,
135 0x00000000,
136 0x40001000,
137 0x08102040
138};
139
Lokesh Vutlad3daba12013-12-10 15:02:22 +0530140const struct ctrl_ioregs ioregs_lpddr2 = {
141 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
142 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
143 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
144 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
145 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
146 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
147 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
148 .emif_sdram_config_ext = 0x1,
149};
150
151const struct emif_regs emif_regs_lpddr2 = {
152 .sdram_config = 0x808012BA,
153 .ref_ctrl = 0x0000040D,
154 .sdram_tim1 = 0xEA86B411,
155 .sdram_tim2 = 0x103A094A,
156 .sdram_tim3 = 0x0F6BA37F,
157 .read_idle_ctrl = 0x00050000,
158 .zq_config = 0x50074BE4,
159 .temp_alert_config = 0x0,
160 .emif_rd_wr_lvl_rmp_win = 0x0,
161 .emif_rd_wr_lvl_rmp_ctl = 0x0,
162 .emif_rd_wr_lvl_ctl = 0x0,
James Doublesine2a62072014-12-22 16:26:10 -0600163 .emif_ddr_phy_ctlr_1 = 0x0E284006,
Cooper Jr., Franklin8038b492014-06-27 13:31:15 -0500164 .emif_rd_wr_exec_thresh = 0x80000405,
Lokesh Vutlad3daba12013-12-10 15:02:22 +0530165 .emif_ddr_ext_phy_ctrl_1 = 0x04010040,
166 .emif_ddr_ext_phy_ctrl_2 = 0x00500050,
167 .emif_ddr_ext_phy_ctrl_3 = 0x00500050,
168 .emif_ddr_ext_phy_ctrl_4 = 0x00500050,
Cooper Jr., Franklin8038b492014-06-27 13:31:15 -0500169 .emif_ddr_ext_phy_ctrl_5 = 0x00500050,
170 .emif_prio_class_serv_map = 0x80000001,
171 .emif_connect_id_serv_1_map = 0x80000094,
172 .emif_connect_id_serv_2_map = 0x00000000,
173 .emif_cos_config = 0x000FFFFF
Lokesh Vutlad3daba12013-12-10 15:02:22 +0530174};
175
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530176const struct ctrl_ioregs ioregs_ddr3 = {
177 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
178 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
179 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
180 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
181 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
182 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
183 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
James Doublesine2a62072014-12-22 16:26:10 -0600184 .emif_sdram_config_ext = 0xc163,
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530185};
186
187const struct emif_regs ddr3_emif_regs_400Mhz = {
188 .sdram_config = 0x638413B2,
189 .ref_ctrl = 0x00000C30,
190 .sdram_tim1 = 0xEAAAD4DB,
191 .sdram_tim2 = 0x266B7FDA,
192 .sdram_tim3 = 0x107F8678,
193 .read_idle_ctrl = 0x00050000,
194 .zq_config = 0x50074BE4,
195 .temp_alert_config = 0x0,
Lokesh Vutlae27f2dd2014-02-18 07:31:57 -0500196 .emif_ddr_phy_ctlr_1 = 0x0E004008,
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530197 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
198 .emif_ddr_ext_phy_ctrl_2 = 0x00400040,
199 .emif_ddr_ext_phy_ctrl_3 = 0x00400040,
200 .emif_ddr_ext_phy_ctrl_4 = 0x00400040,
201 .emif_ddr_ext_phy_ctrl_5 = 0x00400040,
202 .emif_rd_wr_lvl_rmp_win = 0x0,
203 .emif_rd_wr_lvl_rmp_ctl = 0x0,
204 .emif_rd_wr_lvl_ctl = 0x0,
Cooper Jr., Franklin8038b492014-06-27 13:31:15 -0500205 .emif_rd_wr_exec_thresh = 0x80000405,
206 .emif_prio_class_serv_map = 0x80000001,
207 .emif_connect_id_serv_1_map = 0x80000094,
208 .emif_connect_id_serv_2_map = 0x00000000,
209 .emif_cos_config = 0x000FFFFF
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530210};
211
Franklin S. Cooper Jr2c952112014-06-27 13:31:14 -0500212/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
213const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
214 .sdram_config = 0x638413B2,
215 .ref_ctrl = 0x00000C30,
216 .sdram_tim1 = 0xEAAAD4DB,
217 .sdram_tim2 = 0x266B7FDA,
218 .sdram_tim3 = 0x107F8678,
219 .read_idle_ctrl = 0x00050000,
220 .zq_config = 0x50074BE4,
221 .temp_alert_config = 0x0,
222 .emif_ddr_phy_ctlr_1 = 0x0E004008,
223 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
224 .emif_ddr_ext_phy_ctrl_2 = 0x00000065,
225 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
226 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5,
227 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5,
Cooper Jr., Franklin8038b492014-06-27 13:31:15 -0500228 .emif_rd_wr_exec_thresh = 0x80000405,
229 .emif_prio_class_serv_map = 0x80000001,
230 .emif_connect_id_serv_1_map = 0x80000094,
231 .emif_connect_id_serv_2_map = 0x00000000,
232 .emif_cos_config = 0x000FFFFF
Franklin S. Cooper Jr2c952112014-06-27 13:31:14 -0500233};
234
235/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
236const struct emif_regs ddr3_emif_regs_400Mhz_production = {
237 .sdram_config = 0x638413B2,
238 .ref_ctrl = 0x00000C30,
239 .sdram_tim1 = 0xEAAAD4DB,
240 .sdram_tim2 = 0x266B7FDA,
241 .sdram_tim3 = 0x107F8678,
242 .read_idle_ctrl = 0x00050000,
243 .zq_config = 0x50074BE4,
244 .temp_alert_config = 0x0,
245 .emif_ddr_phy_ctlr_1 = 0x0E004008,
246 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
247 .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
248 .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
249 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
250 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
Cooper Jr., Franklin8038b492014-06-27 13:31:15 -0500251 .emif_rd_wr_exec_thresh = 0x80000405,
252 .emif_prio_class_serv_map = 0x80000001,
253 .emif_connect_id_serv_1_map = 0x80000094,
254 .emif_connect_id_serv_2_map = 0x00000000,
255 .emif_cos_config = 0x000FFFFF
Franklin S. Cooper Jr2c952112014-06-27 13:31:14 -0500256};
257
Felipe Balbi9cb9f332014-06-10 15:01:20 -0500258static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
259 .sdram_config = 0x638413b2,
260 .sdram_config2 = 0x00000000,
261 .ref_ctrl = 0x00000c30,
262 .sdram_tim1 = 0xeaaad4db,
263 .sdram_tim2 = 0x266b7fda,
264 .sdram_tim3 = 0x107f8678,
265 .read_idle_ctrl = 0x00050000,
266 .zq_config = 0x50074be4,
267 .temp_alert_config = 0x0,
268 .emif_ddr_phy_ctlr_1 = 0x0e084008,
269 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
270 .emif_ddr_ext_phy_ctrl_2 = 0x89,
271 .emif_ddr_ext_phy_ctrl_3 = 0x90,
272 .emif_ddr_ext_phy_ctrl_4 = 0x8e,
273 .emif_ddr_ext_phy_ctrl_5 = 0x8d,
274 .emif_rd_wr_lvl_rmp_win = 0x0,
275 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
276 .emif_rd_wr_lvl_ctl = 0x00000000,
Cooper Jr., Franklin8038b492014-06-27 13:31:15 -0500277 .emif_rd_wr_exec_thresh = 0x80000000,
278 .emif_prio_class_serv_map = 0x80000001,
279 .emif_connect_id_serv_1_map = 0x80000094,
280 .emif_connect_id_serv_2_map = 0x00000000,
281 .emif_cos_config = 0x000FFFFF
Felipe Balbi9cb9f332014-06-10 15:01:20 -0500282};
283
Felipe Balbi403d70a2014-12-22 16:26:17 -0600284static const struct emif_regs ddr3_idk_emif_regs_400Mhz = {
285 .sdram_config = 0x61a11b32,
286 .sdram_config2 = 0x00000000,
287 .ref_ctrl = 0x00000c30,
288 .sdram_tim1 = 0xeaaad4db,
289 .sdram_tim2 = 0x266b7fda,
290 .sdram_tim3 = 0x107f8678,
291 .read_idle_ctrl = 0x00050000,
292 .zq_config = 0x50074be4,
293 .temp_alert_config = 0x00000000,
294 .emif_ddr_phy_ctlr_1 = 0x00008009,
295 .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
296 .emif_ddr_ext_phy_ctrl_2 = 0x00000040,
297 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e,
298 .emif_ddr_ext_phy_ctrl_4 = 0x00000051,
299 .emif_ddr_ext_phy_ctrl_5 = 0x00000051,
300 .emif_rd_wr_lvl_rmp_win = 0x00000000,
301 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
302 .emif_rd_wr_lvl_ctl = 0x00000000,
303 .emif_rd_wr_exec_thresh = 0x00000405,
304 .emif_prio_class_serv_map = 0x00000000,
305 .emif_connect_id_serv_1_map = 0x00000000,
306 .emif_connect_id_serv_2_map = 0x00000000,
307 .emif_cos_config = 0x00ffffff
308};
309
Tom Rini7c352cd2015-06-05 15:51:11 +0530310void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
311{
312 if (board_is_eposevm()) {
313 *regs = ext_phy_ctrl_const_base_lpddr2;
314 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
315 }
316
317 return;
318}
319
Lokesh Vutlacf04d032013-12-10 15:02:20 +0530320/*
321 * get_sys_clk_index : returns the index of the sys_clk read from
322 * ctrl status register. This value is either
323 * read from efuse or sysboot pins.
324 */
325static u32 get_sys_clk_index(void)
326{
327 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
328 u32 ind = readl(&ctrl->statusreg), src;
329
330 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
331 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
332 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
333 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
334 else /* Value read from SYS BOOT pins */
335 return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
336 CTRL_SYSBOOT_15_14_SHIFT);
337}
338
James Doublesine2a62072014-12-22 16:26:10 -0600339const struct dpll_params *get_dpll_ddr_params(void)
340{
341 int ind = get_sys_clk_index();
342
343 if (board_is_eposevm())
344 return &epos_evm_dpll_ddr[ind];
Madan Srinivasa5051b72016-05-19 19:10:48 -0500345 else if (board_is_evm() || board_is_sk())
James Doublesine2a62072014-12-22 16:26:10 -0600346 return &gp_evm_dpll_ddr;
Felipe Balbi403d70a2014-12-22 16:26:17 -0600347 else if (board_is_idk())
348 return &idk_dpll_ddr;
James Doublesine2a62072014-12-22 16:26:10 -0600349
Nishanth Menon5f8bb932016-02-24 12:30:56 -0600350 printf(" Board '%s' not supported\n", board_ti_get_name());
James Doublesine2a62072014-12-22 16:26:10 -0600351 return NULL;
352}
353
354
Lokesh Vutlacf04d032013-12-10 15:02:20 +0530355/*
356 * get_opp_offset:
357 * Returns the index for safest OPP of the device to boot.
358 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
359 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
360 * This data is read from dev_attribute register which is e-fused.
361 * A'1' in bit indicates OPP disabled and not available, a '0' indicates
362 * OPP available. Lowest OPP starts with min_off. So returning the
363 * bit with rightmost '0'.
364 */
365static int get_opp_offset(int max_off, int min_off)
366{
367 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
Tom Rinifeca6e62014-06-05 11:15:27 -0400368 int opp, offset, i;
369
370 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
371 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
Lokesh Vutlacf04d032013-12-10 15:02:20 +0530372
373 for (i = max_off; i >= min_off; i--) {
374 offset = opp & (1 << i);
375 if (!offset)
376 return i;
377 }
378
379 return min_off;
380}
381
382const struct dpll_params *get_dpll_mpu_params(void)
383{
384 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
385 u32 ind = get_sys_clk_index();
386
387 return &dpll_mpu[ind][opp];
388}
389
390const struct dpll_params *get_dpll_core_params(void)
391{
392 int ind = get_sys_clk_index();
393
394 return &dpll_core[ind];
395}
396
397const struct dpll_params *get_dpll_per_params(void)
398{
399 int ind = get_sys_clk_index();
400
401 return &dpll_per[ind];
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530402}
403
Felipe Balbi403d70a2014-12-22 16:26:17 -0600404void scale_vcores_generic(u32 m)
Tom Rini83bad102014-06-05 11:15:30 -0400405{
Tom Rini83bad102014-06-05 11:15:30 -0400406 int mpu_vdd;
Tom Rini83bad102014-06-05 11:15:30 -0400407
408 if (i2c_probe(TPS65218_CHIP_PM))
409 return;
410
Felipe Balbi403d70a2014-12-22 16:26:17 -0600411 switch (m) {
Felipe Balbi068ea0a2014-12-22 16:26:13 -0600412 case 1000:
Tom Rini83bad102014-06-05 11:15:30 -0400413 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
Felipe Balbi068ea0a2014-12-22 16:26:13 -0600414 break;
Felipe Balbid5c082a2014-12-22 16:26:15 -0600415 case 800:
416 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV;
417 break;
418 case 720:
419 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV;
420 break;
Felipe Balbi068ea0a2014-12-22 16:26:13 -0600421 case 600:
Tom Rini83bad102014-06-05 11:15:30 -0400422 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
Felipe Balbi068ea0a2014-12-22 16:26:13 -0600423 break;
Felipe Balbid5c082a2014-12-22 16:26:15 -0600424 case 300:
425 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV;
426 break;
Felipe Balbi068ea0a2014-12-22 16:26:13 -0600427 default:
Tom Rini83bad102014-06-05 11:15:30 -0400428 puts("Unknown MPU clock, not scaling\n");
429 return;
430 }
431
432 /* Set DCDC1 (CORE) voltage to 1.1V */
433 if (tps65218_voltage_update(TPS65218_DCDC1,
434 TPS65218_DCDC_VOLT_SEL_1100MV)) {
Felipe Balbi403d70a2014-12-22 16:26:17 -0600435 printf("%s failure\n", __func__);
Tom Rini83bad102014-06-05 11:15:30 -0400436 return;
437 }
438
439 /* Set DCDC2 (MPU) voltage */
440 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
Felipe Balbi403d70a2014-12-22 16:26:17 -0600441 printf("%s failure\n", __func__);
Tom Rini83bad102014-06-05 11:15:30 -0400442 return;
443 }
444}
445
Felipe Balbi403d70a2014-12-22 16:26:17 -0600446void scale_vcores_idk(u32 m)
447{
448 int mpu_vdd;
449
450 if (i2c_probe(TPS62362_I2C_ADDR))
451 return;
452
453 switch (m) {
454 case 1000:
455 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
456 break;
457 case 800:
458 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV;
459 break;
460 case 720:
461 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV;
462 break;
463 case 600:
464 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV;
465 break;
466 case 300:
467 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV;
468 break;
469 default:
470 puts("Unknown MPU clock, not scaling\n");
471 return;
472 }
473
474 /* Set VDD_MPU voltage */
475 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) {
476 printf("%s failure\n", __func__);
477 return;
478 }
479}
480
Nishanth Menon5f8bb932016-02-24 12:30:56 -0600481void gpi2c_init(void)
482{
483 /* When needed to be invoked prior to BSS initialization */
484 static bool first_time = true;
485
486 if (first_time) {
487 enable_i2c0_pin_mux();
488 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
489 CONFIG_SYS_OMAP24_I2C_SLAVE);
490 first_time = false;
491 }
492}
493
Felipe Balbi403d70a2014-12-22 16:26:17 -0600494void scale_vcores(void)
495{
496 const struct dpll_params *mpu_params;
Felipe Balbi403d70a2014-12-22 16:26:17 -0600497
Nishanth Menon5f8bb932016-02-24 12:30:56 -0600498 /* Ensure I2C is initialized for PMIC configuration */
499 gpi2c_init();
500
Felipe Balbi403d70a2014-12-22 16:26:17 -0600501 /* Get the frequency */
502 mpu_params = get_dpll_mpu_params();
503
504 if (board_is_idk())
505 scale_vcores_idk(mpu_params->m);
506 else
507 scale_vcores_generic(mpu_params->m);
508}
509
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530510void set_uart_mux_conf(void)
511{
512 enable_uart0_pin_mux();
513}
514
515void set_mux_conf_regs(void)
516{
517 enable_board_pin_mux();
518}
519
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530520static void enable_vtt_regulator(void)
521{
522 u32 temp;
523
524 /* enable module */
Dave Gerlachcd8341b2014-02-10 11:41:49 -0500525 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530526
Dave Gerlachcd8341b2014-02-10 11:41:49 -0500527 /* enable output for GPIO5_7 */
528 writel(GPIO_SETDATAOUT(7),
529 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
530 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
531 temp = temp & ~(GPIO_OE_ENABLE(7));
532 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530533}
534
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530535void sdram_init(void)
536{
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530537 /*
538 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
539 * GP EMV has 1GB DDR3 connected to EMIF
540 * along with VTT regulator.
541 */
542 if (board_is_eposevm()) {
543 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
Franklin S. Cooper Jr2c952112014-06-27 13:31:14 -0500544 } else if (board_is_evm_14_or_later()) {
545 enable_vtt_regulator();
546 config_ddr(0, &ioregs_ddr3, NULL, NULL,
547 &ddr3_emif_regs_400Mhz_production, 0);
548 } else if (board_is_evm_12_or_later()) {
549 enable_vtt_regulator();
550 config_ddr(0, &ioregs_ddr3, NULL, NULL,
551 &ddr3_emif_regs_400Mhz_beta, 0);
Madan Srinivasa5051b72016-05-19 19:10:48 -0500552 } else if (board_is_evm()) {
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530553 enable_vtt_regulator();
554 config_ddr(0, &ioregs_ddr3, NULL, NULL,
555 &ddr3_emif_regs_400Mhz, 0);
Felipe Balbi9cb9f332014-06-10 15:01:20 -0500556 } else if (board_is_sk()) {
557 config_ddr(400, &ioregs_ddr3, NULL, NULL,
558 &ddr3_sk_emif_regs_400Mhz, 0);
Felipe Balbi403d70a2014-12-22 16:26:17 -0600559 } else if (board_is_idk()) {
560 config_ddr(400, &ioregs_ddr3, NULL, NULL,
561 &ddr3_idk_emif_regs_400Mhz, 0);
Lokesh Vutlab5e01ee2013-12-10 15:02:23 +0530562 }
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530563}
564#endif
565
Tom Rini7aa55982014-06-23 16:06:29 -0400566/* setup board specific PMIC */
567int power_init_board(void)
568{
569 struct pmic *p;
570
Felipe Balbi403d70a2014-12-22 16:26:17 -0600571 if (board_is_idk()) {
572 power_tps62362_init(I2C_PMIC);
573 p = pmic_get("TPS62362");
574 if (p && !pmic_probe(p))
575 puts("PMIC: TPS62362\n");
576 } else {
577 power_tps65218_init(I2C_PMIC);
578 p = pmic_get("TPS65218_PMIC");
579 if (p && !pmic_probe(p))
580 puts("PMIC: TPS65218\n");
581 }
Tom Rini7aa55982014-06-23 16:06:29 -0400582
583 return 0;
584}
585
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530586int board_init(void)
587{
Cooper Jr., Franklin8038b492014-06-27 13:31:15 -0500588 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
589 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
590 modena_init0_bw_integer, modena_init0_watermark_0;
591
Lokesh Vutla369cbe12013-12-10 15:02:12 +0530592 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
pekon guptae53ad4b2014-07-22 16:03:22 +0530593 gpmc_init();
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530594
Cooper Jr., Franklin8038b492014-06-27 13:31:15 -0500595 /* Clear all important bits for DSS errata that may need to be tweaked*/
596 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
597 MREQPRIO_0_SAB_INIT0_MASK;
598
599 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
600
601 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
602 BW_LIMITER_BW_FRAC_MASK;
603
604 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
605 BW_LIMITER_BW_INT_MASK;
606
607 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
608 BW_LIMITER_BW_WATERMARK_MASK;
609
610 /* Setting MReq Priority of the DSS*/
611 mreqprio_0 |= 0x77;
612
613 /*
614 * Set L3 Fast Configuration Register
615 * Limiting bandwith for ARM core to 700 MBPS
616 */
617 modena_init0_bw_fractional |= 0x10;
618 modena_init0_bw_integer |= 0x3;
619
620 writel(mreqprio_0, &cdev->mreqprio_0);
621 writel(mreqprio_1, &cdev->mreqprio_1);
622
623 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
624 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
625 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
626
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530627 return 0;
628}
629
630#ifdef CONFIG_BOARD_LATE_INIT
631int board_late_init(void)
632{
Sekhar Norif4af1632013-12-10 15:02:16 +0530633#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Nishanth Menon5f8bb932016-02-24 12:30:56 -0600634 set_board_info_env(NULL);
Lokesh Vutla5d4d4362016-11-29 11:58:03 +0530635
636 /*
637 * Default FIT boot on HS devices. Non FIT images are not allowed
638 * on HS devices.
639 */
640 if (get_device_type() == HS_DEVICE)
641 setenv("boot_fit", "1");
Sekhar Norif4af1632013-12-10 15:02:16 +0530642#endif
Lokesh Vutlafbf27282013-07-30 11:36:27 +0530643 return 0;
644}
645#endif
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500646
Kishon Vijay Abraham I9f81eb72015-02-23 18:40:21 +0530647#ifdef CONFIG_USB_DWC3
648static struct dwc3_device usb_otg_ss1 = {
649 .maximum_speed = USB_SPEED_HIGH,
650 .base = USB_OTG_SS1_BASE,
651 .tx_fifo_resize = false,
652 .index = 0,
653};
654
655static struct dwc3_omap_device usb_otg_ss1_glue = {
656 .base = (void *)USB_OTG_SS1_GLUE_BASE,
657 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
Kishon Vijay Abraham I9f81eb72015-02-23 18:40:21 +0530658 .index = 0,
659};
660
661static struct ti_usb_phy_device usb_phy1_device = {
662 .usb2_phy_power = (void *)USB2_PHY1_POWER,
663 .index = 0,
664};
665
666static struct dwc3_device usb_otg_ss2 = {
667 .maximum_speed = USB_SPEED_HIGH,
668 .base = USB_OTG_SS2_BASE,
669 .tx_fifo_resize = false,
670 .index = 1,
671};
672
673static struct dwc3_omap_device usb_otg_ss2_glue = {
674 .base = (void *)USB_OTG_SS2_GLUE_BASE,
675 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
Kishon Vijay Abraham I9f81eb72015-02-23 18:40:21 +0530676 .index = 1,
677};
678
679static struct ti_usb_phy_device usb_phy2_device = {
680 .usb2_phy_power = (void *)USB2_PHY2_POWER,
681 .index = 1,
682};
683
Kishon Vijay Abraham I2d48aa62015-02-23 18:40:23 +0530684int usb_gadget_handle_interrupts(int index)
Kishon Vijay Abraham I9f81eb72015-02-23 18:40:21 +0530685{
686 u32 status;
687
Kishon Vijay Abraham I2d48aa62015-02-23 18:40:23 +0530688 status = dwc3_omap_uboot_interrupt_status(index);
Kishon Vijay Abraham I9f81eb72015-02-23 18:40:21 +0530689 if (status)
Kishon Vijay Abraham I2d48aa62015-02-23 18:40:23 +0530690 dwc3_uboot_handle_interrupt(index);
Kishon Vijay Abraham I9f81eb72015-02-23 18:40:21 +0530691
692 return 0;
693}
Roger Quadros55efadd2016-05-23 17:37:48 +0300694#endif /* CONFIG_USB_DWC3 */
695
696#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
697int board_usb_init(int index, enum usb_init_type init)
698{
699 enable_usb_clocks(index);
700#ifdef CONFIG_USB_DWC3
701 switch (index) {
702 case 0:
703 if (init == USB_INIT_DEVICE) {
704 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
705 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
706 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
707 ti_usb_phy_uboot_init(&usb_phy1_device);
708 dwc3_uboot_init(&usb_otg_ss1);
709 }
710 break;
711 case 1:
712 if (init == USB_INIT_DEVICE) {
713 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
714 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
715 ti_usb_phy_uboot_init(&usb_phy2_device);
716 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
717 dwc3_uboot_init(&usb_otg_ss2);
718 }
719 break;
720 default:
721 printf("Invalid Controller Index\n");
722 }
Kishon Vijay Abraham I9f81eb72015-02-23 18:40:21 +0530723#endif
724
Roger Quadros55efadd2016-05-23 17:37:48 +0300725 return 0;
726}
727
728int board_usb_cleanup(int index, enum usb_init_type init)
729{
730#ifdef CONFIG_USB_DWC3
731 switch (index) {
732 case 0:
733 case 1:
734 if (init == USB_INIT_DEVICE) {
735 ti_usb_phy_uboot_exit(index);
736 dwc3_uboot_exit(index);
737 dwc3_omap_uboot_exit(index);
738 }
739 break;
740 default:
741 printf("Invalid Controller Index\n");
742 }
743#endif
744 disable_usb_clocks(index);
745
746 return 0;
747}
748#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
749
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500750#ifdef CONFIG_DRIVER_TI_CPSW
751
752static void cpsw_control(int enabled)
753{
754 /* Additional controls can be added here */
755 return;
756}
757
758static struct cpsw_slave_data cpsw_slaves[] = {
759 {
760 .slave_reg_ofs = 0x208,
761 .sliver_reg_ofs = 0xd80,
762 .phy_addr = 16,
763 },
764 {
765 .slave_reg_ofs = 0x308,
766 .sliver_reg_ofs = 0xdc0,
767 .phy_addr = 1,
768 },
769};
770
771static struct cpsw_platform_data cpsw_data = {
772 .mdio_base = CPSW_MDIO_BASE,
773 .cpsw_base = CPSW_BASE,
774 .mdio_div = 0xff,
775 .channels = 8,
776 .cpdma_reg_ofs = 0x800,
777 .slaves = 1,
778 .slave_data = cpsw_slaves,
779 .ale_reg_ofs = 0xd00,
780 .ale_entries = 1024,
781 .host_port_reg_ofs = 0x108,
782 .hw_stats_reg_ofs = 0x900,
783 .bd_ram_ofs = 0x2000,
784 .mac_control = (1 << 5),
785 .control = cpsw_control,
786 .host_port_num = 0,
787 .version = CPSW_CTRL_VERSION_2,
788};
789
790int board_eth_init(bd_t *bis)
791{
792 int rv;
793 uint8_t mac_addr[6];
794 uint32_t mac_hi, mac_lo;
795
796 /* try reading mac address from efuse */
797 mac_lo = readl(&cdev->macid0l);
798 mac_hi = readl(&cdev->macid0h);
799 mac_addr[0] = mac_hi & 0xFF;
800 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
801 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
802 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
803 mac_addr[4] = mac_lo & 0xFF;
804 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
805
806 if (!getenv("ethaddr")) {
807 puts("<ethaddr> not set. Validating first E-fuse MAC\n");
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500808 if (is_valid_ethaddr(mac_addr))
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500809 eth_setenv_enetaddr("ethaddr", mac_addr);
810 }
811
812 mac_lo = readl(&cdev->macid1l);
813 mac_hi = readl(&cdev->macid1h);
814 mac_addr[0] = mac_hi & 0xFF;
815 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
816 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
817 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
818 mac_addr[4] = mac_lo & 0xFF;
819 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
820
821 if (!getenv("eth1addr")) {
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500822 if (is_valid_ethaddr(mac_addr))
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500823 eth_setenv_enetaddr("eth1addr", mac_addr);
824 }
825
826 if (board_is_eposevm()) {
827 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
828 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
829 cpsw_slaves[0].phy_addr = 16;
Felipe Balbi619ce622014-06-10 15:01:21 -0500830 } else if (board_is_sk()) {
831 writel(RGMII_MODE_ENABLE, &cdev->miisel);
832 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
833 cpsw_slaves[0].phy_addr = 4;
834 cpsw_slaves[1].phy_addr = 5;
Felipe Balbi403d70a2014-12-22 16:26:17 -0600835 } else if (board_is_idk()) {
836 writel(RGMII_MODE_ENABLE, &cdev->miisel);
837 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
838 cpsw_slaves[0].phy_addr = 0;
Mugunthan V N4cdd7fd2014-02-18 07:31:54 -0500839 } else {
840 writel(RGMII_MODE_ENABLE, &cdev->miisel);
841 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
842 cpsw_slaves[0].phy_addr = 0;
843 }
844
845 rv = cpsw_register(&cpsw_data);
846 if (rv < 0)
847 printf("Error %d registering CPSW switch\n", rv);
848
849 return rv;
850}
851#endif
Lokesh Vutla5a3775a2016-05-16 11:11:15 +0530852
853#ifdef CONFIG_SPL_LOAD_FIT
854int board_fit_config_name_match(const char *name)
855{
Lokesh Vutla17361212016-06-10 10:44:47 +0530856 if (board_is_evm() && !strcmp(name, "am437x-gp-evm"))
Lokesh Vutla5a3775a2016-05-16 11:11:15 +0530857 return 0;
858 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
859 return 0;
Lokesh Vutla7dd12832016-05-16 11:11:17 +0530860 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
861 return 0;
Lokesh Vutla54a92e12016-05-16 11:11:18 +0530862 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
863 return 0;
Lokesh Vutla5a3775a2016-05-16 11:11:15 +0530864 else
865 return -1;
866}
867#endif
Madan Srinivase29878f2016-06-27 09:19:23 -0500868
869#ifdef CONFIG_TI_SECURE_DEVICE
870void board_fit_image_post_process(void **p_image, size_t *p_size)
871{
872 secure_boot_verify_image(p_image, p_size);
873}
874#endif