Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 1 | /* |
| 2 | * board.c |
| 3 | * |
| 4 | * Board functions for TI AM43XX based boards |
| 5 | * |
| 6 | * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
Sekhar Nori | 9f1a8cd | 2013-12-10 15:02:15 +0530 | [diff] [blame] | 12 | #include <i2c.h> |
| 13 | #include <asm/errno.h> |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 14 | #include <spl.h> |
Lokesh Vutla | 3b34ac1 | 2013-07-30 11:36:29 +0530 | [diff] [blame] | 15 | #include <asm/arch/clock.h> |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 16 | #include <asm/arch/sys_proto.h> |
| 17 | #include <asm/arch/mux.h> |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 18 | #include <asm/arch/ddr_defs.h> |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 19 | #include <asm/arch/gpio.h> |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 20 | #include <asm/emif.h> |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 21 | #include "board.h" |
Tom Rini | 7aa5598 | 2014-06-23 16:06:29 -0400 | [diff] [blame] | 22 | #include <power/pmic.h> |
Tom Rini | 83bad10 | 2014-06-05 11:15:30 -0400 | [diff] [blame] | 23 | #include <power/tps65218.h> |
Mugunthan V N | 4cdd7fd | 2014-02-18 07:31:54 -0500 | [diff] [blame] | 24 | #include <miiphy.h> |
| 25 | #include <cpsw.h> |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
Mugunthan V N | 4cdd7fd | 2014-02-18 07:31:54 -0500 | [diff] [blame] | 29 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; |
Mugunthan V N | 4cdd7fd | 2014-02-18 07:31:54 -0500 | [diff] [blame] | 30 | |
Sekhar Nori | 9f1a8cd | 2013-12-10 15:02:15 +0530 | [diff] [blame] | 31 | /* |
| 32 | * Read header information from EEPROM into global structure. |
| 33 | */ |
| 34 | static int read_eeprom(struct am43xx_board_id *header) |
| 35 | { |
| 36 | /* Check if baseboard eeprom is available */ |
| 37 | if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { |
| 38 | printf("Could not probe the EEPROM at 0x%x\n", |
| 39 | CONFIG_SYS_I2C_EEPROM_ADDR); |
| 40 | return -ENODEV; |
| 41 | } |
| 42 | |
| 43 | /* read the eeprom using i2c */ |
| 44 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, |
| 45 | sizeof(struct am43xx_board_id))) { |
| 46 | printf("Could not read the EEPROM\n"); |
| 47 | return -EIO; |
| 48 | } |
| 49 | |
| 50 | if (header->magic != 0xEE3355AA) { |
| 51 | /* |
| 52 | * read the eeprom using i2c again, |
| 53 | * but use only a 1 byte address |
| 54 | */ |
| 55 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, |
| 56 | sizeof(struct am43xx_board_id))) { |
| 57 | printf("Could not read the EEPROM at 0x%x\n", |
| 58 | CONFIG_SYS_I2C_EEPROM_ADDR); |
| 59 | return -EIO; |
| 60 | } |
| 61 | |
| 62 | if (header->magic != 0xEE3355AA) { |
| 63 | printf("Incorrect magic number (0x%x) in EEPROM\n", |
| 64 | header->magic); |
| 65 | return -EINVAL; |
| 66 | } |
| 67 | } |
| 68 | |
| 69 | strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); |
| 70 | am43xx_board_name[sizeof(header->name)] = 0; |
| 71 | |
Franklin S. Cooper Jr | 2c95211 | 2014-06-27 13:31:14 -0500 | [diff] [blame] | 72 | strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version)); |
| 73 | am43xx_board_rev[sizeof(header->version)] = 0; |
| 74 | |
Sekhar Nori | 9f1a8cd | 2013-12-10 15:02:15 +0530 | [diff] [blame] | 75 | return 0; |
| 76 | } |
| 77 | |
Sourav Poddar | 7a5f71b | 2014-05-19 16:53:37 -0400 | [diff] [blame] | 78 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 79 | |
Lokesh Vutla | cf04d03 | 2013-12-10 15:02:20 +0530 | [diff] [blame] | 80 | #define NUM_OPPS 6 |
| 81 | |
| 82 | const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { |
| 83 | { /* 19.2 MHz */ |
| 84 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */ |
| 85 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ |
| 86 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */ |
| 87 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */ |
| 88 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */ |
| 89 | {-1, -1, -1, -1, -1, -1, -1} /* OPP NT */ |
| 90 | }, |
| 91 | { /* 24 MHz */ |
| 92 | {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ |
| 93 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ |
| 94 | {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ |
| 95 | {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ |
| 96 | {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ |
| 97 | {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ |
| 98 | }, |
| 99 | { /* 25 MHz */ |
| 100 | {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ |
| 101 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ |
| 102 | {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ |
| 103 | {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ |
| 104 | {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ |
| 105 | {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ |
| 106 | }, |
| 107 | { /* 26 MHz */ |
| 108 | {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ |
| 109 | {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ |
| 110 | {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ |
| 111 | {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ |
| 112 | {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ |
| 113 | {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ |
| 114 | }, |
| 115 | }; |
| 116 | |
| 117 | const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { |
| 118 | {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 119 | {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ |
| 120 | {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ |
| 121 | {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ |
| 122 | }; |
| 123 | |
| 124 | const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { |
| 125 | {-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ |
| 126 | {960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */ |
| 127 | {960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */ |
| 128 | {960, 25, 5, -1, -1, -1, -1} /* 26 MHz */ |
| 129 | }; |
| 130 | |
| 131 | const struct dpll_params epos_evm_dpll_ddr = { |
| 132 | 266, 24, 1, -1, 1, -1, -1}; |
| 133 | |
| 134 | const struct dpll_params gp_evm_dpll_ddr = { |
| 135 | 400, 23, 1, -1, 1, -1, -1}; |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 136 | |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 137 | const struct ctrl_ioregs ioregs_lpddr2 = { |
| 138 | .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, |
| 139 | .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, |
| 140 | .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, |
| 141 | .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, |
| 142 | .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, |
| 143 | .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, |
| 144 | .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, |
| 145 | .emif_sdram_config_ext = 0x1, |
| 146 | }; |
| 147 | |
| 148 | const struct emif_regs emif_regs_lpddr2 = { |
| 149 | .sdram_config = 0x808012BA, |
| 150 | .ref_ctrl = 0x0000040D, |
| 151 | .sdram_tim1 = 0xEA86B411, |
| 152 | .sdram_tim2 = 0x103A094A, |
| 153 | .sdram_tim3 = 0x0F6BA37F, |
| 154 | .read_idle_ctrl = 0x00050000, |
| 155 | .zq_config = 0x50074BE4, |
| 156 | .temp_alert_config = 0x0, |
| 157 | .emif_rd_wr_lvl_rmp_win = 0x0, |
| 158 | .emif_rd_wr_lvl_rmp_ctl = 0x0, |
| 159 | .emif_rd_wr_lvl_ctl = 0x0, |
| 160 | .emif_ddr_phy_ctlr_1 = 0x0E084006, |
Cooper Jr., Franklin | 8038b49 | 2014-06-27 13:31:15 -0500 | [diff] [blame] | 161 | .emif_rd_wr_exec_thresh = 0x80000405, |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 162 | .emif_ddr_ext_phy_ctrl_1 = 0x04010040, |
| 163 | .emif_ddr_ext_phy_ctrl_2 = 0x00500050, |
| 164 | .emif_ddr_ext_phy_ctrl_3 = 0x00500050, |
| 165 | .emif_ddr_ext_phy_ctrl_4 = 0x00500050, |
Cooper Jr., Franklin | 8038b49 | 2014-06-27 13:31:15 -0500 | [diff] [blame] | 166 | .emif_ddr_ext_phy_ctrl_5 = 0x00500050, |
| 167 | .emif_prio_class_serv_map = 0x80000001, |
| 168 | .emif_connect_id_serv_1_map = 0x80000094, |
| 169 | .emif_connect_id_serv_2_map = 0x00000000, |
| 170 | .emif_cos_config = 0x000FFFFF |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | const u32 ext_phy_ctrl_const_base_lpddr2[] = { |
| 174 | 0x00500050, |
| 175 | 0x00350035, |
| 176 | 0x00350035, |
| 177 | 0x00350035, |
| 178 | 0x00350035, |
| 179 | 0x00350035, |
| 180 | 0x00000000, |
| 181 | 0x00000000, |
| 182 | 0x00000000, |
| 183 | 0x00000000, |
| 184 | 0x00000000, |
| 185 | 0x00000000, |
| 186 | 0x00000000, |
| 187 | 0x00000000, |
| 188 | 0x00000000, |
| 189 | 0x00000000, |
| 190 | 0x00000000, |
| 191 | 0x00000000, |
| 192 | 0x40001000, |
| 193 | 0x08102040 |
| 194 | }; |
| 195 | |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 196 | const struct ctrl_ioregs ioregs_ddr3 = { |
| 197 | .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, |
| 198 | .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, |
| 199 | .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, |
| 200 | .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, |
| 201 | .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, |
| 202 | .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, |
| 203 | .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, |
Lokesh Vutla | 0df8afd | 2013-12-19 10:00:28 +0530 | [diff] [blame] | 204 | .emif_sdram_config_ext = 0x0143, |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 205 | }; |
| 206 | |
| 207 | const struct emif_regs ddr3_emif_regs_400Mhz = { |
| 208 | .sdram_config = 0x638413B2, |
| 209 | .ref_ctrl = 0x00000C30, |
| 210 | .sdram_tim1 = 0xEAAAD4DB, |
| 211 | .sdram_tim2 = 0x266B7FDA, |
| 212 | .sdram_tim3 = 0x107F8678, |
| 213 | .read_idle_ctrl = 0x00050000, |
| 214 | .zq_config = 0x50074BE4, |
| 215 | .temp_alert_config = 0x0, |
Lokesh Vutla | e27f2dd | 2014-02-18 07:31:57 -0500 | [diff] [blame] | 216 | .emif_ddr_phy_ctlr_1 = 0x0E004008, |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 217 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 218 | .emif_ddr_ext_phy_ctrl_2 = 0x00400040, |
| 219 | .emif_ddr_ext_phy_ctrl_3 = 0x00400040, |
| 220 | .emif_ddr_ext_phy_ctrl_4 = 0x00400040, |
| 221 | .emif_ddr_ext_phy_ctrl_5 = 0x00400040, |
| 222 | .emif_rd_wr_lvl_rmp_win = 0x0, |
| 223 | .emif_rd_wr_lvl_rmp_ctl = 0x0, |
| 224 | .emif_rd_wr_lvl_ctl = 0x0, |
Cooper Jr., Franklin | 8038b49 | 2014-06-27 13:31:15 -0500 | [diff] [blame] | 225 | .emif_rd_wr_exec_thresh = 0x80000405, |
| 226 | .emif_prio_class_serv_map = 0x80000001, |
| 227 | .emif_connect_id_serv_1_map = 0x80000094, |
| 228 | .emif_connect_id_serv_2_map = 0x00000000, |
| 229 | .emif_cos_config = 0x000FFFFF |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 230 | }; |
| 231 | |
Franklin S. Cooper Jr | 2c95211 | 2014-06-27 13:31:14 -0500 | [diff] [blame] | 232 | /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ |
| 233 | const struct emif_regs ddr3_emif_regs_400Mhz_beta = { |
| 234 | .sdram_config = 0x638413B2, |
| 235 | .ref_ctrl = 0x00000C30, |
| 236 | .sdram_tim1 = 0xEAAAD4DB, |
| 237 | .sdram_tim2 = 0x266B7FDA, |
| 238 | .sdram_tim3 = 0x107F8678, |
| 239 | .read_idle_ctrl = 0x00050000, |
| 240 | .zq_config = 0x50074BE4, |
| 241 | .temp_alert_config = 0x0, |
| 242 | .emif_ddr_phy_ctlr_1 = 0x0E004008, |
| 243 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 244 | .emif_ddr_ext_phy_ctrl_2 = 0x00000065, |
| 245 | .emif_ddr_ext_phy_ctrl_3 = 0x00000091, |
| 246 | .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, |
| 247 | .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, |
Cooper Jr., Franklin | 8038b49 | 2014-06-27 13:31:15 -0500 | [diff] [blame] | 248 | .emif_rd_wr_exec_thresh = 0x80000405, |
| 249 | .emif_prio_class_serv_map = 0x80000001, |
| 250 | .emif_connect_id_serv_1_map = 0x80000094, |
| 251 | .emif_connect_id_serv_2_map = 0x00000000, |
| 252 | .emif_cos_config = 0x000FFFFF |
Franklin S. Cooper Jr | 2c95211 | 2014-06-27 13:31:14 -0500 | [diff] [blame] | 253 | }; |
| 254 | |
| 255 | /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ |
| 256 | const struct emif_regs ddr3_emif_regs_400Mhz_production = { |
| 257 | .sdram_config = 0x638413B2, |
| 258 | .ref_ctrl = 0x00000C30, |
| 259 | .sdram_tim1 = 0xEAAAD4DB, |
| 260 | .sdram_tim2 = 0x266B7FDA, |
| 261 | .sdram_tim3 = 0x107F8678, |
| 262 | .read_idle_ctrl = 0x00050000, |
| 263 | .zq_config = 0x50074BE4, |
| 264 | .temp_alert_config = 0x0, |
| 265 | .emif_ddr_phy_ctlr_1 = 0x0E004008, |
| 266 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 267 | .emif_ddr_ext_phy_ctrl_2 = 0x00000066, |
| 268 | .emif_ddr_ext_phy_ctrl_3 = 0x00000091, |
| 269 | .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, |
| 270 | .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, |
Cooper Jr., Franklin | 8038b49 | 2014-06-27 13:31:15 -0500 | [diff] [blame] | 271 | .emif_rd_wr_exec_thresh = 0x80000405, |
| 272 | .emif_prio_class_serv_map = 0x80000001, |
| 273 | .emif_connect_id_serv_1_map = 0x80000094, |
| 274 | .emif_connect_id_serv_2_map = 0x00000000, |
| 275 | .emif_cos_config = 0x000FFFFF |
Franklin S. Cooper Jr | 2c95211 | 2014-06-27 13:31:14 -0500 | [diff] [blame] | 276 | }; |
| 277 | |
Felipe Balbi | 9cb9f33 | 2014-06-10 15:01:20 -0500 | [diff] [blame] | 278 | static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { |
| 279 | .sdram_config = 0x638413b2, |
| 280 | .sdram_config2 = 0x00000000, |
| 281 | .ref_ctrl = 0x00000c30, |
| 282 | .sdram_tim1 = 0xeaaad4db, |
| 283 | .sdram_tim2 = 0x266b7fda, |
| 284 | .sdram_tim3 = 0x107f8678, |
| 285 | .read_idle_ctrl = 0x00050000, |
| 286 | .zq_config = 0x50074be4, |
| 287 | .temp_alert_config = 0x0, |
| 288 | .emif_ddr_phy_ctlr_1 = 0x0e084008, |
| 289 | .emif_ddr_ext_phy_ctrl_1 = 0x08020080, |
| 290 | .emif_ddr_ext_phy_ctrl_2 = 0x89, |
| 291 | .emif_ddr_ext_phy_ctrl_3 = 0x90, |
| 292 | .emif_ddr_ext_phy_ctrl_4 = 0x8e, |
| 293 | .emif_ddr_ext_phy_ctrl_5 = 0x8d, |
| 294 | .emif_rd_wr_lvl_rmp_win = 0x0, |
| 295 | .emif_rd_wr_lvl_rmp_ctl = 0x00000000, |
| 296 | .emif_rd_wr_lvl_ctl = 0x00000000, |
Cooper Jr., Franklin | 8038b49 | 2014-06-27 13:31:15 -0500 | [diff] [blame] | 297 | .emif_rd_wr_exec_thresh = 0x80000000, |
| 298 | .emif_prio_class_serv_map = 0x80000001, |
| 299 | .emif_connect_id_serv_1_map = 0x80000094, |
| 300 | .emif_connect_id_serv_2_map = 0x00000000, |
| 301 | .emif_cos_config = 0x000FFFFF |
Felipe Balbi | 9cb9f33 | 2014-06-10 15:01:20 -0500 | [diff] [blame] | 302 | }; |
| 303 | |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 304 | const u32 ext_phy_ctrl_const_base_ddr3[] = { |
| 305 | 0x00400040, |
| 306 | 0x00350035, |
| 307 | 0x00350035, |
| 308 | 0x00350035, |
| 309 | 0x00350035, |
| 310 | 0x00350035, |
| 311 | 0x00000000, |
| 312 | 0x00000000, |
| 313 | 0x00000000, |
| 314 | 0x00000000, |
| 315 | 0x00000000, |
| 316 | 0x00340034, |
| 317 | 0x00340034, |
| 318 | 0x00340034, |
| 319 | 0x00340034, |
| 320 | 0x00340034, |
| 321 | 0x0, |
| 322 | 0x0, |
| 323 | 0x40000000, |
| 324 | 0x08102040 |
| 325 | }; |
| 326 | |
Franklin S. Cooper Jr | 2c95211 | 2014-06-27 13:31:14 -0500 | [diff] [blame] | 327 | const u32 ext_phy_ctrl_const_base_ddr3_beta[] = { |
| 328 | 0x00000000, |
| 329 | 0x00000045, |
| 330 | 0x00000046, |
| 331 | 0x00000048, |
| 332 | 0x00000047, |
| 333 | 0x00000000, |
| 334 | 0x0000004C, |
| 335 | 0x00000070, |
| 336 | 0x00000085, |
| 337 | 0x000000A3, |
| 338 | 0x00000000, |
| 339 | 0x0000000C, |
| 340 | 0x00000030, |
| 341 | 0x00000045, |
| 342 | 0x00000063, |
| 343 | 0x00000000, |
| 344 | 0x0, |
| 345 | 0x0, |
| 346 | 0x40000000, |
| 347 | 0x08102040 |
| 348 | }; |
| 349 | |
| 350 | const u32 ext_phy_ctrl_const_base_ddr3_production[] = { |
| 351 | 0x00000000, |
| 352 | 0x00000044, |
| 353 | 0x00000044, |
| 354 | 0x00000046, |
| 355 | 0x00000046, |
| 356 | 0x00000000, |
| 357 | 0x00000059, |
| 358 | 0x00000077, |
| 359 | 0x00000093, |
| 360 | 0x000000A8, |
| 361 | 0x00000000, |
| 362 | 0x00000019, |
| 363 | 0x00000037, |
| 364 | 0x00000053, |
| 365 | 0x00000068, |
| 366 | 0x00000000, |
| 367 | 0x0, |
| 368 | 0x0, |
| 369 | 0x40000000, |
| 370 | 0x08102040 |
| 371 | }; |
| 372 | |
Felipe Balbi | 9cb9f33 | 2014-06-10 15:01:20 -0500 | [diff] [blame] | 373 | static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = { |
| 374 | /* first 5 are taken care by emif_regs */ |
| 375 | 0x00700070, |
| 376 | |
| 377 | 0x00350035, |
| 378 | 0x00350035, |
| 379 | 0x00350035, |
| 380 | 0x00350035, |
| 381 | 0x00350035, |
| 382 | |
| 383 | 0x00000000, |
| 384 | 0x00000000, |
| 385 | 0x00000000, |
| 386 | 0x00000000, |
| 387 | 0x00000000, |
| 388 | |
| 389 | 0x00150015, |
| 390 | 0x00150015, |
| 391 | 0x00150015, |
| 392 | 0x00150015, |
| 393 | 0x00150015, |
| 394 | |
| 395 | 0x00800080, |
| 396 | 0x00800080, |
| 397 | |
| 398 | 0x40000000, |
| 399 | |
| 400 | 0x08102040, |
| 401 | |
| 402 | 0x00000000, |
| 403 | 0x00000000, |
| 404 | 0x00000000, |
| 405 | 0x00000000, |
| 406 | 0x00000000, |
| 407 | 0x00000000, |
| 408 | 0x00000000, |
| 409 | 0x00000000, |
| 410 | 0x00000000, |
| 411 | 0x00000000, |
| 412 | 0x00000000, |
| 413 | }; |
| 414 | |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 415 | void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) |
| 416 | { |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 417 | if (board_is_eposevm()) { |
| 418 | *regs = ext_phy_ctrl_const_base_lpddr2; |
| 419 | *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); |
Franklin S. Cooper Jr | 2c95211 | 2014-06-27 13:31:14 -0500 | [diff] [blame] | 420 | } else if (board_is_evm_14_or_later()) { |
| 421 | *regs = ext_phy_ctrl_const_base_ddr3_production; |
| 422 | *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production); |
| 423 | } else if (board_is_evm_12_or_later()) { |
| 424 | *regs = ext_phy_ctrl_const_base_ddr3_beta; |
| 425 | *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta); |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 426 | } else if (board_is_gpevm()) { |
| 427 | *regs = ext_phy_ctrl_const_base_ddr3; |
| 428 | *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); |
Felipe Balbi | 9cb9f33 | 2014-06-10 15:01:20 -0500 | [diff] [blame] | 429 | } else if (board_is_sk()) { |
| 430 | *regs = ext_phy_ctrl_const_base_ddr3_sk; |
| 431 | *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk); |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 432 | } |
Lokesh Vutla | d3daba1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 433 | |
| 434 | return; |
| 435 | } |
| 436 | |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 437 | const struct dpll_params *get_dpll_ddr_params(void) |
| 438 | { |
Lokesh Vutla | cf04d03 | 2013-12-10 15:02:20 +0530 | [diff] [blame] | 439 | if (board_is_eposevm()) |
| 440 | return &epos_evm_dpll_ddr; |
Felipe Balbi | 9cb9f33 | 2014-06-10 15:01:20 -0500 | [diff] [blame] | 441 | else if (board_is_gpevm() || board_is_sk()) |
Lokesh Vutla | cf04d03 | 2013-12-10 15:02:20 +0530 | [diff] [blame] | 442 | return &gp_evm_dpll_ddr; |
| 443 | |
Felipe Balbi | d51e5ae | 2014-06-10 15:01:18 -0500 | [diff] [blame] | 444 | printf(" Board '%s' not supported\n", am43xx_board_name); |
Lokesh Vutla | cf04d03 | 2013-12-10 15:02:20 +0530 | [diff] [blame] | 445 | return NULL; |
| 446 | } |
| 447 | |
| 448 | /* |
| 449 | * get_sys_clk_index : returns the index of the sys_clk read from |
| 450 | * ctrl status register. This value is either |
| 451 | * read from efuse or sysboot pins. |
| 452 | */ |
| 453 | static u32 get_sys_clk_index(void) |
| 454 | { |
| 455 | struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; |
| 456 | u32 ind = readl(&ctrl->statusreg), src; |
| 457 | |
| 458 | src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; |
| 459 | if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ |
| 460 | return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> |
| 461 | CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); |
| 462 | else /* Value read from SYS BOOT pins */ |
| 463 | return ((ind & CTRL_SYSBOOT_15_14_MASK) >> |
| 464 | CTRL_SYSBOOT_15_14_SHIFT); |
| 465 | } |
| 466 | |
| 467 | /* |
| 468 | * get_opp_offset: |
| 469 | * Returns the index for safest OPP of the device to boot. |
| 470 | * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. |
| 471 | * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. |
| 472 | * This data is read from dev_attribute register which is e-fused. |
| 473 | * A'1' in bit indicates OPP disabled and not available, a '0' indicates |
| 474 | * OPP available. Lowest OPP starts with min_off. So returning the |
| 475 | * bit with rightmost '0'. |
| 476 | */ |
| 477 | static int get_opp_offset(int max_off, int min_off) |
| 478 | { |
| 479 | struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; |
Tom Rini | feca6e6 | 2014-06-05 11:15:27 -0400 | [diff] [blame] | 480 | int opp, offset, i; |
| 481 | |
| 482 | /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ |
| 483 | opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; |
Lokesh Vutla | cf04d03 | 2013-12-10 15:02:20 +0530 | [diff] [blame] | 484 | |
| 485 | for (i = max_off; i >= min_off; i--) { |
| 486 | offset = opp & (1 << i); |
| 487 | if (!offset) |
| 488 | return i; |
| 489 | } |
| 490 | |
| 491 | return min_off; |
| 492 | } |
| 493 | |
| 494 | const struct dpll_params *get_dpll_mpu_params(void) |
| 495 | { |
| 496 | int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); |
| 497 | u32 ind = get_sys_clk_index(); |
| 498 | |
| 499 | return &dpll_mpu[ind][opp]; |
| 500 | } |
| 501 | |
| 502 | const struct dpll_params *get_dpll_core_params(void) |
| 503 | { |
| 504 | int ind = get_sys_clk_index(); |
| 505 | |
| 506 | return &dpll_core[ind]; |
| 507 | } |
| 508 | |
| 509 | const struct dpll_params *get_dpll_per_params(void) |
| 510 | { |
| 511 | int ind = get_sys_clk_index(); |
| 512 | |
| 513 | return &dpll_per[ind]; |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 514 | } |
| 515 | |
Tom Rini | 83bad10 | 2014-06-05 11:15:30 -0400 | [diff] [blame] | 516 | void scale_vcores(void) |
| 517 | { |
| 518 | const struct dpll_params *mpu_params; |
| 519 | int mpu_vdd; |
| 520 | struct am43xx_board_id header; |
| 521 | |
| 522 | enable_i2c0_pin_mux(); |
| 523 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); |
| 524 | if (read_eeprom(&header) < 0) |
| 525 | puts("Could not get board ID.\n"); |
| 526 | |
| 527 | /* Get the frequency */ |
| 528 | mpu_params = get_dpll_mpu_params(); |
| 529 | |
| 530 | if (i2c_probe(TPS65218_CHIP_PM)) |
| 531 | return; |
| 532 | |
| 533 | if (mpu_params->m == 1000) { |
| 534 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; |
| 535 | } else if (mpu_params->m == 600) { |
| 536 | mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; |
| 537 | } else { |
| 538 | puts("Unknown MPU clock, not scaling\n"); |
| 539 | return; |
| 540 | } |
| 541 | |
| 542 | /* Set DCDC1 (CORE) voltage to 1.1V */ |
| 543 | if (tps65218_voltage_update(TPS65218_DCDC1, |
| 544 | TPS65218_DCDC_VOLT_SEL_1100MV)) { |
| 545 | puts("tps65218_voltage_update failure\n"); |
| 546 | return; |
| 547 | } |
| 548 | |
| 549 | /* Set DCDC2 (MPU) voltage */ |
| 550 | if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { |
| 551 | puts("tps65218_voltage_update failure\n"); |
| 552 | return; |
| 553 | } |
| 554 | } |
| 555 | |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 556 | void set_uart_mux_conf(void) |
| 557 | { |
| 558 | enable_uart0_pin_mux(); |
| 559 | } |
| 560 | |
| 561 | void set_mux_conf_regs(void) |
| 562 | { |
| 563 | enable_board_pin_mux(); |
| 564 | } |
| 565 | |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 566 | static void enable_vtt_regulator(void) |
| 567 | { |
| 568 | u32 temp; |
| 569 | |
| 570 | /* enable module */ |
Dave Gerlach | cd8341b | 2014-02-10 11:41:49 -0500 | [diff] [blame] | 571 | writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 572 | |
Dave Gerlach | cd8341b | 2014-02-10 11:41:49 -0500 | [diff] [blame] | 573 | /* enable output for GPIO5_7 */ |
| 574 | writel(GPIO_SETDATAOUT(7), |
| 575 | AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); |
| 576 | temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); |
| 577 | temp = temp & ~(GPIO_OE_ENABLE(7)); |
| 578 | writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 579 | } |
| 580 | |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 581 | void sdram_init(void) |
| 582 | { |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 583 | /* |
| 584 | * EPOS EVM has 1GB LPDDR2 connected to EMIF. |
| 585 | * GP EMV has 1GB DDR3 connected to EMIF |
| 586 | * along with VTT regulator. |
| 587 | */ |
| 588 | if (board_is_eposevm()) { |
| 589 | config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); |
Franklin S. Cooper Jr | 2c95211 | 2014-06-27 13:31:14 -0500 | [diff] [blame] | 590 | } else if (board_is_evm_14_or_later()) { |
| 591 | enable_vtt_regulator(); |
| 592 | config_ddr(0, &ioregs_ddr3, NULL, NULL, |
| 593 | &ddr3_emif_regs_400Mhz_production, 0); |
| 594 | } else if (board_is_evm_12_or_later()) { |
| 595 | enable_vtt_regulator(); |
| 596 | config_ddr(0, &ioregs_ddr3, NULL, NULL, |
| 597 | &ddr3_emif_regs_400Mhz_beta, 0); |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 598 | } else if (board_is_gpevm()) { |
| 599 | enable_vtt_regulator(); |
| 600 | config_ddr(0, &ioregs_ddr3, NULL, NULL, |
| 601 | &ddr3_emif_regs_400Mhz, 0); |
Felipe Balbi | 9cb9f33 | 2014-06-10 15:01:20 -0500 | [diff] [blame] | 602 | } else if (board_is_sk()) { |
| 603 | config_ddr(400, &ioregs_ddr3, NULL, NULL, |
| 604 | &ddr3_sk_emif_regs_400Mhz, 0); |
Lokesh Vutla | b5e01ee | 2013-12-10 15:02:23 +0530 | [diff] [blame] | 605 | } |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 606 | } |
| 607 | #endif |
| 608 | |
Tom Rini | 7aa5598 | 2014-06-23 16:06:29 -0400 | [diff] [blame] | 609 | /* setup board specific PMIC */ |
| 610 | int power_init_board(void) |
| 611 | { |
| 612 | struct pmic *p; |
| 613 | |
| 614 | power_tps65218_init(I2C_PMIC); |
| 615 | p = pmic_get("TPS65218_PMIC"); |
| 616 | if (p && !pmic_probe(p)) |
| 617 | puts("PMIC: TPS65218\n"); |
| 618 | |
| 619 | return 0; |
| 620 | } |
| 621 | |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 622 | int board_init(void) |
| 623 | { |
Cooper Jr., Franklin | 8038b49 | 2014-06-27 13:31:15 -0500 | [diff] [blame] | 624 | struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; |
| 625 | u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, |
| 626 | modena_init0_bw_integer, modena_init0_watermark_0; |
| 627 | |
Lokesh Vutla | 369cbe1 | 2013-12-10 15:02:12 +0530 | [diff] [blame] | 628 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
pekon gupta | e53ad4b | 2014-07-22 16:03:22 +0530 | [diff] [blame^] | 629 | gpmc_init(); |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 630 | |
Cooper Jr., Franklin | 8038b49 | 2014-06-27 13:31:15 -0500 | [diff] [blame] | 631 | /* Clear all important bits for DSS errata that may need to be tweaked*/ |
| 632 | mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & |
| 633 | MREQPRIO_0_SAB_INIT0_MASK; |
| 634 | |
| 635 | mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; |
| 636 | |
| 637 | modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & |
| 638 | BW_LIMITER_BW_FRAC_MASK; |
| 639 | |
| 640 | modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & |
| 641 | BW_LIMITER_BW_INT_MASK; |
| 642 | |
| 643 | modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & |
| 644 | BW_LIMITER_BW_WATERMARK_MASK; |
| 645 | |
| 646 | /* Setting MReq Priority of the DSS*/ |
| 647 | mreqprio_0 |= 0x77; |
| 648 | |
| 649 | /* |
| 650 | * Set L3 Fast Configuration Register |
| 651 | * Limiting bandwith for ARM core to 700 MBPS |
| 652 | */ |
| 653 | modena_init0_bw_fractional |= 0x10; |
| 654 | modena_init0_bw_integer |= 0x3; |
| 655 | |
| 656 | writel(mreqprio_0, &cdev->mreqprio_0); |
| 657 | writel(mreqprio_1, &cdev->mreqprio_1); |
| 658 | |
| 659 | writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); |
| 660 | writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); |
| 661 | writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); |
| 662 | |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 663 | return 0; |
| 664 | } |
| 665 | |
| 666 | #ifdef CONFIG_BOARD_LATE_INIT |
| 667 | int board_late_init(void) |
| 668 | { |
Sekhar Nori | f4af163 | 2013-12-10 15:02:16 +0530 | [diff] [blame] | 669 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 670 | char safe_string[HDR_NAME_LEN + 1]; |
| 671 | struct am43xx_board_id header; |
| 672 | |
| 673 | if (read_eeprom(&header) < 0) |
| 674 | puts("Could not get board ID.\n"); |
| 675 | |
| 676 | /* Now set variables based on the header. */ |
| 677 | strncpy(safe_string, (char *)header.name, sizeof(header.name)); |
| 678 | safe_string[sizeof(header.name)] = 0; |
| 679 | setenv("board_name", safe_string); |
| 680 | |
| 681 | strncpy(safe_string, (char *)header.version, sizeof(header.version)); |
| 682 | safe_string[sizeof(header.version)] = 0; |
| 683 | setenv("board_rev", safe_string); |
| 684 | #endif |
Lokesh Vutla | fbf2728 | 2013-07-30 11:36:27 +0530 | [diff] [blame] | 685 | return 0; |
| 686 | } |
| 687 | #endif |
Mugunthan V N | 4cdd7fd | 2014-02-18 07:31:54 -0500 | [diff] [blame] | 688 | |
| 689 | #ifdef CONFIG_DRIVER_TI_CPSW |
| 690 | |
| 691 | static void cpsw_control(int enabled) |
| 692 | { |
| 693 | /* Additional controls can be added here */ |
| 694 | return; |
| 695 | } |
| 696 | |
| 697 | static struct cpsw_slave_data cpsw_slaves[] = { |
| 698 | { |
| 699 | .slave_reg_ofs = 0x208, |
| 700 | .sliver_reg_ofs = 0xd80, |
| 701 | .phy_addr = 16, |
| 702 | }, |
| 703 | { |
| 704 | .slave_reg_ofs = 0x308, |
| 705 | .sliver_reg_ofs = 0xdc0, |
| 706 | .phy_addr = 1, |
| 707 | }, |
| 708 | }; |
| 709 | |
| 710 | static struct cpsw_platform_data cpsw_data = { |
| 711 | .mdio_base = CPSW_MDIO_BASE, |
| 712 | .cpsw_base = CPSW_BASE, |
| 713 | .mdio_div = 0xff, |
| 714 | .channels = 8, |
| 715 | .cpdma_reg_ofs = 0x800, |
| 716 | .slaves = 1, |
| 717 | .slave_data = cpsw_slaves, |
| 718 | .ale_reg_ofs = 0xd00, |
| 719 | .ale_entries = 1024, |
| 720 | .host_port_reg_ofs = 0x108, |
| 721 | .hw_stats_reg_ofs = 0x900, |
| 722 | .bd_ram_ofs = 0x2000, |
| 723 | .mac_control = (1 << 5), |
| 724 | .control = cpsw_control, |
| 725 | .host_port_num = 0, |
| 726 | .version = CPSW_CTRL_VERSION_2, |
| 727 | }; |
| 728 | |
| 729 | int board_eth_init(bd_t *bis) |
| 730 | { |
| 731 | int rv; |
| 732 | uint8_t mac_addr[6]; |
| 733 | uint32_t mac_hi, mac_lo; |
| 734 | |
| 735 | /* try reading mac address from efuse */ |
| 736 | mac_lo = readl(&cdev->macid0l); |
| 737 | mac_hi = readl(&cdev->macid0h); |
| 738 | mac_addr[0] = mac_hi & 0xFF; |
| 739 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 740 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 741 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 742 | mac_addr[4] = mac_lo & 0xFF; |
| 743 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 744 | |
| 745 | if (!getenv("ethaddr")) { |
| 746 | puts("<ethaddr> not set. Validating first E-fuse MAC\n"); |
| 747 | if (is_valid_ether_addr(mac_addr)) |
| 748 | eth_setenv_enetaddr("ethaddr", mac_addr); |
| 749 | } |
| 750 | |
| 751 | mac_lo = readl(&cdev->macid1l); |
| 752 | mac_hi = readl(&cdev->macid1h); |
| 753 | mac_addr[0] = mac_hi & 0xFF; |
| 754 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; |
| 755 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; |
| 756 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; |
| 757 | mac_addr[4] = mac_lo & 0xFF; |
| 758 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; |
| 759 | |
| 760 | if (!getenv("eth1addr")) { |
| 761 | if (is_valid_ether_addr(mac_addr)) |
| 762 | eth_setenv_enetaddr("eth1addr", mac_addr); |
| 763 | } |
| 764 | |
| 765 | if (board_is_eposevm()) { |
| 766 | writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); |
| 767 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; |
| 768 | cpsw_slaves[0].phy_addr = 16; |
Felipe Balbi | 619ce62 | 2014-06-10 15:01:21 -0500 | [diff] [blame] | 769 | } else if (board_is_sk()) { |
| 770 | writel(RGMII_MODE_ENABLE, &cdev->miisel); |
| 771 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; |
| 772 | cpsw_slaves[0].phy_addr = 4; |
| 773 | cpsw_slaves[1].phy_addr = 5; |
Mugunthan V N | 4cdd7fd | 2014-02-18 07:31:54 -0500 | [diff] [blame] | 774 | } else { |
| 775 | writel(RGMII_MODE_ENABLE, &cdev->miisel); |
| 776 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; |
| 777 | cpsw_slaves[0].phy_addr = 0; |
| 778 | } |
| 779 | |
| 780 | rv = cpsw_register(&cpsw_data); |
| 781 | if (rv < 0) |
| 782 | printf("Error %d registering CPSW switch\n", rv); |
| 783 | |
| 784 | return rv; |
| 785 | } |
| 786 | #endif |