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wdenk56f94be2002-11-05 16:35:14 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenk56f94be2002-11-05 16:35:14 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk0608e042004-03-25 19:29:38 +000016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk56f94be2002-11-05 16:35:14 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 * Derived from ../tqm8xx/tqm8xx.c
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
39#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
40
wdenk0608e042004-03-25 19:29:38 +000041#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenk56f94be2002-11-05 16:35:14 +000042#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
wdenk682011f2003-06-03 23:54:09 +000044#define CONFIG_BAUDRATE 115200 /* console baudrate */
wdenk56f94be2002-11-05 16:35:14 +000045#if 0
46#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47#else
wdenk682011f2003-06-03 23:54:09 +000048#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
wdenk56f94be2002-11-05 16:35:14 +000049#endif
50
wdenk56f94be2002-11-05 16:35:14 +000051#define CONFIG_BOARD_TYPES 1 /* support board types */
52
wdenk56f94be2002-11-05 16:35:14 +000053
54#undef CONFIG_BOOTARGS
55
wdenk56f94be2002-11-05 16:35:14 +000056
wdenk0608e042004-03-25 19:29:38 +000057#define CONFIG_EXTRA_ENV_SETTINGS \
58"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
59 "run addhw; diskboot 200000 0:1; bootm 200000\0" \
60"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
61 "run addhw; diskboot 200000 2:1; bootm 200000\0" \
62"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \
63"panic_boot=echo No Bootdevice !!! reset\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010064"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
wdenk0608e042004-03-25 19:29:38 +000065"ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
67 ":${netmask}:${hostname}:${netdev}:off\0" \
68"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
wdenk0608e042004-03-25 19:29:38 +000069"netdev=eth0\0" \
70"contrast=55\0" \
71"silent=1\0" \
72"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010073"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \
wdenk02b11f82004-05-12 22:54:36 +000074 "cp.b 200000 40050000 14000\0"
wdenk56f94be2002-11-05 16:35:14 +000075
wdenk682011f2003-06-03 23:54:09 +000076#define CONFIG_BOOTCOMMAND \
77 "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
78
wdenk56f94be2002-11-05 16:35:14 +000079
wdenk0608e042004-03-25 19:29:38 +000080#define CONFIG_MISC_INIT_R 1
81#define CONFIG_MISC_INIT_F 1
wdenk56f94be2002-11-05 16:35:14 +000082
83#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk56f94be2002-11-05 16:35:14 +000085
wdenk02b11f82004-05-12 22:54:36 +000086#define CONFIG_WATCHDOG 1 /* watchdog enabled */
wdenk56f94be2002-11-05 16:35:14 +000087
wdenk0608e042004-03-25 19:29:38 +000088#define CONFIG_STATUS_LED 1 /* Status LED enabled */
wdenk56f94be2002-11-05 16:35:14 +000089
90#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
91
Jon Loeliger7be044e2007-07-09 21:24:19 -050092/*
93 * BOOTP options
94 */
95#define CONFIG_BOOTP_SUBNETMASK
96#define CONFIG_BOOTP_GATEWAY
97#define CONFIG_BOOTP_HOSTNAME
98#define CONFIG_BOOTP_BOOTPATH
99#define CONFIG_BOOTP_BOOTFILESIZE
100
wdenk56f94be2002-11-05 16:35:14 +0000101
102#define CONFIG_MAC_PARTITION
103#define CONFIG_DOS_PARTITION
104
wdenk56f94be2002-11-05 16:35:14 +0000105
wdenk02b11f82004-05-12 22:54:36 +0000106/*
107 * enable I2C and select the hardware/software driver
108 */
109#undef CONFIG_HARD_I2C /* I2C with hardware support */
110#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
wdenk0608e042004-03-25 19:29:38 +0000111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
113#define CONFIG_SYS_I2C_SLAVE 0xFE
wdenk02b11f82004-05-12 22:54:36 +0000114
115#ifdef CONFIG_SOFT_I2C
116/*
117 * Software (bit-bang) I2C driver configuration
118 */
119#define PB_SCL 0x00000020 /* PB 26 */
120#define PB_SDA 0x00000010 /* PB 27 */
121
122#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
123#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
124#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
125#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
126#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
127 else immr->im_cpm.cp_pbdat &= ~PB_SDA
128#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
129 else immr->im_cpm.cp_pbdat &= ~PB_SCL
130#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
131#endif /* CONFIG_SOFT_I2C */
132
133
134/*-----------------------------------------------------------------------
135 * I2C Configuration
136 */
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
139#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
wdenk02b11f82004-05-12 22:54:36 +0000140
141
142/* List of I2C addresses to be verified by POST */
143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define I2C_ADDR_LIST {CONFIG_SYS_I2C_PICIO_ADDR, \
145 CONFIG_SYS_I2C_RTC_ADDR, \
wdenk02b11f82004-05-12 22:54:36 +0000146 }
147
148
149#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_DISCOVER_PHY
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200152#define CONFIG_MII
wdenk02b11f82004-05-12 22:54:36 +0000153
154#if 0
155#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
156#endif
157#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */
wdenk56f94be2002-11-05 16:35:14 +0000158
159/* Define to allow the user to overwrite serial and ethaddr */
160#define CONFIG_ENV_OVERWRITE
wdenk02b11f82004-05-12 22:54:36 +0000161#if 1
162/* POST support */
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_POST (CONFIG_SYS_POST_CPU | \
165 CONFIG_SYS_POST_RTC | \
166 CONFIG_SYS_POST_I2C)
wdenk02b11f82004-05-12 22:54:36 +0000167#endif
wdenk56f94be2002-11-05 16:35:14 +0000168
wdenk56f94be2002-11-05 16:35:14 +0000169
Jon Loeliger348f2582007-07-08 13:46:18 -0500170/*
171 * Command line configuration.
172 */
173#include <config_cmd_default.h>
174
175#define CONFIG_CMD_DATE
176#define CONFIG_CMD_DHCP
177#define CONFIG_CMD_I2C
178#define CONFIG_CMD_IDE
179#define CONFIG_CMD_NFS
Jon Loeliger348f2582007-07-08 13:46:18 -0500180#define CONFIG_CMD_SNTP
181
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500182#ifdef CONFIG_POST
183 #define CONFIG_CMD_DIAG
184#endif
wdenk56f94be2002-11-05 16:35:14 +0000185
186/*
187 * Miscellaneous configurable options
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_LONGHELP /* undef to save memory */
190#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500191#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk56f94be2002-11-05 16:35:14 +0000193#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk56f94be2002-11-05 16:35:14 +0000195#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
197#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
198#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk56f94be2002-11-05 16:35:14 +0000199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
201#define CONFIG_SYS_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */
wdenk56f94be2002-11-05 16:35:14 +0000202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
wdenk56f94be2002-11-05 16:35:14 +0000204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk56f94be2002-11-05 16:35:14 +0000206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
wdenk56f94be2002-11-05 16:35:14 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
wdenk682011f2003-06-03 23:54:09 +0000210
wdenk56f94be2002-11-05 16:35:14 +0000211/*
212 * Low Level Configuration Settings
213 * (address mappings, register initial values, etc.)
214 * You should know what you are doing if you make changes here.
215 */
216/*-----------------------------------------------------------------------
217 * Internal Memory Mapped Register
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_IMMR 0xFFF00000
wdenk56f94be2002-11-05 16:35:14 +0000220
221/*-----------------------------------------------------------------------
222 * Definitions for initial stack pointer and data area (in DPRAM)
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
225#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
226#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
227#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
228#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk56f94be2002-11-05 16:35:14 +0000229
230/*-----------------------------------------------------------------------
231 * Start addresses for the final memory configuration
232 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk56f94be2002-11-05 16:35:14 +0000234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_SDRAM_BASE 0x00000000
236#define CONFIG_SYS_FLASH_BASE 0x40000000
237#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
238#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
239#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk56f94be2002-11-05 16:35:14 +0000240
241/*
242 * For booting Linux, the board info and command line data
243 * have to be in the first 8 MB of memory, since this is
244 * the maximum mapped by the Linux kernel during initialization.
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk56f94be2002-11-05 16:35:14 +0000247
248/*-----------------------------------------------------------------------
249 * FLASH organization
250 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
252#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
wdenk56f94be2002-11-05 16:35:14 +0000253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
255#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk56f94be2002-11-05 16:35:14 +0000256
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200257#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200258#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
259#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
260#define CONFIG_ENV_SECT_SIZE 0x10000
wdenk56f94be2002-11-05 16:35:14 +0000261
262/* Address and size of Redundant Environment Sector */
263#if 0
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200264#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
265#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk56f94be2002-11-05 16:35:14 +0000266#endif
267/*-----------------------------------------------------------------------
268 * Hardware Information Block
269 */
wdenk02b11f82004-05-12 22:54:36 +0000270#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
272#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
273#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
wdenk56f94be2002-11-05 16:35:14 +0000274#endif
275/*-----------------------------------------------------------------------
276 * Cache Configuration
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500279#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk56f94be2002-11-05 16:35:14 +0000281#endif
282
283/*-----------------------------------------------------------------------
284 * SYPCR - System Protection Control 11-9
285 * SYPCR can only be written once after reset!
286 *-----------------------------------------------------------------------
287 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
288 */
wdenk02b11f82004-05-12 22:54:36 +0000289#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk56f94be2002-11-05 16:35:14 +0000291 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
292#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk56f94be2002-11-05 16:35:14 +0000294#endif
295
296/*-----------------------------------------------------------------------
297 * SIUMCR - SIU Module Configuration 11-6
298 *-----------------------------------------------------------------------
299 * PCMCIA config., multi-function pin tri-state
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
wdenk56f94be2002-11-05 16:35:14 +0000302
303/*-----------------------------------------------------------------------
304 * TBSCR - Time Base Status and Control 11-26
305 *-----------------------------------------------------------------------
306 * Clear Reference Interrupt Status, Timebase freezing enabled
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk56f94be2002-11-05 16:35:14 +0000309
310/*-----------------------------------------------------------------------
311 * RTCSC - Real-Time Clock Status and Control Register 11-27
312 *-----------------------------------------------------------------------
313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk56f94be2002-11-05 16:35:14 +0000315
316/*-----------------------------------------------------------------------
317 * PISCR - Periodic Interrupt Status and Control 11-31
318 *-----------------------------------------------------------------------
319 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
320 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk56f94be2002-11-05 16:35:14 +0000322
323/*-----------------------------------------------------------------------
324 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
325 *-----------------------------------------------------------------------
326 * Reset PLL lock status sticky bit, timer expired status bit and timer
327 * interrupt status bit
328 *
329 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
330 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
wdenk56f94be2002-11-05 16:35:14 +0000332
333/*-----------------------------------------------------------------------
334 * SCCR - System Clock and reset Control Register 15-27
335 *-----------------------------------------------------------------------
336 * Set clock output, timebase and RTC source and divider,
337 * power management and some other internal clocks
338 */
339#define SCCR_MASK SCCR_EBDF00
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \
wdenk56f94be2002-11-05 16:35:14 +0000341 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
342 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
343 SCCR_DFALCD00)
344
345/*-----------------------------------------------------------------------
346 * PCMCIA stuff
347 *-----------------------------------------------------------------------
348 *
349 */
350
wdenkea909b72002-11-21 23:11:29 +0000351/* KUP4K use both slots, SLOT_A as "primary". */
wdenk0608e042004-03-25 19:29:38 +0000352#define CONFIG_PCMCIA_SLOT_A 1
wdenk56f94be2002-11-05 16:35:14 +0000353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
355#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
356#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
357#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
358#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
359#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
360#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
361#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk56f94be2002-11-05 16:35:14 +0000362
wdenkea909b72002-11-21 23:11:29 +0000363#define PCMCIA_SOCKETS_NO 2
364#define PCMCIA_MEM_WIN_NO 8
wdenk56f94be2002-11-05 16:35:14 +0000365/*-----------------------------------------------------------------------
366 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
367 *-----------------------------------------------------------------------
368 */
369
wdenk0608e042004-03-25 19:29:38 +0000370#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenk56f94be2002-11-05 16:35:14 +0000371
wdenk0608e042004-03-25 19:29:38 +0000372#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
373#define CONFIG_IDE_LED 1 /* LED for ide supported */
wdenk56f94be2002-11-05 16:35:14 +0000374#undef CONFIG_IDE_RESET /* reset for ide not supported */
375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_IDE_MAXBUS 2
377#define CONFIG_SYS_IDE_MAXDEVICE 4
wdenk56f94be2002-11-05 16:35:14 +0000378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk56f94be2002-11-05 16:35:14 +0000380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
wdenkea909b72002-11-21 23:11:29 +0000382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk56f94be2002-11-05 16:35:14 +0000384
385/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk56f94be2002-11-05 16:35:14 +0000387
388/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk56f94be2002-11-05 16:35:14 +0000390
391/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk56f94be2002-11-05 16:35:14 +0000393
394
395/*-----------------------------------------------------------------------
396 *
397 *-----------------------------------------------------------------------
398 *
399 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_DER 0
wdenk56f94be2002-11-05 16:35:14 +0000401
402/*
403 * Init Memory Controller:
404 *
405 * BR0/1 and OR0/1 (FLASH)
406 */
407#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
408
409/* used to re-map FLASH both when starting from SRAM or FLASH:
410 * restrict access enough to keep SRAM working (if any)
411 * but not too much to meddle with FLASH accesses
412 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
414#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk56f94be2002-11-05 16:35:14 +0000415
416/*
417 * FLASH timing:
418 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenk56f94be2002-11-05 16:35:14 +0000420 OR_SCY_2_CLK | OR_EHTR | OR_BI)
421
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
423#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
424#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
wdenk56f94be2002-11-05 16:35:14 +0000425
426
wdenk56f94be2002-11-05 16:35:14 +0000427/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk56f94be2002-11-05 16:35:14 +0000429
wdenk56f94be2002-11-05 16:35:14 +0000430
431/*
432 * Memory Periodic Timer Prescaler
433 *
434 * The Divider for PTA (refresh timer) configuration is based on an
435 * example SDRAM configuration (64 MBit, one bank). The adjustment to
436 * the number of chip selects (NCS) and the actually needed refresh
437 * rate is done by setting MPTPR.
438 *
439 * PTA is calculated from
440 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
441 *
442 * gclk CPU clock (not bus clock!)
443 * Trefresh Refresh cycle * 4 (four word bursts used)
444 *
wdenk0608e042004-03-25 19:29:38 +0000445 * 4096 Rows from SDRAM example configuration
446 * 1000 factor s -> ms
447 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
448 * 4 Number of refresh cycles per period
449 * 64 Refresh cycle in ms per number of rows
wdenk56f94be2002-11-05 16:35:14 +0000450 * --------------------------------------------
451 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
452 *
453 * 50 MHz => 50.000.000 / Divider = 98
454 * 66 Mhz => 66.000.000 / Divider = 129
455 * 80 Mhz => 80.000.000 / Divider = 156
456 */
457#if defined(CONFIG_80MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_MAMR_PTA 156
wdenk56f94be2002-11-05 16:35:14 +0000459#elif defined(CONFIG_66MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_MAMR_PTA 129
wdenk56f94be2002-11-05 16:35:14 +0000461#else /* 50 MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_MAMR_PTA 98
wdenk56f94be2002-11-05 16:35:14 +0000463#endif /*CONFIG_??MHz */
464
465/*
466 * For 16 MBit, refresh rates could be 31.3 us
467 * (= 64 ms / 2K = 125 / quad bursts).
468 * For a simpler initialization, 15.6 us is used instead.
469 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
471 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenk56f94be2002-11-05 16:35:14 +0000472 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_MPTPR 0x400
wdenk56f94be2002-11-05 16:35:14 +0000474
475/*
476 * MAMR settings for SDRAM
477 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_MAMR 0x80802114
wdenk56f94be2002-11-05 16:35:14 +0000479
480/*
481 * Internal Definitions
482 *
483 * Boot Flags
484 */
wdenk0608e042004-03-25 19:29:38 +0000485#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenk56f94be2002-11-05 16:35:14 +0000486#define BOOTFLAG_WARM 0x02 /* Software reboot */
487
488
489#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
490#if 0
Stefan Roesef2302d42008-08-06 14:05:38 +0200491#define CONFIG_AUTOBOOT_PROMPT \
492 "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay
wdenk56f94be2002-11-05 16:35:14 +0000493#endif
wdenk682011f2003-06-03 23:54:09 +0000494#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
wdenk0608e042004-03-25 19:29:38 +0000495#define CONFIG_SILENT_CONSOLE 1
wdenk56f94be2002-11-05 16:35:14 +0000496
497#endif /* __CONFIG_H */