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wdenk75dc29e2002-08-19 15:30:13 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenk75dc29e2002-08-19 15:30:13 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk75dc29e2002-08-19 15:30:13 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
21#define CONFIG_FPS850L 1 /* ...on a FingerPrint Sensor */
22
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0x40000000
24
wdenk75dc29e2002-08-19 15:30:13 +000025#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020026#define CONFIG_SYS_SMC_RXBUFLEN 128
27#define CONFIG_SYS_MAXIDLE 10
Wolfgang Denkeb6da802007-09-16 02:39:35 +020028#define CONFIG_BAUDRATE 115200
wdenk75dc29e2002-08-19 15:30:13 +000029
Wolfgang Denkeb6da802007-09-16 02:39:35 +020030#define CONFIG_BOOTCOUNT_LIMIT
31
32#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk75dc29e2002-08-19 15:30:13 +000033
34#define CONFIG_BOARD_TYPES 1 /* support board types */
35
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010036#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
Wolfgang Denkeb6da802007-09-16 02:39:35 +020037
38#undef CONFIG_BOOTARGS
39
40#define CONFIG_EXTRA_ENV_SETTINGS \
41 "netdev=eth0\0" \
42 "nfsargs=setenv bootargs root=/dev/nfs rw " \
43 "nfsroot=${serverip}:${rootpath}\0" \
44 "ramargs=setenv bootargs root=/dev/ram rw\0" \
45 "addip=setenv bootargs ${bootargs} " \
46 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
47 ":${hostname}:${netdev}:off panic=1\0" \
48 "flash_nfs=run nfsargs addip;" \
49 "bootm ${kernel_addr}\0" \
50 "flash_self=run ramargs addip;" \
51 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
52 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
53 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020054 "hostname=FPS850L\0" \
55 "bootfile=FPS850L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020056 "fdt_addr=40040000\0" \
57 "kernel_addr=40060000\0" \
58 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020059 "u-boot=FPS850L/u-image.bin\0" \
60 "load=tftp 200000 ${u-boot}\0" \
61 "update=prot off 40000000 +${filesize};" \
62 "era 40000000 +${filesize};" \
63 "cp.b 200000 40000000 ${filesize};" \
64 "sete filesize;save\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020065 ""
66#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk75dc29e2002-08-19 15:30:13 +000067
68#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk75dc29e2002-08-19 15:30:13 +000070
71#undef CONFIG_WATCHDOG /* watchdog disabled */
72
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050073/*
74 * BOOTP options
75 */
76#define CONFIG_BOOTP_SUBNETMASK
77#define CONFIG_BOOTP_GATEWAY
78#define CONFIG_BOOTP_HOSTNAME
79#define CONFIG_BOOTP_BOOTPATH
80#define CONFIG_BOOTP_BOOTFILESIZE
81#define CONFIG_BOOTP_SUBNETMASK
82#define CONFIG_BOOTP_GATEWAY
83#define CONFIG_BOOTP_HOSTNAME
84#define CONFIG_BOOTP_NISDOMAIN
85#define CONFIG_BOOTP_BOOTPATH
86#define CONFIG_BOOTP_DNS
87#define CONFIG_BOOTP_DNS2
88#define CONFIG_BOOTP_SEND_HOSTNAME
89#define CONFIG_BOOTP_NTPSERVER
90#define CONFIG_BOOTP_TIMEOFFSET
wdenk75dc29e2002-08-19 15:30:13 +000091
Wolfgang Denkeb6da802007-09-16 02:39:35 +020092#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
wdenk75dc29e2002-08-19 15:30:13 +000093
Jon Loeliger60a08762007-07-07 21:04:26 -050094/*
95 * Command line configuration.
96 */
97#include <config_cmd_default.h>
98
Wolfgang Denkeb6da802007-09-16 02:39:35 +020099#define CONFIG_CMD_ASKENV
100#define CONFIG_CMD_DATE
101#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200102#define CONFIG_CMD_JFFS2
Wolfgang Denkeb6da802007-09-16 02:39:35 +0200103#define CONFIG_CMD_NFS
104#define CONFIG_CMD_SNTP
Jon Loeliger60a08762007-07-07 21:04:26 -0500105
wdenk75dc29e2002-08-19 15:30:13 +0000106
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200107#define CONFIG_NETCONSOLE
108
109
wdenk75dc29e2002-08-19 15:30:13 +0000110/*
111 * Miscellaneous configurable options
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LONGHELP /* undef to save memory */
114#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Wolfgang Denkeb6da802007-09-16 02:39:35 +0200115
116#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Wolfgang Denkeb6da802007-09-16 02:39:35 +0200118
Jon Loeliger60a08762007-07-07 21:04:26 -0500119#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk75dc29e2002-08-19 15:30:13 +0000121#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk75dc29e2002-08-19 15:30:13 +0000123#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
125#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk75dc29e2002-08-19 15:30:13 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
129#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk75dc29e2002-08-19 15:30:13 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk75dc29e2002-08-19 15:30:13 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk75dc29e2002-08-19 15:30:13 +0000134
wdenk75dc29e2002-08-19 15:30:13 +0000135/*
136 * Low Level Configuration Settings
137 * (address mappings, register initial values, etc.)
138 * You should know what you are doing if you make changes here.
139 */
140/*-----------------------------------------------------------------------
141 * Internal Memory Mapped Register
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_IMMR 0xFFF00000
wdenk75dc29e2002-08-19 15:30:13 +0000144
145/*-----------------------------------------------------------------------
146 * Definitions for initial stack pointer and data area (in DPRAM)
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200149#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200150#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk75dc29e2002-08-19 15:30:13 +0000152
153/*-----------------------------------------------------------------------
154 * Start addresses for the final memory configuration
155 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk75dc29e2002-08-19 15:30:13 +0000157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_SDRAM_BASE 0x00000000
159#define CONFIG_SYS_FLASH_BASE 0x40000000
160#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
161#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
162#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk75dc29e2002-08-19 15:30:13 +0000163
164/*
165 * For booting Linux, the board info and command line data
166 * have to be in the first 8 MB of memory, since this is
167 * the maximum mapped by the Linux kernel during initialization.
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk46a414d2004-06-17 18:50:45 +0000170
wdenk75dc29e2002-08-19 15:30:13 +0000171/*-----------------------------------------------------------------------
172 * FLASH organization
173 */
wdenk75dc29e2002-08-19 15:30:13 +0000174
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200175/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200177#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
179#define CONFIG_SYS_FLASH_EMPTY_INFO
180#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
181#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
182#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenk75dc29e2002-08-19 15:30:13 +0000183
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200184#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200185#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
186#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenk75dc29e2002-08-19 15:30:13 +0000187
wdenk46a414d2004-06-17 18:50:45 +0000188/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200189#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
190#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk46a414d2004-06-17 18:50:45 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200193
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200194#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
195
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200196/*-----------------------------------------------------------------------
197 * Dynamic MTD partition support
198 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100199#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200200#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
201#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200202#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
203
204#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
205 "128k(dtb)," \
206 "1664k(kernel)," \
207 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200208 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200209
wdenk75dc29e2002-08-19 15:30:13 +0000210/*-----------------------------------------------------------------------
211 * Hardware Information Block
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
214#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
215#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenk75dc29e2002-08-19 15:30:13 +0000216
217/*-----------------------------------------------------------------------
218 * Cache Configuration
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500221#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk75dc29e2002-08-19 15:30:13 +0000223#endif
224
225/*-----------------------------------------------------------------------
226 * SYPCR - System Protection Control 11-9
227 * SYPCR can only be written once after reset!
228 *-----------------------------------------------------------------------
229 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
230 */
231#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk75dc29e2002-08-19 15:30:13 +0000233 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
234#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk75dc29e2002-08-19 15:30:13 +0000236#endif
237
238/*-----------------------------------------------------------------------
239 * SIUMCR - SIU Module Configuration 11-6
240 *-----------------------------------------------------------------------
241 * PCMCIA config., multi-function pin tri-state
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk75dc29e2002-08-19 15:30:13 +0000244
245/*-----------------------------------------------------------------------
246 * TBSCR - Time Base Status and Control 11-26
247 *-----------------------------------------------------------------------
248 * Clear Reference Interrupt Status, Timebase freezing enabled
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk75dc29e2002-08-19 15:30:13 +0000251
252/*-----------------------------------------------------------------------
253 * RTCSC - Real-Time Clock Status and Control Register 11-27
254 *-----------------------------------------------------------------------
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk75dc29e2002-08-19 15:30:13 +0000257
258/*-----------------------------------------------------------------------
259 * PISCR - Periodic Interrupt Status and Control 11-31
260 *-----------------------------------------------------------------------
261 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
262 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk75dc29e2002-08-19 15:30:13 +0000264
265/*-----------------------------------------------------------------------
266 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
267 *-----------------------------------------------------------------------
268 * Reset PLL lock status sticky bit, timer expired status bit and timer
269 * interrupt status bit - leave PLL multiplication factor unchanged !
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenk75dc29e2002-08-19 15:30:13 +0000272
273/*-----------------------------------------------------------------------
274 * SCCR - System Clock and reset Control Register 15-27
275 *-----------------------------------------------------------------------
276 * Set clock output, timebase and RTC source and divider,
277 * power management and some other internal clocks
278 */
279#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk75dc29e2002-08-19 15:30:13 +0000281 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
282 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
283 SCCR_DFALCD00)
284
285/*-----------------------------------------------------------------------
286 * PCMCIA stuff
287 *-----------------------------------------------------------------------
288 *
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
291#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
292#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
293#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
294#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
295#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
296#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
297#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk75dc29e2002-08-19 15:30:13 +0000298
299/*-----------------------------------------------------------------------
300 *
301 *-----------------------------------------------------------------------
302 *
303 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_DER 0
wdenk75dc29e2002-08-19 15:30:13 +0000305
306/*
307 * Init Memory Controller:
308 *
309 * BR0/1 and OR0/1 (FLASH)
310 */
311
312#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
313#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
314
315/* used to re-map FLASH both when starting from SRAM or FLASH:
316 * restrict access enough to keep SRAM working (if any)
317 * but not too much to meddle with FLASH accesses
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
320#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk75dc29e2002-08-19 15:30:13 +0000321
wdenk46a414d2004-06-17 18:50:45 +0000322/*
323 * FLASH timing:
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenk46a414d2004-06-17 18:50:45 +0000326 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenk75dc29e2002-08-19 15:30:13 +0000327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
329#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
330#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk75dc29e2002-08-19 15:30:13 +0000331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
333#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
334#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenk75dc29e2002-08-19 15:30:13 +0000335
336/*
337 * BR2/3 and OR2/3 (SDRAM)
338 *
339 */
340#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
341#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
342#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
343
344/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk75dc29e2002-08-19 15:30:13 +0000346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
348#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk75dc29e2002-08-19 15:30:13 +0000349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
351#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk75dc29e2002-08-19 15:30:13 +0000352
353/*
354 * Memory Periodic Timer Prescaler
wdenk46a414d2004-06-17 18:50:45 +0000355 *
356 * The Divider for PTA (refresh timer) configuration is based on an
357 * example SDRAM configuration (64 MBit, one bank). The adjustment to
358 * the number of chip selects (NCS) and the actually needed refresh
359 * rate is done by setting MPTPR.
360 *
361 * PTA is calculated from
362 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
363 *
364 * gclk CPU clock (not bus clock!)
365 * Trefresh Refresh cycle * 4 (four word bursts used)
366 *
367 * 4096 Rows from SDRAM example configuration
368 * 1000 factor s -> ms
369 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
370 * 4 Number of refresh cycles per period
371 * 64 Refresh cycle in ms per number of rows
372 * --------------------------------------------
373 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
374 *
375 * 50 MHz => 50.000.000 / Divider = 98
376 * 66 Mhz => 66.000.000 / Divider = 129
377 * 80 Mhz => 80.000.000 / Divider = 156
wdenk75dc29e2002-08-19 15:30:13 +0000378 */
379
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
381#define CONFIG_SYS_MAMR_PTA 98
wdenk75dc29e2002-08-19 15:30:13 +0000382
wdenk46a414d2004-06-17 18:50:45 +0000383/*
384 * For 16 MBit, refresh rates could be 31.3 us
385 * (= 64 ms / 2K = 125 / quad bursts).
386 * For a simpler initialization, 15.6 us is used instead.
387 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
389 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenk46a414d2004-06-17 18:50:45 +0000390 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
392#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk75dc29e2002-08-19 15:30:13 +0000393
394/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
396#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk75dc29e2002-08-19 15:30:13 +0000397
398/*
399 * MAMR settings for SDRAM
400 */
401
402/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk75dc29e2002-08-19 15:30:13 +0000404 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
405 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
406/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk75dc29e2002-08-19 15:30:13 +0000408 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
409 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
410
Heiko Schocher7026ead2010-02-09 15:50:27 +0100411/* pass open firmware flat tree */
412#define CONFIG_OF_LIBFDT 1
413#define CONFIG_OF_BOARD_SETUP 1
414#define CONFIG_HWCONFIG 1
415
wdenk75dc29e2002-08-19 15:30:13 +0000416#endif /* __CONFIG_H */