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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk0f8c9762002-08-19 11:57:05 +00006 */
7
8/*
9 * Config header file for Cogent platform using an MPC8xx CPU module
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
21#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050022#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk0f8c9762002-08-19 11:57:05 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xfff00000
25
wdenkc837dcb2004-01-20 23:12:12 +000026#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050027#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
wdenkc837dcb2004-01-20 23:12:12 +000028
wdenk0f8c9762002-08-19 11:57:05 +000029/* Cogent Modular Architecture options */
30#define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
31#define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
32
33/*
34 * select serial console configuration
35 *
36 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
37 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
38 * for SCC).
39 *
40 * if CONFIG_CONS_NONE is defined, then the serial console routines must
41 * defined elsewhere (for example, on the cogent platform, there are serial
42 * ports on the motherboard which are used for the serial console - see
43 * cogent/cma101/serial.[ch]).
44 */
45#define CONFIG_CONS_ON_SMC /* define if console on SMC */
46#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
47#undef CONFIG_CONS_NONE /* define if console on something else*/
48#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
49#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
50#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
51#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
52
53/*
54 * select ethernet configuration
55 *
56 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
57 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
58 * for FCC)
59 *
60 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050061 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk0f8c9762002-08-19 11:57:05 +000062 */
63#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
64#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
65#define CONFIG_ETHER_NONE /* define if ether on something else */
66#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
67
68/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
69#define CONFIG_8260_CLKIN 66666666 /* in Hz */
70
71#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
72#define CONFIG_BAUDRATE 230400
73#else
74#define CONFIG_BAUDRATE 9600
75#endif
76
wdenk0f8c9762002-08-19 11:57:05 +000077
Jon Loeliger37e4f242007-07-04 22:31:56 -050078/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050079 * BOOTP options
80 */
81#define CONFIG_BOOTP_BOOTFILESIZE
82#define CONFIG_BOOTP_BOOTPATH
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85
86
87/*
Jon Loeliger37e4f242007-07-04 22:31:56 -050088 * Command line configuration.
89 */
90#include <config_cmd_default.h>
91
92#define CONFIG_CMD_KGDB
93
94#undef CONFIG_CMD_NET
Wolfgang Denkba273f02010-11-24 19:19:08 +010095#undef CONFIG_CMD_NFS
wdenk0f8c9762002-08-19 11:57:05 +000096
97#ifdef DEBUG
98#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
99#else
100#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
101#endif
102#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
103
104#define CONFIG_BOOTARGS "root=/dev/ram rw"
105
Jon Loeliger37e4f242007-07-04 22:31:56 -0500106#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000107#define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
108#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
109#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
110#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
111#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
112#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
113#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
114# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
115#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
116# else
117#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
118# endif
119#endif
120
121#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
122
123/*
124 * Miscellaneous configurable options
125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_LONGHELP /* undef to save memory */
127#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500128#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000130#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000132#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
134#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
135#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
138#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk0f8c9762002-08-19 11:57:05 +0000145
146/*
147 * Low Level Configuration Settings
148 * (address mappings, register initial values, etc.)
149 * You should know what you are doing if you make changes here.
150 */
151
152/*-----------------------------------------------------------------------
153 * Low Level Cogent settings
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154 * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
wdenk0f8c9762002-08-19 11:57:05 +0000155 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
156 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
157 * (second 2 for CMA120 only)
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
wdenk0f8c9762002-08-19 11:57:05 +0000160
161#include <configs/cogent_common.h>
162
163#ifdef CONFIG_CONS_NONE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
wdenk0f8c9762002-08-19 11:57:05 +0000165#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
wdenka8c7c702003-12-06 19:49:23 +0000167#define CONFIG_SHOW_ACTIVITY
wdenk0f8c9762002-08-19 11:57:05 +0000168
169#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
170/*
171 * flash exists on the motherboard
172 * set these four according to TOP dipsw:
173 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
174 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
175 */
176#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
177#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
178#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
179#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
180#endif
181#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
182#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
183
184/*-----------------------------------------------------------------------
185 * Hard Reset Configuration Words
186 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk0f8c9762002-08-19 11:57:05 +0000188 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk0f8c9762002-08-19 11:57:05 +0000190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
wdenk0f8c9762002-08-19 11:57:05 +0000192 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
193/* no slaves so just duplicate the master hrcw */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
195#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
196#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
197#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
198#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
199#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
200#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
wdenk0f8c9762002-08-19 11:57:05 +0000201
202/*-----------------------------------------------------------------------
203 * Internal Memory Mapped Register
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_IMMR 0xF0000000
wdenk0f8c9762002-08-19 11:57:05 +0000206
207/*-----------------------------------------------------------------------
208 * Definitions for initial stack pointer and data area (in DPRAM)
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200211#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200212#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000214
215/*-----------------------------------------------------------------------
216 * Start addresses for the final memory configuration
217 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
wdenk0f8c9762002-08-19 11:57:05 +0000221#ifdef CONFIG_CMA302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
wdenk0f8c9762002-08-19 11:57:05 +0000223#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
wdenk0f8c9762002-08-19 11:57:05 +0000225#endif
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200226#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
228#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenk0f8c9762002-08-19 11:57:05 +0000229
230/*
231 * For booting Linux, the board info and command line data
232 * have to be in the first 8 MB of memory, since this is
233 * the maximum mapped by the Linux kernel during initialization.
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
wdenk0f8c9762002-08-19 11:57:05 +0000236
237/*-----------------------------------------------------------------------
238 * FLASH organization
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
241#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
244#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000245
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200246#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000248#ifdef CONFIG_CMA302
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200249#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
250#define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
wdenk0f8c9762002-08-19 11:57:05 +0000251#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200252#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000253#endif
254
255/*-----------------------------------------------------------------------
256 * Cache Configuration
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500259#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
wdenk0f8c9762002-08-19 11:57:05 +0000261#endif
262
263/*-----------------------------------------------------------------------
264 * HIDx - Hardware Implementation-dependent Registers 2-11
265 *-----------------------------------------------------------------------
266 * HID0 also contains cache control - initially enable both caches and
267 * invalidate contents, then the final state leaves only the instruction
268 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
269 * but Soft reset does not.
270 *
271 * HID1 has only read-only information - nothing to set.
272 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenk0f8c9762002-08-19 11:57:05 +0000274 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
276#define CONFIG_SYS_HID2 0
wdenk0f8c9762002-08-19 11:57:05 +0000277
278/*-----------------------------------------------------------------------
279 * RMR - Reset Mode Register 5-5
280 *-----------------------------------------------------------------------
281 * turn on Checkstop Reset Enable
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_RMR RMR_CSRE
wdenk0f8c9762002-08-19 11:57:05 +0000284
285/*-----------------------------------------------------------------------
286 * BCR - Bus Configuration 4-25
287 *-----------------------------------------------------------------------
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_BCR BCR_EBM
wdenk0f8c9762002-08-19 11:57:05 +0000290
291/*-----------------------------------------------------------------------
292 * SIUMCR - SIU Module Configuration 4-31
293 *-----------------------------------------------------------------------
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
wdenk0f8c9762002-08-19 11:57:05 +0000296
297/*-----------------------------------------------------------------------
298 * SYPCR - System Protection Control 4-35
299 * SYPCR can only be written once after reset!
300 *-----------------------------------------------------------------------
301 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
302 */
303#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk0f8c9762002-08-19 11:57:05 +0000305 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
306#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk0f8c9762002-08-19 11:57:05 +0000308 SYPCR_SWRI|SYPCR_SWP)
309#endif /* CONFIG_WATCHDOG */
310
311/*-----------------------------------------------------------------------
312 * TMCNTSC - Time Counter Status and Control 4-40
313 *-----------------------------------------------------------------------
314 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
315 * and enable Time Counter
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk0f8c9762002-08-19 11:57:05 +0000318
319/*-----------------------------------------------------------------------
320 * PISCR - Periodic Interrupt Status and Control 4-42
321 *-----------------------------------------------------------------------
322 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
323 * Periodic timer
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk0f8c9762002-08-19 11:57:05 +0000326
327/*-----------------------------------------------------------------------
328 * SCCR - System Clock Control 9-8
329 *-----------------------------------------------------------------------
330 * Ensure DFBRG is Divide by 16
331 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
wdenk0f8c9762002-08-19 11:57:05 +0000333
334/*-----------------------------------------------------------------------
335 * RCCR - RISC Controller Configuration 13-7
336 *-----------------------------------------------------------------------
337 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_RCCR 0
wdenk0f8c9762002-08-19 11:57:05 +0000339
340#if defined(CONFIG_CMA282)
341
342/*
343 * Init Memory Controller:
344 *
345 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
346 * and CS2 for (optional) local bus RAM on the CPU module.
347 *
348 * Note the motherboard address space (256 Mbyte in size) is connected
349 * to the 60x Bus and is located starting at address 0. The Hard Reset
350 * Configuration Word should put the 60x Bus into External Bus Mode, since
351 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
352 *
353 * (the *_SIZE vars must be a power of 2)
354 */
355
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200356#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
wdenk0f8c9762002-08-19 11:57:05 +0000358#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
360#define CONFIG_SYS_CMA_CS2_SIZE (16 << 20)
wdenk0f8c9762002-08-19 11:57:05 +0000361#endif
362
363/*
364 * CS0 maps the EPROM on the cpu module
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365 * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
wdenk0f8c9762002-08-19 11:57:05 +0000366 *
367 * Note: We must have already transferred control to the final location
368 * of the EPROM before these are used, because when BR0/OR0 are set, the
369 * mirror of the eprom at any other addresses will disappear.
370 */
371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
373#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
374/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
375#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
wdenk0f8c9762002-08-19 11:57:05 +0000376 ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
377
378/*
379 * CS2 enables the Local Bus SDRAM on the CPU Module
380 *
381 * Will leave this unset for the moment, because a) my CPU module has no
382 * SDRAM installed (it is optional); and b) it will require programming
383 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
384 * if you can't test it.
385 */
386
387#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
389#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
390/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
391#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
wdenk0f8c9762002-08-19 11:57:05 +0000392#endif
393
394#endif
wdenk0f8c9762002-08-19 11:57:05 +0000395#endif /* __CONFIG_H */