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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the R&S Protocol Board board.
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenke2211742002-11-02 23:30:20 +000012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21
22#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
23#define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050024#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenke2211742002-11-02 23:30:20 +000025
Wolfgang Denk2ae18242010-10-06 09:05:45 +020026#define CONFIG_SYS_TEXT_BASE 0xff000000
Wolfgang Denk2ced53e2010-11-28 21:18:58 +010027#define CONFIG_SYS_LDSCRIPT "board/rsdproto/u-boot.lds"
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028
wdenkc837dcb2004-01-20 23:12:12 +000029#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
30
wdenke2211742002-11-02 23:30:20 +000031/*
32 * select serial console configuration
33 *
34 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
35 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
36 * for SCC).
37 *
38 * if CONFIG_CONS_NONE is defined, then the serial console routines must
39 * defined elsewhere.
40 */
41#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
42#define CONFIG_CONS_ON_SCC /* define if console on SCC */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020043#undef CONFIG_CONS_NONE /* define if console on neither */
wdenke2211742002-11-02 23:30:20 +000044#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
45
46/*
47 * select ethernet configuration
48 *
49 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
50 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
51 * for FCC)
52 *
53 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050054 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +000055 */
56#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
57#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
58#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
59#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
60
61#if (CONFIG_ETHER_INDEX == 2)
62
63/*
64 * - Rx-CLK is CLK13
65 * - Tx-CLK is CLK14
66 * - Select bus for bd/buffers (see 28-13)
67 * - Enable Full Duplex in FSMR
68 */
Mike Frysingerd4590da2011-10-17 05:38:58 +000069# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
70# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
72# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenke2211742002-11-02 23:30:20 +000073
74#endif /* CONFIG_ETHER_INDEX */
75
76
77/* allow to overwrite serial and ethaddr */
78#define CONFIG_ENV_OVERWRITE
79
80/* enable I2C */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020081#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
83#define CONFIG_SYS_I2C_SLAVE 0x30
wdenke2211742002-11-02 23:30:20 +000084
85
86/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
87#define CONFIG_8260_CLKIN 50000000 /* in Hz */
88
89#define CONFIG_BAUDRATE 115200
90
Jon Loeliger90cc3eb2007-07-04 22:33:23 -050091
92/*
Jon Loeliger079a1362007-07-10 10:12:10 -050093 * BOOTP options
94 */
95#define CONFIG_BOOTP_BOOTFILESIZE
96#define CONFIG_BOOTP_BOOTPATH
97#define CONFIG_BOOTP_GATEWAY
98#define CONFIG_BOOTP_HOSTNAME
99
100
101/*
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500102 * Command line configuration.
103 */
104#include <config_cmd_default.h>
105
106#undef CONFIG_CMD_KGDB
107
wdenke2211742002-11-02 23:30:20 +0000108
109/* Define this if you want to boot from 0x00000100. If you don't define
110 * this, you will need to program the bootloader to 0xfff00000, and
111 * get the hardware reset config words at 0xfe000000. The simplest
112 * way to do that is to program the bootloader at both addresses.
113 * It is suggested that you just let U-Boot live at 0x00000000.
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_RSD_BOOT_LOW 1
wdenke2211742002-11-02 23:30:20 +0000116
wdenke2211742002-11-02 23:30:20 +0000117#define CONFIG_BOOTDELAY 5
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200118#define CONFIG_BOOTARGS "devfs=mount root=ramfs"
wdenke2211742002-11-02 23:30:20 +0000119#define CONFIG_ETHADDR 08:00:3e:26:0a:5a
120#define CONFIG_NETMASK 255.255.0.0
121
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500122#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000123#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
124#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
125#endif
126
127/*
128 * Miscellaneous configurable options
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_LONGHELP /* undef to save memory */
131#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500132#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000134#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000136#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
138#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
139#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
142#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000147
wdenke2211742002-11-02 23:30:20 +0000148/*
149 * Low Level Configuration Settings
150 * (address mappings, register initial values, etc.)
151 * You should know what you are doing if you make changes here.
152 */
153
154/*-----------------------------------------------------------------------
155 * Physical Memory Map
156 */
157#define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
158#define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
159
160#define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
161#define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
162
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200163#define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
164#define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
wdenke2211742002-11-02 23:30:20 +0000165
166/*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
167/*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
168
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200169#define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
170#define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
wdenke2211742002-11-02 23:30:20 +0000171
172/*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
173/*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
174
175#define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
176#define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
177
178#define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
179#define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
180
181#define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
182
183#define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
184#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_IMMR PHYS_IMMR
wdenke2211742002-11-02 23:30:20 +0000187
188/*-----------------------------------------------------------------------
189 * Reset Address
190 *
191 * In order to reset the CPU, U-Boot jumps to a special address which
192 * causes a machine check exception. The default address for this is
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
wdenke2211742002-11-02 23:30:20 +0000194 * testing the monitor in RAM using a JTAG debugger.
195 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 * Just set CONFIG_SYS_RESET_ADDRESS to an address that you know is sure to
wdenke2211742002-11-02 23:30:20 +0000197 * cause a bus error on your hardware.
198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_RESET_ADDRESS 0x20000000
wdenke2211742002-11-02 23:30:20 +0000200
201/*-----------------------------------------------------------------------
202 * Hard Reset Configuration Words
203 */
204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#if defined(CONFIG_SYS_RSD_BOOT_LOW)
206# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenke2211742002-11-02 23:30:20 +0000207#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208# define CONFIG_SYS_RSD_HRCW_BOOT_FLAGS (0)
209#endif /* defined(CONFIG_SYS_RSD_BOOT_LOW) */
wdenke2211742002-11-02 23:30:20 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211/* get the HRCW ISB field from CONFIG_SYS_IMMR */
212#define CONFIG_SYS_RSD_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
213 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) |\
214 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenke2211742002-11-02 23:30:20 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_HRCW_MASTER (HRCW_L2CPC10 | \
wdenke2211742002-11-02 23:30:20 +0000217 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 CONFIG_SYS_RSD_HRCW_IMMR |\
wdenk8bde7f72003-06-27 21:31:46 +0000219 HRCW_MMR00 | \
220 HRCW_APPC10 | \
221 HRCW_CS10PC00 | \
222 HRCW_MODCK_H0000 |\
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223 CONFIG_SYS_RSD_HRCW_BOOT_FLAGS)
wdenke2211742002-11-02 23:30:20 +0000224
225/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_HRCW_SLAVE1 0
227#define CONFIG_SYS_HRCW_SLAVE2 0
228#define CONFIG_SYS_HRCW_SLAVE3 0
229#define CONFIG_SYS_HRCW_SLAVE4 0
230#define CONFIG_SYS_HRCW_SLAVE5 0
231#define CONFIG_SYS_HRCW_SLAVE6 0
232#define CONFIG_SYS_HRCW_SLAVE7 0
wdenke2211742002-11-02 23:30:20 +0000233
234/*-----------------------------------------------------------------------
235 * Definitions for initial stack pointer and data area (in DPRAM)
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200238#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200239#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000241
242/*-----------------------------------------------------------------------
243 * Start addresses for the final memory configuration
244 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
246 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependend.
wdenke2211742002-11-02 23:30:20 +0000247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_60X
249#define CONFIG_SYS_FLASH_BASE PHYS_FLASH
250/*#define CONFIG_SYS_MONITOR_BASE 0x200000 */
251#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
252#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
253#define CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000254#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */
256#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000257
258/*
259 * For booting Linux, the board info and command line data
260 * have to be in the first 8 MB of memory, since this is
261 * the maximum mapped by the Linux kernel during initialization.
262 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000264
265/*-----------------------------------------------------------------------
266 * FLASH and environment organization
267 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
269#define CONFIG_SYS_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
272#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000273
274/* turn off NVRAM env feature */
275#undef CONFIG_NVRAM_ENV
276
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200277#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200278#define CONFIG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
279#define CONFIG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000280
281/*-----------------------------------------------------------------------
282 * Cache Configuration
283 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500285#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000287#endif
288
289/*-----------------------------------------------------------------------
290 * HIDx - Hardware Implementation-dependent Registers 2-11
291 *-----------------------------------------------------------------------
292 * HID0 also contains cache control - initially enable both caches and
293 * invalidate contents, then the final state leaves only the instruction
294 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
295 * but Soft reset does not.
296 *
297 * HID1 has only read-only information - nothing to set.
298 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
300#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
301#define CONFIG_SYS_HID2 0
wdenke2211742002-11-02 23:30:20 +0000302
303/*-----------------------------------------------------------------------
304 * RMR - Reset Mode Register
305 *-----------------------------------------------------------------------
306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_RMR 0
wdenke2211742002-11-02 23:30:20 +0000308
309/*-----------------------------------------------------------------------
310 * BCR - Bus Configuration 4-25
311 *-----------------------------------------------------------------------
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_BCR 0x100c0000
wdenke2211742002-11-02 23:30:20 +0000314
315/*-----------------------------------------------------------------------
316 * SIUMCR - SIU Module Configuration 4-31
317 *-----------------------------------------------------------------------
318 */
319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
wdenke2211742002-11-02 23:30:20 +0000321 SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
322
323/*-----------------------------------------------------------------------
324 * SYPCR - System Protection Control 11-9
325 * SYPCR can only be written once after reset!
326 *-----------------------------------------------------------------------
327 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
wdenke2211742002-11-02 23:30:20 +0000330 SYPCR_SWRI | SYPCR_SWP)
331
332/*-----------------------------------------------------------------------
333 * TMCNTSC - Time Counter Status and Control 4-40
334 *-----------------------------------------------------------------------
335 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
336 * and enable Time Counter
337 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
wdenke2211742002-11-02 23:30:20 +0000339
340/*-----------------------------------------------------------------------
341 * PISCR - Periodic Interrupt Status and Control 4-42
342 *-----------------------------------------------------------------------
343 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
344 * Periodic timer
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000347
348/*-----------------------------------------------------------------------
349 * SCCR - System Clock Control 9-8
350 *-----------------------------------------------------------------------
351 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_SCCR 0x00000000
wdenke2211742002-11-02 23:30:20 +0000353
354/*-----------------------------------------------------------------------
355 * RCCR - RISC Controller Configuration 13-7
356 *-----------------------------------------------------------------------
357 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_RCCR 0
wdenke2211742002-11-02 23:30:20 +0000359
360/*
361 * Init Memory Controller:
362 */
363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_PSDMR 0x494D2452
365#define CONFIG_SYS_LSDMR 0x49492552
wdenke2211742002-11-02 23:30:20 +0000366
367/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_BR0_PRELIM (PHYS_FLASH | BRx_V)
369#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000370 ORxG_BCTLD | \
371 ORxG_SCY_5_CLK)
372
373/* DPRAM to the PCI BUS on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
375#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000376 ORxG_ACS_DIV4)
377
378/* 60x Bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
380#define CONFIG_SYS_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000381 ORxS_BPD_4 | \
382 ORxS_ROWST_PBI1_A2 | \
383 ORxS_NUMR_13 | \
384 ORxS_IBID)
385
386/* Virtex-FPGA - Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V)
388#define CONFIG_SYS_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
wdenk8bde7f72003-06-27 21:31:46 +0000389 ORxG_SCY_1_CLK | \
390 ORxG_ACS_DIV2 | \
391 ORxG_CSNT )
wdenke2211742002-11-02 23:30:20 +0000392
393/* local bus SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
395#define CONFIG_SYS_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000396 ORxS_BPD_4 | \
397 ORxS_ROWST_PBI1_A4 | \
398 ORxS_NUMR_13)
399
400/* DPRAM to the Sharc-Bus on the protocol board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
402#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
wdenke2211742002-11-02 23:30:20 +0000403 ORxG_ACS_DIV4)
404
wdenke2211742002-11-02 23:30:20 +0000405#endif /* __CONFIG_H */