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Dirk Eibach2da0fc02011-01-21 09:31:21 +01001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach2da0fc02011-01-21 09:31:21 +01006 */
7
8#ifndef __GDSYS_FPGA_H
9#define __GDSYS_FPGA_H
10
Dirk Eibach255ef4d2011-10-20 11:12:55 +020011int init_func_fpga(void);
12
Dirk Eibach2da0fc02011-01-21 09:31:21 +010013enum {
14 FPGA_STATE_DONE_FAILED = 1 << 0,
15 FPGA_STATE_REFLECTION_FAILED = 1 << 1,
Dirk Eibach255ef4d2011-10-20 11:12:55 +020016 FPGA_STATE_PLATFORM = 1 << 2,
Dirk Eibach2da0fc02011-01-21 09:31:21 +010017};
18
19int get_fpga_state(unsigned dev);
20void print_fpga_state(unsigned dev);
21
Dirk Eibachaba27ac2013-06-26 16:04:26 +020022int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
23int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
24
25extern struct ihs_fpga *fpga_ptr[];
26
27#define FPGA_SET_REG(ix, fld, val) \
28 fpga_set_reg((ix), \
29 &fpga_ptr[ix]->fld, \
30 offsetof(struct ihs_fpga, fld), \
31 val)
32
33#define FPGA_GET_REG(ix, fld, val) \
34 fpga_get_reg((ix), \
35 &fpga_ptr[ix]->fld, \
36 offsetof(struct ihs_fpga, fld), \
37 val)
38
Dirk Eibach0e60aa82012-04-27 10:33:46 +020039struct ihs_gpio {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010040 u16 read;
41 u16 clear;
42 u16 set;
Dirk Eibach0e60aa82012-04-27 10:33:46 +020043};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010044
Dirk Eibach0e60aa82012-04-27 10:33:46 +020045struct ihs_i2c {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010046 u16 write_mailbox;
47 u16 write_mailbox_ext;
48 u16 read_mailbox;
49 u16 read_mailbox_ext;
Dirk Eibach0e60aa82012-04-27 10:33:46 +020050};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010051
Dirk Eibach0e60aa82012-04-27 10:33:46 +020052struct ihs_osd {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010053 u16 version;
54 u16 features;
55 u16 control;
56 u16 xy_size;
Dirk Eibach52158e32011-04-06 13:53:47 +020057 u16 xy_scale;
58 u16 x_pos;
59 u16 y_pos;
Dirk Eibach0e60aa82012-04-27 10:33:46 +020060};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010061
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000062#ifdef CONFIG_NEO
Dirk Eibach0e60aa82012-04-27 10:33:46 +020063struct ihs_fpga {
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000064 u16 reflection_low; /* 0x0000 */
65 u16 versions; /* 0x0002 */
66 u16 fpga_features; /* 0x0004 */
67 u16 fpga_version; /* 0x0006 */
68 u16 reserved_0[8187]; /* 0x0008 */
69 u16 reflection_high; /* 0x3ffe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +020070};
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000071#endif
72
Dirk Eibach2da0fc02011-01-21 09:31:21 +010073#ifdef CONFIG_IO
Dirk Eibach0e60aa82012-04-27 10:33:46 +020074struct ihs_fpga {
Dirk Eibach2da0fc02011-01-21 09:31:21 +010075 u16 reflection_low; /* 0x0000 */
76 u16 versions; /* 0x0002 */
77 u16 fpga_features; /* 0x0004 */
78 u16 fpga_version; /* 0x0006 */
79 u16 reserved_0[5]; /* 0x0008 */
80 u16 quad_serdes_reset; /* 0x0012 */
81 u16 reserved_1[8181]; /* 0x0014 */
82 u16 reflection_high; /* 0x3ffe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +020083};
Dirk Eibach2da0fc02011-01-21 09:31:21 +010084#endif
85
Dirk Eibach255ef4d2011-10-20 11:12:55 +020086#ifdef CONFIG_IO64
Dirk Eibachaba27ac2013-06-26 16:04:26 +020087
88struct ihs_fpga_channel {
89 u16 status_int;
90 u16 config_int;
91 u16 switch_connect_config;
92 u16 tx_destination;
93};
94
95struct ihs_fpga_hicb {
96 u16 status_int;
97 u16 config_int;
98};
99
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200100struct ihs_fpga {
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200101 u16 reflection_low; /* 0x0000 */
102 u16 versions; /* 0x0002 */
103 u16 fpga_features; /* 0x0004 */
104 u16 fpga_version; /* 0x0006 */
105 u16 reserved_0[5]; /* 0x0008 */
106 u16 quad_serdes_reset; /* 0x0012 */
107 u16 reserved_1[502]; /* 0x0014 */
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200108 struct ihs_fpga_channel ch[32]; /* 0x0400 */
109 struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */
110 u16 reserved_2[7487]; /* 0x0580 */
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200111 u16 reflection_high; /* 0x3ffe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200112};
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200113#endif
114
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100115#ifdef CONFIG_IOCON
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200116struct ihs_fpga {
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100117 u16 reflection_low; /* 0x0000 */
118 u16 versions; /* 0x0002 */
119 u16 fpga_version; /* 0x0004 */
120 u16 fpga_features; /* 0x0006 */
121 u16 reserved_0[6]; /* 0x0008 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200122 struct ihs_gpio gpio; /* 0x0014 */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100123 u16 mpc3w_control; /* 0x001a */
124 u16 reserved_1[19]; /* 0x001c */
125 u16 videocontrol; /* 0x0042 */
Dirk Eibache50e8962013-07-25 19:28:13 +0200126 u16 reserved_2[14]; /* 0x0044 */
127 u16 mc_int; /* 0x0060 */
128 u16 mc_int_en; /* 0x0062 */
129 u16 mc_status; /* 0x0064 */
130 u16 mc_control; /* 0x0066 */
131 u16 mc_tx_data; /* 0x0068 */
132 u16 mc_tx_address; /* 0x006a */
133 u16 mc_tx_cmd; /* 0x006c */
134 u16 mc_res; /* 0x006e */
135 u16 mc_rx_cmd_status; /* 0x0070 */
136 u16 mc_rx_data; /* 0x0072 */
137 u16 reserved_3[69]; /* 0x0074 */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100138 u16 reflection_high; /* 0x00fe */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200139 struct ihs_osd osd; /* 0x0100 */
Dirk Eibache50e8962013-07-25 19:28:13 +0200140 u16 reserved_4[889]; /* 0x010e */
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200141 u16 videomem[31736]; /* 0x0800 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200142};
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100143#endif
144
145#ifdef CONFIG_DLVISION_10G
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200146struct ihs_fpga {
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100147 u16 reflection_low; /* 0x0000 */
148 u16 versions; /* 0x0002 */
149 u16 fpga_version; /* 0x0004 */
150 u16 fpga_features; /* 0x0006 */
151 u16 reserved_0[10]; /* 0x0008 */
152 u16 extended_interrupt; /* 0x001c */
153 u16 reserved_1[9]; /* 0x001e */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200154 struct ihs_i2c i2c; /* 0x0030 */
Dirk Eibach7749c842011-04-06 13:53:48 +0200155 u16 reserved_2[16]; /* 0x0038 */
156 u16 mpc3w_control; /* 0x0058 */
157 u16 reserved_3[34]; /* 0x005a */
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100158 u16 videocontrol; /* 0x009e */
Dirk Eibach7749c842011-04-06 13:53:48 +0200159 u16 reserved_4[176]; /* 0x00a0 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200160 struct ihs_osd osd; /* 0x0200 */
Dirk Eibach7749c842011-04-06 13:53:48 +0200161 u16 reserved_5[761]; /* 0x020e */
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200162 u16 videomem[31736]; /* 0x0800 */
Dirk Eibach0e60aa82012-04-27 10:33:46 +0200163};
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100164#endif
165
166#endif