Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 1bc4e8eb1d7f0eb49240a5b5ba5714b925147641 / . / configs / orangepi-r1-plus-rk3328_defconfig
blob: c5afe5ea6e5c180d76d6b00201fbbf4ef8e84178 [file] [log] [blame]
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]1CONFIG_ARM=y
2CONFIG_SKIP_LOWLEVEL_INIT=y
3CONFIG_COUNTER_FREQUENCY=24000000
4CONFIG_ARCH_ROCKCHIP=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]5CONFIG_SPL_GPIO=y
6CONFIG_NR_DRAM_BANKS=1
Tom Rinidf896742023-08-07 15:17:12 -0400[diff] [blame]7CONFIG_SF_DEFAULT_SPEED=20000000
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]8CONFIG_ENV_OFFSET=0x3F8000
9CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
10CONFIG_DM_RESET=y
11CONFIG_ROCKCHIP_RK3328=y
Jonas Karlmanaa321d42024-02-17 00:22:41 +0000[diff] [blame]12CONFIG_ROCKCHIP_SPI_IMAGE=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]13CONFIG_DEBUG_UART_BASE=0xFF130000
14CONFIG_DEBUG_UART_CLOCK=24000000
Jonas Karlmanaa321d42024-02-17 00:22:41 +0000[diff] [blame]15CONFIG_SPL_SPI_FLASH_SUPPORT=y
16CONFIG_SPL_SPI=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]17CONFIG_SYS_LOAD_ADDR=0x800800
18CONFIG_DEBUG_UART=y
19# CONFIG_ANDROID_BOOT_IMAGE is not set
20CONFIG_FIT=y
21CONFIG_FIT_VERBOSE=y
Jonas Karlmanf652b252024-02-17 00:22:33 +0000[diff] [blame]22CONFIG_SPL_FIT_SIGNATURE=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]23CONFIG_SPL_LOAD_FIT=y
Jonas Karlmanf652b252024-02-17 00:22:33 +0000[diff] [blame]24CONFIG_LEGACY_IMAGE_FORMAT=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]25CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
26# CONFIG_DISPLAY_CPUINFO is not set
27CONFIG_DISPLAY_BOARDINFO_LATE=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]28CONFIG_SPL_MAX_SIZE=0x40000
29CONFIG_SPL_PAD_TO=0x7f8000
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]30# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]31CONFIG_SPL_POWER=y
Jonas Karlmanaa321d42024-02-17 00:22:41 +0000[diff] [blame]32CONFIG_SPL_SPI_LOAD=y
33CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]34CONFIG_SPL_ATF=y
35CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]36CONFIG_CMD_BOOTZ=y
Jonas Karlmanf652b252024-02-17 00:22:33 +0000[diff] [blame]37CONFIG_CMD_GPIO=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]38CONFIG_CMD_GPT=y
39CONFIG_CMD_MMC=y
40CONFIG_CMD_USB=y
Jonas Karlman1bc4e8e2024-03-10 18:51:00 +0000[diff] [blame^]41CONFIG_CMD_ROCKUSB=y
42CONFIG_CMD_USB_MASS_STORAGE=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]43# CONFIG_CMD_SETEXPR is not set
44CONFIG_CMD_TIME=y
Jonas Karlmanf652b252024-02-17 00:22:33 +0000[diff] [blame]45CONFIG_CMD_REGULATOR=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]46CONFIG_SPL_OF_CONTROL=y
47CONFIG_TPL_OF_CONTROL=y
48CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
49CONFIG_TPL_OF_PLATDATA=y
50CONFIG_ENV_IS_IN_MMC=y
51CONFIG_SYS_RELOC_GD_ENV_ADDR=y
52CONFIG_SYS_MMC_ENV_DEV=1
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]53CONFIG_TPL_DM=y
Jonas Karlmanf652b252024-02-17 00:22:33 +0000[diff] [blame]54CONFIG_SPL_DM_SEQ_ALIAS=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]55CONFIG_REGMAP=y
56CONFIG_SPL_REGMAP=y
57CONFIG_TPL_REGMAP=y
58CONFIG_SYSCON=y
59CONFIG_SPL_SYSCON=y
60CONFIG_TPL_SYSCON=y
61CONFIG_CLK=y
62CONFIG_SPL_CLK=y
63CONFIG_FASTBOOT_BUF_ADDR=0x800800
64CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
65CONFIG_ROCKCHIP_GPIO=y
66CONFIG_SYS_I2C_ROCKCHIP=y
67CONFIG_MMC_DW=y
68CONFIG_MMC_DW_ROCKCHIP=y
Jonas Karlmanaa321d42024-02-17 00:22:41 +0000[diff] [blame]69CONFIG_SPI_FLASH_SFDP_SUPPORT=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]70CONFIG_SPI_FLASH_GIGADEVICE=y
Jonas Karlmanaa321d42024-02-17 00:22:41 +0000[diff] [blame]71CONFIG_SPI_FLASH_MACRONIX=y
72CONFIG_SPI_FLASH_WINBOND=y
73CONFIG_SPI_FLASH_XMC=y
74CONFIG_SPI_FLASH_ZBIT=y
Jonas Karlmanf652b252024-02-17 00:22:33 +0000[diff] [blame]75CONFIG_PHY_MOTORCOMM=y
76CONFIG_PHY_REALTEK=y
77CONFIG_DM_MDIO=y
78CONFIG_DM_ETH_PHY=y
79CONFIG_PHY_GIGE=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]80CONFIG_ETH_DESIGNWARE=y
81CONFIG_GMAC_ROCKCHIP=y
Jonas Karlmanf652b252024-02-17 00:22:33 +0000[diff] [blame]82CONFIG_PHY_ROCKCHIP_INNO_USB2=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]83CONFIG_PINCTRL=y
84CONFIG_SPL_PINCTRL=y
85CONFIG_DM_PMIC=y
86CONFIG_PMIC_RK8XX=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]87CONFIG_SPL_DM_REGULATOR=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]88CONFIG_DM_REGULATOR_FIXED=y
89CONFIG_SPL_DM_REGULATOR_FIXED=y
90CONFIG_REGULATOR_RK8XX=y
91CONFIG_PWM_ROCKCHIP=y
92CONFIG_RAM=y
93CONFIG_SPL_RAM=y
94CONFIG_TPL_RAM=y
Jonas Karlmanf652b252024-02-17 00:22:33 +0000[diff] [blame]95CONFIG_DM_RNG=y
96CONFIG_RNG_ROCKCHIP=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]97CONFIG_BAUDRATE=1500000
98CONFIG_DEBUG_UART_SHIFT=2
99CONFIG_SYS_NS16550_MEM32=y
100CONFIG_ROCKCHIP_SPI=y
101CONFIG_SYSINFO=y
102CONFIG_SYSRESET=y
103# CONFIG_TPL_SYSRESET is not set
104CONFIG_USB=y
Jonas Karlman1bc4e8e2024-03-10 18:51:00 +0000[diff] [blame^]105CONFIG_DM_USB_GADGET=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]106CONFIG_USB_XHCI_HCD=y
Jonas Karlman1bc4e8e2024-03-10 18:51:00 +0000[diff] [blame^]107CONFIG_USB_XHCI_DWC3=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]108CONFIG_USB_EHCI_HCD=y
109CONFIG_USB_EHCI_GENERIC=y
110CONFIG_USB_OHCI_HCD=y
111CONFIG_USB_OHCI_GENERIC=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]112CONFIG_USB_DWC3=y
113# CONFIG_USB_DWC3_GADGET is not set
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]114CONFIG_USB_GADGET=y
115CONFIG_USB_GADGET_DWC2_OTG=y
Jonas Karlman1bc4e8e2024-03-10 18:51:00 +0000[diff] [blame^]116CONFIG_USB_FUNCTION_ROCKUSB=y
Tianling Shen69e16c72023-05-20 19:20:49 +0800[diff] [blame]117CONFIG_SPL_TINY_MEMSET=y
118CONFIG_TPL_TINY_MEMSET=y
119CONFIG_ERRNO_STR=y