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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbell643cf0e2014-05-05 11:52:23 +01002/*
3 * (C) Copyright 2007-2012
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Tom Cubie <tangliang@allwinnertech.com>
6 *
7 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Ian Campbell643cf0e2014-05-05 11:52:23 +01008 */
9
10#include <common.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
Hans de Goedea93b0fe2016-03-16 20:57:28 +010013#include <asm/arch/prcm.h>
Philipp Tomsichea1af9f2016-10-28 18:21:29 +080014#include <asm/arch/gtbus.h>
Ian Campbell643cf0e2014-05-05 11:52:23 +010015#include <asm/arch/sys_proto.h>
16
Chen-Yu Tsaied805842016-01-06 15:13:07 +080017__weak void clock_init_sec(void)
18{
19}
20
Philipp Tomsichea1af9f2016-10-28 18:21:29 +080021__weak void gtbus_init(void)
22{
23}
24
Ian Campbell643cf0e2014-05-05 11:52:23 +010025int clock_init(void)
26{
27#ifdef CONFIG_SPL_BUILD
28 clock_init_safe();
Philipp Tomsichea1af9f2016-10-28 18:21:29 +080029 gtbus_init();
Ian Campbell643cf0e2014-05-05 11:52:23 +010030#endif
31 clock_init_uart();
Chen-Yu Tsaied805842016-01-06 15:13:07 +080032 clock_init_sec();
Ian Campbell643cf0e2014-05-05 11:52:23 +010033
34 return 0;
35}
Hans de Goedea93b0fe2016-03-16 20:57:28 +010036
37/* These functions are shared between various SoCs so put them here. */
Icenowy Zhengcfe673c2022-01-29 10:23:07 -050038#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I && \
39 !defined CONFIG_MACH_SUNIV
Hans de Goedea93b0fe2016-03-16 20:57:28 +010040int clock_twi_onoff(int port, int state)
41{
42 struct sunxi_ccm_reg *const ccm =
43 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
44
45 if (port == 5) {
46 if (state)
47 prcm_apb0_enable(
48 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
49 else
50 prcm_apb0_disable(
51 PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
52 return 0;
53 }
54
55 /* set the apb clock gate and reset for twi */
56 if (state) {
57 setbits_le32(&ccm->apb2_gate,
58 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
59 setbits_le32(&ccm->apb2_reset_cfg,
60 1 << (APB2_RESET_TWI_SHIFT + port));
61 } else {
62 clrbits_le32(&ccm->apb2_reset_cfg,
63 1 << (APB2_RESET_TWI_SHIFT + port));
64 clrbits_le32(&ccm->apb2_gate,
65 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
66 }
67
68 return 0;
69}
70#endif