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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
wdenke2211742002-11-02 23:30:20 +000031#undef DEBUG
32#define GTREGREAD(x) 0xffffffff /* needed for debug */
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39/* these hardware addresses are pretty bogus, please change them to
40 suit your needs */
41
42/* first ethernet */
43#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
44
45#define CONFIG_IPADDR 192.168.0.105
46#define CONFIG_SERVERIP 192.168.0.100
47
48#define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */
49
50#define CONFIG_BAUDRATE 9600 /* console baudrate */
51
52#undef CONFIG_WATCHDOG
53
54#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
55
56#define CONFIG_ZERO_BOOTDELAY_CHECK
57
58#undef CONFIG_BOOTARGS
59#define CONFIG_BOOTCOMMAND \
60 "bootp 1000000; " \
61 "setenv bootargs root=ramfs console=ttyS00,9600 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
63 "${netmask}:${hostname}:eth0:none; " \
wdenke2211742002-11-02 23:30:20 +000064 "bootm"
65
66#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
67#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
68
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050069/*
70 * BOOTP options
71 */
72#define CONFIG_BOOTP_SUBNETMASK
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75#define CONFIG_BOOTP_BOOTPATH
76
77#define CONFIG_BOOTP_BOOTFILESIZE
78
wdenke2211742002-11-02 23:30:20 +000079
Jon Loeligerde8b2a62007-07-05 19:32:07 -050080/*
81 * Command line configuration.
82 */
83#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +000084
Jon Loeligerde8b2a62007-07-05 19:32:07 -050085#define CONFIG_CMD_PCI
86#define CONFIG_CMD_JFFS2
Wolfgang Denk5728be32007-08-06 01:01:49 +020087#define CONFIG_CMD_SCSI
Jon Loeligerde8b2a62007-07-05 19:32:07 -050088#define CONFIG_CMD_IDE
Wolfgang Denk5728be32007-08-06 01:01:49 +020089#define CONFIG_CMD_DATE
90#define CONFIG_CMD_FDC
Jon Loeligerde8b2a62007-07-05 19:32:07 -050091#define CONFIG_CMD_ELF
92
wdenke2211742002-11-02 23:30:20 +000093
94/*
95 * Miscellaneous configurable options
96 */
97#define CFG_LONGHELP /* undef to save memory */
98#define CFG_PROMPT "=> " /* Monitor Command Prompt */
99
100/*
101 * choose between COM1 and COM2 as serial console
102 */
103#define CONFIG_CONS_INDEX 1
104
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500105#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000106#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
107#else
108#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
109#endif
110#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
111#define CFG_MAXARGS 16 /* max number of command args */
112#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
113
114#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
115#define CFG_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
116
117#define CFG_LOAD_ADDR 0x1000000 /* default load address */
118
119#define CFG_HZ 1000 /* dec. freq: 1 ms ticks */
120
121#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
122
123/*
124 * Low Level Configuration Settings
125 * (address mappings, register initial values, etc.)
126 * You should know what you are doing if you make changes here.
127 */
128#define CFG_BOARD_ASM_INIT
129#define CONFIG_MISC_INIT_R
130
131/*
132 * Choose the address mapping scheme for the MPC106 mem controller.
133 * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
134 */
135#define CFG_ADDRESS_MAP_A
136#ifdef CFG_ADDRESS_MAP_A
137
138#define CFG_PCI_MEMORY_BUS 0x80000000
139#define CFG_PCI_MEMORY_PHYS 0x00000000
140#define CFG_PCI_MEMORY_SIZE 0x80000000
141
142#define CFG_PCI_MEM_BUS 0x00000000
143#define CFG_PCI_MEM_PHYS 0xc0000000
144#define CFG_PCI_MEM_SIZE 0x3f000000
145
146#define CFG_ISA_MEM_BUS 0
147#define CFG_ISA_MEM_PHYS 0
148#define CFG_ISA_MEM_SIZE 0
149
150#define CFG_PCI_IO_BUS 0x1000
151#define CFG_PCI_IO_PHYS 0x81000000
152#define CFG_PCI_IO_SIZE 0x01000000-CFG_PCI_IO_BUS
153
154#define CFG_ISA_IO_BUS 0x00000000
155#define CFG_ISA_IO_PHYS 0x80000000
156#define CFG_ISA_IO_SIZE 0x00800000
157
158#else
159
160#define CFG_PCI_MEMORY_BUS 0x00000000
161#define CFG_PCI_MEMORY_PHYS 0x00000000
162#define CFG_PCI_MEMORY_SIZE 0x40000000
163
164#define CFG_PCI_MEM_BUS 0x80000000
165#define CFG_PCI_MEM_PHYS 0x80000000
166#define CFG_PCI_MEM_SIZE 0x7d000000
167
168#define CFG_ISA_MEM_BUS 0x00000000
169#define CFG_ISA_MEM_PHYS 0xfd000000
170#define CFG_ISA_MEM_SIZE 0x01000000
171
172#define CFG_PCI_IO_BUS 0x00800000
173#define CFG_PCI_IO_PHYS 0xfe800000
174#define CFG_PCI_IO_SIZE 0x00400000
175
176#define CFG_ISA_IO_BUS 0x00000000
177#define CFG_ISA_IO_PHYS 0xfe000000
178#define CFG_ISA_IO_SIZE 0x00800000
179
180#endif /*CFG_ADDRESS_MAP_A */
181
182#define CFG_60X_PCI_MEM_OFFSET 0x00000000
183
184/* driver defines FDC,IDE,... */
185#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
186#define CFG_ISA_IO CFG_ISA_IO_PHYS
187#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
188
189/*
190 * Start addresses for the final memory configuration
191 * (Set up by the startup code)
192 * Please note that CFG_SDRAM_BASE _must_ start at 0
193 */
194#define CFG_SDRAM_BASE 0x00000000
195#define CFG_FLASH_BASE 0xfff00000
196
197/*
198 * Definitions for initial stack pointer and data area
199 */
200#define CFG_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
201#define CFG_INIT_RAM_END 0x4000
202#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for init data */
203#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
204#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
205
206/*
207 * Flash mapping/organization on the MPC10x.
208 */
209#define FLASH_BASE0_PRELIM 0xff800000
210#define FLASH_BASE1_PRELIM 0xffc00000
211
212#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
213#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
214
215#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
216#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
217
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200218/*
219 * JFFS2 partitions
220 *
221 */
222/* No command line, one static partition */
223#undef CONFIG_JFFS2_CMDLINE
224#define CONFIG_JFFS2_DEV "nor"
225#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
226#define CONFIG_JFFS2_PART_OFFSET 0x00000000
227
228/* mtdparts command line support
229 *
230 * Note: fake mtd_id used, no linux mtd map file
231 */
232/*
233#define CONFIG_JFFS2_CMDLINE
234#define MTDIDS_DEFAULT "nor0=bab7xx-0"
235#define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)"
236*/
wdenke2211742002-11-02 23:30:20 +0000237
238#define CFG_MONITOR_BASE CFG_FLASH_BASE
239#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
240#define CFG_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
241#undef CFG_MEMTEST
242
243/*
244 * Environment settings
245 */
246#define CONFIG_ENV_OVERWRITE
247#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
248#define CFG_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
249#define CFG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
250/*
251 * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
252 * user applications can use the remaining space for other purposes.
253 */
254#define CFG_ENV_ADDR (CFG_NVRAM_SIZE +0x10 -0x800)
255#define CFG_NV_SROM_COPY_ADDR (CFG_NVRAM_SIZE +0x10 -0x400)
256#define CFG_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */
257#define CFG_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
258
259/*
260 * Serial devices
261 */
262#define CFG_NS16550
263#define CFG_NS16550_SERIAL
264#define CFG_NS16550_REG_SIZE 1
265#define CFG_NS16550_CLK 1843200
266#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
267#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
268
269/*
270 * PCI stuff
271 */
272#define CONFIG_PCI /* include pci support */
273#define CONFIG_PCI_PNP /* pci plug-and-play */
274#define CONFIG_PCI_HOST PCI_HOST_AUTO
275#undef CONFIG_PCI_SCAN_SHOW
276
277/*
278 * Video console (graphic: SMI LynxEM, keyboard: i8042)
279 */
280#define CONFIG_VIDEO
281#define CONFIG_CFB_CONSOLE
282#define CONFIG_VIDEO_SMI_LYNXEM
283#define CONFIG_I8042_KBD
284#define CONFIG_VIDEO_LOGO
285#define CONFIG_CONSOLE_TIME
286#define CONFIG_CONSOLE_EXTRA_INFO
287#define CONFIG_CONSOLE_CURSOR
288#define CFG_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */
289
290/*
291 * IDE/SCSI globals
292 */
293#ifndef __ASSEMBLY__
294extern unsigned int eltec_board;
295extern unsigned int ata_reset_time;
296extern unsigned int scsi_reset_time;
297extern unsigned short scsi_dev_id;
298extern unsigned int scsi_max_scsi_id;
299extern unsigned char scsi_sym53c8xx_ccf;
300#endif
301
302/*
303 * ATAPI Support (experimental)
304 */
305#define CONFIG_ATAPI
306#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
307#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
308
309#define CFG_ATA_BASE_ADDR CFG_60X_PCI_IO_OFFSET /* base address */
310#define CFG_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */
311#define CFG_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
312#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
313#define CFG_ATA_REG_OFFSET 0 /* reg offset */
314#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
315
316#define ATA_RESET_TIME (ata_reset_time)
317
318#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
319#undef CONFIG_IDE_LED /* no led for ide supported */
320
321/*
322 * SCSI support (experimental) only SYM53C8xx supported
323 */
324#define CONFIG_SCSI_SYM53C8XX
325#define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */
326#define CFG_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */
327#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
328#define CFG_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */
329#define CFG_SCSI_MAX_DEVICE (15 * CFG_SCSI_MAX_LUN) /* max. Target devices */
330#define CFG_SCSI_SPIN_UP_TIME (scsi_reset_time)
331
332/*
333 * Partion suppport
334 */
335#define CONFIG_DOS_PARTITION
336#define CONFIG_MAC_PARTITION
337#define CONFIG_ISO_PARTITION
338
339/*
340 * Winbond Configuration
341 */
342#define CFG_WINBOND_83C553 1 /* has a winbond bridge */
343#define CFG_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */
344#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */
345#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */
346
347/*
348 * NS87308 Configuration
349 */
350#define CFG_NS87308 /* Nat Semi super-io cntr on ISA bus */
351#define CFG_NS87308_BADDR_10 1
352#define CFG_NS87308_DEVS (CFG_NS87308_UART1 | \
wdenk8bde7f72003-06-27 21:31:46 +0000353 CFG_NS87308_UART2 | \
354 CFG_NS87308_KBC1 | \
355 CFG_NS87308_MOUSE | \
356 CFG_NS87308_FDC | \
357 CFG_NS87308_RARP | \
358 CFG_NS87308_GPIO | \
359 CFG_NS87308_POWRMAN | \
360 CFG_NS87308_RTC_APC )
wdenke2211742002-11-02 23:30:20 +0000361
362#define CFG_NS87308_PS2MOD
363#define CFG_NS87308_GPIO_BASE 0x0220
364#define CFG_NS87308_PWMAN_BASE 0x0460
365#define CFG_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */
366
367/*
368 * set up the NVRAM access registers
369 * NVRAM's controlled by the configurable CS line from the 87308
370 */
371#define CFG_NS87308_CS0_BASE 0x0076
372#define CFG_NS87308_CS0_CONF 0x40
373#define CFG_NS87308_CS1_BASE 0x0070
374#define CFG_NS87308_CS1_CONF 0x1C
375#define CFG_NS87308_CS2_BASE 0x0071
376#define CFG_NS87308_CS2_CONF 0x1C
377
378#define CONFIG_RTC_MK48T59
379
380/*
381 * Initial BATs
382 */
383#if 1
384
385#define CFG_IBAT0L 0
386#define CFG_IBAT0U 0
387#define CFG_DBAT0L CFG_IBAT1L
388#define CFG_DBAT0U CFG_IBAT1U
389
390#define CFG_IBAT1L 0
391#define CFG_IBAT1U 0
392#define CFG_DBAT1L CFG_IBAT1L
393#define CFG_DBAT1U CFG_IBAT1U
394
395#define CFG_IBAT2L 0
396#define CFG_IBAT2U 0
397#define CFG_DBAT2L CFG_IBAT2L
398#define CFG_DBAT2U CFG_IBAT2U
399
400#define CFG_IBAT3L 0
401#define CFG_IBAT3U 0
402#define CFG_DBAT3L CFG_IBAT3L
403#define CFG_DBAT3U CFG_IBAT3U
404
405#else
406
407/* SDRAM */
408#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
409#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
410#define CFG_DBAT0L CFG_IBAT1L
411#define CFG_DBAT0U CFG_IBAT1U
412
413/* address range for flashes */
414#define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
415#define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
416#define CFG_DBAT1L CFG_IBAT1L
417#define CFG_DBAT1U CFG_IBAT1U
418
419/* ISA IO space */
420#define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
421#define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
422#define CFG_DBAT2L CFG_IBAT2L
423#define CFG_DBAT2U CFG_IBAT2U
424
425/* ISA memory space */
426#define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
427#define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
428#define CFG_DBAT3L CFG_IBAT3L
429#define CFG_DBAT3U CFG_IBAT3U
430
431#endif
432
433/*
434 * Speed settings are board specific
435 */
436#ifndef __ASSEMBLY__
437extern unsigned long bab7xx_get_bus_freq (void);
438extern unsigned long bab7xx_get_gclk_freq (void);
439#endif
440#define CFG_BUS_HZ bab7xx_get_bus_freq()
441#define CFG_BUS_CLK CFG_BUS_HZ
442#define CFG_CPU_CLK bab7xx_get_gclk_freq()
443
444/*
445 * For booting Linux, the board info and command line data
446 * have to be in the first 8 MB of memory, since this is
447 * the maximum mapped by the Linux kernel during initialization.
448 */
449#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
450
451/*
452 * Cache Configuration
453 */
454#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500455#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000456#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
457#endif
458
459/*
460 * L2 Cache Configuration is board specific for BAB740/BAB750
461 * Init values read from revision srom.
462 */
463#undef CFG_L2
464#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
wdenk8bde7f72003-06-27 21:31:46 +0000465 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
wdenke2211742002-11-02 23:30:20 +0000466#define L2_ENABLE (L2_INIT | L2CR_L2E)
467
468#define CFG_L2_BAB7xx
469
470/*
471 * Internal Definitions
472 *
473 * Boot Flags
474 */
475#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
476#define BOOTFLAG_WARM 0x02 /* Software reboot */
477
478
479#define CONFIG_NET_MULTI /* Multi ethernet cards support */
480#define CONFIG_TULIP
481#define CONFIG_TULIP_SELECT_MEDIA
482
483#endif /* __CONFIG_H */