blob: 7240ce12835b57d43f750f2a6d6f0bf7a5fb655d [file] [log] [blame]
wdenkc1896002003-12-28 11:44:59 +00001/*
2 * (C) Copyright 2003
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
6 *
7 * TOP5200 differences from IceCube:
8 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
9 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
10 * 1 SDRAM/DDRAM Bank up to 256 MB
11 * local VPD I2C Bus is software driven and uses
12 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
13 * FLASH is re-located at 0xff000000
14 * Internal regs are at 0xf0000000
wdenkc1896002003-12-28 11:44:59 +000015 * Reset jumps to 0x00000100
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
wdenkcbd8a352004-02-24 02:00:03 +000044#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenkc1896002003-12-28 11:44:59 +000045#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
46#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
47
wdenkd4ca31c2004-01-02 14:00:00 +000048#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenkc1896002003-12-28 11:44:59 +000049
50#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51#define BOOTFLAG_WARM 0x02 /* Software reboot */
52
wdenkc1896002003-12-28 11:44:59 +000053/*
54 * Serial console configuration
55 */
56#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
57#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
58#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
59
60
wdenk4d13cba2004-03-14 14:09:05 +000061#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
wdenkc1896002003-12-28 11:44:59 +000062/*
63 * PCI Mapping:
64 * 0x40000000 - 0x4fffffff - PCI Memory
65 * 0x50000000 - 0x50ffffff - PCI IO Space
66 */
67# define CONFIG_PCI 1
68# define CONFIG_PCI_PNP 1
69# define CONFIG_PCI_SCAN_SHOW 1
70
71# define CONFIG_PCI_MEM_BUS 0x40000000
72# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
73# define CONFIG_PCI_MEM_SIZE 0x10000000
74
75# define CONFIG_PCI_IO_BUS 0x50000000
76# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
77# define CONFIG_PCI_IO_SIZE 0x01000000
78
wdenkc1896002003-12-28 11:44:59 +000079#endif
80
wdenk4d13cba2004-03-14 14:09:05 +000081/* USB */
82#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
83
84# define CONFIG_USB_OHCI
85# define CONFIG_USB_CLOCK 0x0001bbbb
wdenk498b8db2004-04-18 22:26:17 +000086# if defined (CONFIG_EVAL5200)
87# define CONFIG_USB_CONFIG 0x00005100
88# else
89# define CONFIG_USB_CONFIG 0x00001000
90# endif
wdenk4d13cba2004-03-14 14:09:05 +000091# define CONFIG_DOS_PARTITION
92# define CONFIG_USB_STORAGE
93
wdenk4d13cba2004-03-14 14:09:05 +000094#endif
95
96/* IDE */
97#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
wdenk4d13cba2004-03-14 14:09:05 +000098# define CONFIG_DOS_PARTITION
wdenk4d13cba2004-03-14 14:09:05 +000099#endif
100
wdenkc1896002003-12-28 11:44:59 +0000101
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500102/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500103 * BOOTP options
104 */
105#define CONFIG_BOOTP_BOOTFILESIZE
106#define CONFIG_BOOTP_BOOTPATH
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109
110
111/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500112 * Command line configuration.
113 */
114#include <config_cmd_default.h>
115
116#define CONFIG_CMD_ASKENV
117#define CONFIG_CMD_BEDBUG
118#define CONFIG_CMD_DATE
119#define CONFIG_CMD_DHCP
120#define CONFIG_CMD_EEPROM
121#define CONFIG_CMD_ELF
122#define CONFIG_CMD_I2C
123#define CONFIG_CMD_IMMAP
124#define CONFIG_CMD_MII
125#define CONFIG_CMD_REGINFO
126
127#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
128#define CONFIG_CMD_FAT
129#define CONFIG_CMD_IDE
130#define CONFIG_CMD_USB
131#define CONFIG_CMD_PCI
132#endif
133
wdenkc1896002003-12-28 11:44:59 +0000134
135/*
wdenk4d13cba2004-03-14 14:09:05 +0000136 * MUST be low boot - HIGHBOOT is not supported anymore
wdenkd4ca31c2004-01-02 14:00:00 +0000137 */
138#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
139# define CFG_LOWBOOT 1
140# define CFG_LOWBOOT16 1
wdenk4d13cba2004-03-14 14:09:05 +0000141#else
142# error "TEXT_BASE must be 0xff000000"
wdenkd4ca31c2004-01-02 14:00:00 +0000143#endif
144
145/*
wdenkc1896002003-12-28 11:44:59 +0000146 * Autobooting
147 */
148#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkd4ca31c2004-01-02 14:00:00 +0000149
150#define CONFIG_PREBOOT "echo;" \
151 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
152 "echo"
153
154#undef CONFIG_BOOTARGS
155
156#define CONFIG_EXTRA_ENV_SETTINGS \
157 "netdev=eth0\0" \
158 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100159 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000160 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100161 "addip=setenv bootargs ${bootargs} " \
162 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
163 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000164 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100165 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000166 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100167 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
168 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000169 "rootpath=/opt/eldk/ppc_82xx\0" \
170 "bootfile=/tftpboot/MPC5200/uImage\0" \
171 ""
172
173#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkc1896002003-12-28 11:44:59 +0000174
175/*
176 * IPB Bus clocking configuration.
177 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200178#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkd4ca31c2004-01-02 14:00:00 +0000179
wdenkc1896002003-12-28 11:44:59 +0000180/*
181 * I2C configuration
182 */
183/*
184 * EEPROM configuration
185 */
186#define CFG_EEPROM_PAGE_WRITE_BITS 3
187#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
188
189#define CFG_I2C_EEPROM_ADDR_LEN 2
190#define CFG_EEPROM_SIZE 0x2000
wdenkd4ca31c2004-01-02 14:00:00 +0000191
wdenkc1896002003-12-28 11:44:59 +0000192#define CONFIG_ENV_OVERWRITE
193#define CONFIG_MISC_INIT_R
wdenkd4ca31c2004-01-02 14:00:00 +0000194
wdenkc1896002003-12-28 11:44:59 +0000195#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenk4d13cba2004-03-14 14:09:05 +0000196#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
wdenkd4ca31c2004-01-02 14:00:00 +0000197
wdenkc1896002003-12-28 11:44:59 +0000198#if defined (CONFIG_SOFT_I2C)
199# define SDA0 0x40
200# define SCL0 0x80
wdenkd4ca31c2004-01-02 14:00:00 +0000201# define GPIOE0 *((volatile uchar*)(CFG_MBAR+0x0c00))
202# define DDR0 *((volatile uchar*)(CFG_MBAR+0x0c08))
203# define DVO0 *((volatile uchar*)(CFG_MBAR+0x0c0c))
204# define DVI0 *((volatile uchar*)(CFG_MBAR+0x0c20))
205# define ODE0 *((volatile uchar*)(CFG_MBAR+0x0c04))
wdenkc1896002003-12-28 11:44:59 +0000206# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
207# define I2C_READ ((DVI0&SDA0)?1:0)
208# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
209# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
210# define I2C_DELAY {udelay(5);}
211# define I2C_ACTIVE {DDR0|=SDA0;}
212# define I2C_TRISTATE {DDR0&=~SDA0;}
213# define CFG_I2C_SPEED 100000
214# define CFG_I2C_SLAVE 0x7F
wdenk4d13cba2004-03-14 14:09:05 +0000215#define CFG_I2C_EEPROM_ADDR 0x57
216#define CFG_I2C_FACT_ADDR 0x57
wdenkc1896002003-12-28 11:44:59 +0000217#endif
wdenkd4ca31c2004-01-02 14:00:00 +0000218
219#if defined (CONFIG_HARD_I2C)
wdenkc1896002003-12-28 11:44:59 +0000220# define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
221# define CFG_I2C_SPEED 100000 /* 100 kHz */
222# define CFG_I2C_SLAVE 0x7F
wdenk4d13cba2004-03-14 14:09:05 +0000223#define CFG_I2C_EEPROM_ADDR 0x54
224#define CFG_I2C_FACT_ADDR 0x54
wdenkd4ca31c2004-01-02 14:00:00 +0000225#endif
wdenkc1896002003-12-28 11:44:59 +0000226
227/*
228 * Flash configuration, expect one 16 Megabyte Bank at most
229 */
230#define CFG_FLASH_BASE 0xff000000
231#define CFG_FLASH_SIZE 0x01000000
232#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
wdenkd4ca31c2004-01-02 14:00:00 +0000233#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0)
wdenkc1896002003-12-28 11:44:59 +0000234
235#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
236
237#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
238#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
239
240#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
241
wdenkd4ca31c2004-01-02 14:00:00 +0000242/*
243 * DRAM configuration - will be read from VPD later... TODO!
244 */
245#if 0
246/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
247#define CFG_DRAM_DDR 0
248#define CFG_DRAM_EMODE 0
249#define CFG_DRAM_MODE 0x008D
250#define CFG_DRAM_CONTROL 0x514F0000
251#define CFG_DRAM_CONFIG1 0xC2233A00
252#define CFG_DRAM_CONFIG2 0x88B70004
253#define CFG_DRAM_TAP_DEL 0x08
254#define CFG_DRAM_RAM_SIZE 0x19
255#endif
256#if 1
257/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
258#define CFG_DRAM_DDR 0
259#define CFG_DRAM_EMODE 0
260#define CFG_DRAM_MODE 0x00CD
261#define CFG_DRAM_CONTROL 0x514F0000
262#define CFG_DRAM_CONFIG1 0xD2333A00
263#define CFG_DRAM_CONFIG2 0x8AD70004
264#define CFG_DRAM_TAP_DEL 0x08
265#define CFG_DRAM_RAM_SIZE 0x19
266#endif
267
wdenkc1896002003-12-28 11:44:59 +0000268/*
269 * Environment settings
270 */
271#define CFG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
272#define CFG_ENV_OFFSET 0x1000
273#define CFG_ENV_SIZE 0x0700
wdenkc1896002003-12-28 11:44:59 +0000274
wdenkd4ca31c2004-01-02 14:00:00 +0000275/*
276 * VPD settings
277 */
wdenkc1896002003-12-28 11:44:59 +0000278#define CFG_FACT_OFFSET 0x1800
279#define CFG_FACT_SIZE 0x0800
wdenkd4ca31c2004-01-02 14:00:00 +0000280
wdenkc1896002003-12-28 11:44:59 +0000281/*
wdenkd4ca31c2004-01-02 14:00:00 +0000282 * Memory map
283 *
284 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
wdenkc1896002003-12-28 11:44:59 +0000285 */
286#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
287#define CFG_SDRAM_BASE 0x00000000
288#define CFG_DEFAULT_MBAR 0x80000000
289
290/* Use SRAM until RAM will be available */
291#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
292#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
293
294
295#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
296#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
297#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
298
299#define CFG_MONITOR_BASE TEXT_BASE
300#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
301# define CFG_RAMBOOT 1
302#endif
303
304#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
305#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
306#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
307
308/*
309 * Ethernet configuration
310 */
wdenkcbd8a352004-02-24 02:00:03 +0000311#define CONFIG_MPC5xxx_FEC 1
wdenkc1896002003-12-28 11:44:59 +0000312#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
wdenkd4ca31c2004-01-02 14:00:00 +0000313#define CONFIG_PHY_ADDR 0x1f
wdenkc1896002003-12-28 11:44:59 +0000314#define CONFIG_PHY_TYPE 0x79c874
315/*
wdenkd4ca31c2004-01-02 14:00:00 +0000316 * GPIO configuration:
317 * PSC1,2,3 predefined as UART
318 * PCI disabled
wdenkc1896002003-12-28 11:44:59 +0000319 * Ethernet 100 with MD
320 */
wdenk498b8db2004-04-18 22:26:17 +0000321#define CFG_GPS_PORT_CONFIG 0x00058044
wdenkc1896002003-12-28 11:44:59 +0000322
323/*
324 * Miscellaneous configurable options
325 */
326#define CFG_LONGHELP /* undef to save memory */
327#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500328#if defined(CONFIG_CMD_KGDB)
wdenkc1896002003-12-28 11:44:59 +0000329# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
330#else
331# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
332#endif
333#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
334#define CFG_MAXARGS 16 /* max number of command args */
335#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
336
337#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
338#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
339
wdenk4d13cba2004-03-14 14:09:05 +0000340#define CFG_LOAD_ADDR 0x200000 /* default load address */
wdenkc1896002003-12-28 11:44:59 +0000341
342#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
343
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500344#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
345#if defined(CONFIG_CMD_KGDB)
346# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
347#endif
348
349
wdenk63e73c92004-02-23 22:22:28 +0000350#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
351 #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
352 #define RTC(reg) (0xf0010000+reg)
353 /* setup CS2 for M48T08. Must MAP 64kB */
354 #define CFG_CS2_START RTC(0)
355 #define CFG_CS2_SIZE 0x10000
356 /* setup CS2 configuration register: */
357 /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
358 /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
359 #define CFG_CS2_CFG 0x00047800
360#else
361 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
362#endif
wdenk1c437712004-01-16 00:30:56 +0000363
wdenkc1896002003-12-28 11:44:59 +0000364/*
365 * Various low-level settings
366 */
367#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
368#define CFG_HID0_FINAL HID0_ICE
369
370#define CFG_BOOTCS_START CFG_FLASH_BASE
371#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
372#define CFG_BOOTCS_CFG 0x00047801
373#define CFG_CS0_START CFG_FLASH_BASE
374#define CFG_CS0_SIZE CFG_FLASH_SIZE
375
376#define CFG_CS_BURST 0x00000000
377#define CFG_CS_DEADCYCLE 0x33333333
378
379#define CFG_RESET_ADDRESS 0x7f000000
380
wdenk4d13cba2004-03-14 14:09:05 +0000381/*-----------------------------------------------------------------------
382 * IDE/ATA stuff Supports IDE harddisk
383 *-----------------------------------------------------------------------
384 */
385
386#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
387
388#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
389#undef CONFIG_IDE_LED /* LED for ide not supported */
390
391#define CONFIG_IDE_RESET 1
392#define CONFIG_IDE_PREINIT
393
394#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
395#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
396
397#define CFG_ATA_IDE0_OFFSET 0x0000
398
399#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
400
401/* Offset for data I/O */
402#define CFG_ATA_DATA_OFFSET (0x0060)
403
404/* Offset for normal register accesses */
405#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
406
407/* Offset for alternate registers */
408#define CFG_ATA_ALT_OFFSET (0x005c)
409
410/* Interval between registers */
411#define CFG_ATA_STRIDE 4
412
wdenkc1896002003-12-28 11:44:59 +0000413#endif /* __CONFIG_H */