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Dinh Nguyen77754402012-10-04 06:46:02 +00001/*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Dinh Nguyen77754402012-10-04 06:46:02 +00005 */
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
9#include <asm/arch/socfpga_base_addrs.h>
Chin Liang See5d649d22013-09-11 11:24:48 -050010#include "../../board/altera/socfpga/pinmux_config.h"
Chin Liang Seedc4d4aa2014-06-10 01:17:42 -050011#include "../../board/altera/socfpga/iocsr_config.h"
Chin Liang Seeddfeb0a2014-03-04 22:13:53 -060012#include "../../board/altera/socfpga/pll_config.h"
Dinh Nguyen77754402012-10-04 06:46:02 +000013
14/*
15 * High level configuration
16 */
Chin Liang See31ad8642013-08-07 10:06:56 -050017/* Virtual target or real hardware */
Chin Liang See3ab019e2014-07-22 04:28:35 -050018#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
Dinh Nguyen77754402012-10-04 06:46:02 +000019
20#define CONFIG_ARMV7
Dinh Nguyen77754402012-10-04 06:46:02 +000021#define CONFIG_SYS_DCACHE_OFF
22#undef CONFIG_USE_IRQ
23
24#define CONFIG_MISC_INIT_R
25#define CONFIG_SINGLE_BOOTLOADER
26#define CONFIG_SOCFPGA
27
Chin Liang See31ad8642013-08-07 10:06:56 -050028/* base address for .text section */
29#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
Dinh Nguyen77754402012-10-04 06:46:02 +000030#define CONFIG_SYS_TEXT_BASE 0x08000040
Chin Liang See31ad8642013-08-07 10:06:56 -050031#else
32#define CONFIG_SYS_TEXT_BASE 0x01000040
33#endif
Dinh Nguyen77754402012-10-04 06:46:02 +000034#define CONFIG_SYS_LOAD_ADDR 0x7fc0
35
36/* Console I/O Buffer Size */
37#define CONFIG_SYS_CBSIZE 256
38/* Monitor Command Prompt */
39#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
40#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
41 sizeof(CONFIG_SYS_PROMPT) + 16)
42
43/*
44 * Display CPU and Board Info
45 */
46#define CONFIG_DISPLAY_CPUINFO
47#define CONFIG_DISPLAY_BOARDINFO
48
49/*
50 * Enable early stage initialization at C environment
51 */
52#define CONFIG_BOARD_EARLY_INIT_F
53
54/* flat device tree */
55#define CONFIG_OF_LIBFDT
56/* skip updating the FDT blob */
57#define CONFIG_FDT_BLOB_SKIP_UPDATE
58/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
59#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
60
61#define CONFIG_SPL_RAM_DEVICE
Albert ARIBAUDe05e5de2013-01-08 10:18:02 +000062#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
Dinh Nguyen77754402012-10-04 06:46:02 +000063#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
64#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
65
66/*
67 * Memory allocation (MALLOC)
68 */
69/* Room required on the stack for the environment data */
70#define CONFIG_ENV_SIZE 1024
71/* Size of DRAM reserved for malloc() use */
72#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
73
74/* SP location before relocation, must use scratch RAM */
75#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
76/* Reserving 0x100 space at back of scratch RAM for debug info */
77#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
78/* Stack pointer prior relocation, must situated at on-chip RAM */
79#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
80 CONFIG_SYS_INIT_RAM_SIZE - \
81 GENERATED_GBL_DATA_SIZE)
82
83
84/*
85 * Command line configuration.
86 */
87#define CONFIG_SYS_NO_FLASH
88#include <config_cmd_default.h>
89/* FAT file system support */
90#define CONFIG_CMD_FAT
91
92
93/*
94 * Misc
95 */
96#define CONFIG_DOS_PARTITION 1
97
98#ifdef CONFIG_SPL_BUILD
99#undef CONFIG_PARTITIONS
100#endif
101
102/*
103 * Environment setup
104 */
105
106/* Delay before automatically booting the default image */
107#define CONFIG_BOOTDELAY 3
108/* Enable auto completion of commands using TAB */
109#define CONFIG_AUTO_COMPLETE
110/* use "hush" command parser */
111#define CONFIG_SYS_HUSH_PARSER
112#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
113#define CONFIG_CMD_RUN
114
115#define CONFIG_BOOTCOMMAND "run ramboot"
116
117/*
118 * arguments passed to the bootm command. The value of
119 * CONFIG_BOOTARGS goes into the environment value "bootargs".
120 * Do note the value will overide also the chosen node in FDT blob.
121 */
122#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
123
124#define CONFIG_EXTRA_ENV_SETTINGS \
125 "verify=n\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200126 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
Dinh Nguyen77754402012-10-04 06:46:02 +0000127 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
128 "bootm ${loadaddr} - ${fdt_addr}\0" \
129 "bootimage=uImage\0" \
130 "fdt_addr=100\0" \
131 "fsloadcmd=ext2load\0" \
132 "bootm ${loadaddr} - ${fdt_addr}\0" \
133 "qspiroot=/dev/mtdblock0\0" \
134 "qspirootfstype=jffs2\0" \
135 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
136 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
137 "bootm ${loadaddr} - ${fdt_addr}\0"
138
139/* using environment setting for stdin, stdout, stderr */
140#define CONFIG_SYS_CONSOLE_IS_IN_ENV
141/* Enable the call to overwrite_console() */
142#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
143/* Enable overwrite of previous console environment settings */
144#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
145
146/* max number of command args */
147#define CONFIG_SYS_MAXARGS 16
148
149
150/*
151 * Hardware drivers
152 */
153
154/*
155 * SDRAM Memory Map
156 */
157/* We have 1 bank of DRAM */
158#define CONFIG_NR_DRAM_BANKS 1
159/* SDRAM Bank #1 */
160#define CONFIG_SYS_SDRAM_BASE 0x00000000
161/* SDRAM memory size */
Chin Liang See31ad8642013-08-07 10:06:56 -0500162#define PHYS_SDRAM_1_SIZE 0x40000000
Dinh Nguyen77754402012-10-04 06:46:02 +0000163
164#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
165#define CONFIG_SYS_MEMTEST_START 0x00000000
166#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
167
168/*
169 * NS16550 Configuration
170 */
171#define UART0_BASE SOCFPGA_UART0_ADDRESS
172#define CONFIG_SYS_NS16550
173#define CONFIG_SYS_NS16550_SERIAL
174#define CONFIG_SYS_NS16550_REG_SIZE -4
175#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
176#define CONFIG_CONS_INDEX 1
177#define CONFIG_SYS_NS16550_COM1 UART0_BASE
Dinh Nguyen77754402012-10-04 06:46:02 +0000178#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
Chin Liang See31ad8642013-08-07 10:06:56 -0500179#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
180#define V_NS16550_CLK 1000000
181#else
182#define V_NS16550_CLK 100000000
183#endif
184#define CONFIG_BAUDRATE 115200
Dinh Nguyen77754402012-10-04 06:46:02 +0000185
186/*
187 * FLASH
188 */
189#define CONFIG_SYS_NO_FLASH
190
191/*
192 * L4 OSC1 Timer 0
193 */
194/* This timer use eosc1 where the clock frequency is fixed
195 * throughout any condition */
196#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
Dinh Nguyen77754402012-10-04 06:46:02 +0000197/* reload value when timer count to zero */
198#define TIMER_LOAD_VAL 0xFFFFFFFF
Chin Liang See31ad8642013-08-07 10:06:56 -0500199/* Timer info */
Chin Liang See31ad8642013-08-07 10:06:56 -0500200#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
Rob Herring23ab7ee2013-10-04 10:22:46 -0500201#define CONFIG_SYS_TIMER_RATE 2400000
Chin Liang See31ad8642013-08-07 10:06:56 -0500202#else
Rob Herring23ab7ee2013-10-04 10:22:46 -0500203#define CONFIG_SYS_TIMER_RATE 25000000
Chin Liang See31ad8642013-08-07 10:06:56 -0500204#endif
Pavel Machek2cc0ea72014-07-13 13:10:45 +0200205#define CONFIG_SYS_TIMER_COUNTS_DOWN
Rob Herring23ab7ee2013-10-04 10:22:46 -0500206#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
Dinh Nguyen77754402012-10-04 06:46:02 +0000207
208#define CONFIG_ENV_IS_NOWHERE
209
210/*
Pavel Machek99b97102014-07-14 14:14:17 +0200211 * network support
212 */
213#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
214#define CONFIG_DESIGNWARE_ETH 1
215#endif
216
217#ifdef CONFIG_DESIGNWARE_ETH
218#define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
219#define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
220/* console support for network */
221#define CONFIG_CMD_DHCP
222#define CONFIG_CMD_MII
223#define CONFIG_CMD_NET
224#define CONFIG_CMD_PING
225/* designware */
226#define CONFIG_NET_MULTI
227#define CONFIG_DW_ALTDESCRIPTOR
228#define CONFIG_DW_SEARCH_PHY
229#define CONFIG_MII
230#define CONFIG_PHY_GIGE
231#define CONFIG_DW_AUTONEG
232#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
233#define CONFIG_PHYLIB
234#define CONFIG_PHY_MICREL
235#define CONFIG_PHY_MICREL_KSZ9021
236/* EMAC controller and PHY used */
237#define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
238#define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
239#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
240#endif /* CONFIG_DESIGNWARE_ETH */
241
242/*
Chin Liang See05b884b2014-06-10 01:11:04 -0500243 * L4 Watchdog
244 */
245#define CONFIG_HW_WATCHDOG
246#define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
247#define CONFIG_DESIGNWARE_WATCHDOG
248#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
249/* Clocks source frequency to watchdog timer */
250#define CONFIG_DW_WDT_CLOCK_KHZ 25000
251
252
253/*
Dinh Nguyen77754402012-10-04 06:46:02 +0000254 * SPL "Second Program Loader" aka Initial Software
255 */
256
257/* Enable building of SPL globally */
Dinh Nguyen77754402012-10-04 06:46:02 +0000258#define CONFIG_SPL_FRAMEWORK
259
260/* TEXT_BASE for linking the SPL binary */
261#define CONFIG_SPL_TEXT_BASE 0xFFFF0000
262
263/* Stack size for SPL */
264#define CONFIG_SPL_STACK_SIZE (4 * 1024)
265
266/* MALLOC size for SPL */
267#define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
268
269#define CONFIG_SPL_SERIAL_SUPPORT
270#define CONFIG_SPL_BOARD_INIT
271
272#define CHUNKSZ_CRC32 (1 * 1024)
273
274#define CONFIG_CRC32_VERIFY
275
276/* Linker script for SPL */
277#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
278
279/* Support for common/libcommon.o in SPL binary */
280#define CONFIG_SPL_LIBCOMMON_SUPPORT
281/* Support for lib/libgeneric.o in SPL binary */
282#define CONFIG_SPL_LIBGENERIC_SUPPORT
283
Chin Liang See05b884b2014-06-10 01:11:04 -0500284/* Support for watchdog */
285#define CONFIG_SPL_WATCHDOG_SUPPORT
286
Dinh Nguyen77754402012-10-04 06:46:02 +0000287#endif /* __CONFIG_H */