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Matthias Fuchs72c5d522007-12-28 17:07:14 +01001/*
Matthias Fuchsbe270792008-10-28 13:37:00 +01002 * (Cg) Copyright 2007-2008
Matthias Fuchs72c5d522007-12-28 17:07:14 +01003 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on board/amcc/sequoia/sequoia.c
5 *
6 * (C) Copyright 2006
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * (C) Copyright 2006
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#include <common.h>
30#include <libfdt.h>
31#include <fdt_support.h>
32#include <ppc440.h>
33#include <asm/processor.h>
34#include <asm/io.h>
Matthias Fuchs034394a2008-03-30 18:52:44 +020035#include <asm/bitops.h>
Matthias Fuchs72c5d522007-12-28 17:07:14 +010036#include <command.h>
37#include <i2c.h>
38#ifdef CONFIG_RESET_PHY_R
39#include <miiphy.h>
40#endif
41#include <serial.h>
Stefan Roese6c700492009-11-12 17:19:37 +010042#include <asm/4xx_pci.h>
43
Matthias Fuchs72c5d522007-12-28 17:07:14 +010044#include "fpga.h"
45#include "pmc440.h"
46
47DECLARE_GLOBAL_DATA_PTR;
48
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
Matthias Fuchsbe270792008-10-28 13:37:00 +010050extern void __ft_board_setup(void *blob, bd_t *bd);
Matthias Fuchs72c5d522007-12-28 17:07:14 +010051
52ulong flash_get_size(ulong base, int banknum);
53int pci_is_66mhz(void);
Matthias Fuchsbe270792008-10-28 13:37:00 +010054int is_monarch(void);
Matthias Fuchs034394a2008-03-30 18:52:44 +020055int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
56 uchar *buffer, unsigned cnt);
Matthias Fuchs72c5d522007-12-28 17:07:14 +010057
58struct serial_device *default_serial_console(void)
59{
60 uchar buf[4];
61 ulong delay;
62 int i;
63 ulong val;
64
65 /*
66 * Use default console on P4 when strapping jumper
67 * is installed (bootstrap option != 'H').
68 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020069 mfsdr(SDR0_PINSTP, val);
Matthias Fuchs72c5d522007-12-28 17:07:14 +010070 if (((val & 0xf0000000) >> 29) != 7)
71 return &serial1_device;
72
73 ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
74 if (!(scratchreg & 0x80)) {
75 /* mark scratchreg valid */
76 scratchreg = (scratchreg & 0xffffff00) | 0x80;
77
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
Matthias Fuchs034394a2008-03-30 18:52:44 +020079 0x10, buf, 4);
Matthias Fuchs72c5d522007-12-28 17:07:14 +010080 if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
81 scratchreg |= buf[2];
82
83 /* bringup delay for console */
84 for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
85 udelay(1000);
86 }
87 } else
88 scratchreg |= 0x01;
89 out_be32((void*)GPIO0_ISR3L, scratchreg);
90 }
91
92 if (scratchreg & 0x01)
93 return &serial1_device;
94 else
95 return &serial0_device;
96}
97
98int board_early_init_f(void)
99{
100 u32 sdr0_cust0;
101 u32 sdr0_pfc1, sdr0_pfc2;
102 u32 reg;
103
104 /* general EBC configuration (disable EBC timeouts) */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200105 mtdcr(EBC0_CFGADDR, EBC0_CFG);
106 mtdcr(EBC0_CFGDATA, 0xf8400000);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100107
Matthias Fuchs034394a2008-03-30 18:52:44 +0200108 /*
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100109 * Setup the GPIO pins
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
Matthias Fuchs034394a2008-03-30 18:52:44 +0200111 */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100112 out_be32((void *)GPIO0_OR, 0x40000102);
113 out_be32((void *)GPIO0_TCR, 0x4c90011f);
114 out_be32((void *)GPIO0_OSRL, 0x28051400);
115 out_be32((void *)GPIO0_OSRH, 0x55005000);
116 out_be32((void *)GPIO0_TSRL, 0x08051400);
117 out_be32((void *)GPIO0_TSRH, 0x55005000);
118 out_be32((void *)GPIO0_ISR1L, 0x54000000);
119 out_be32((void *)GPIO0_ISR1H, 0x00000000);
120 out_be32((void *)GPIO0_ISR2L, 0x44000000);
121 out_be32((void *)GPIO0_ISR2H, 0x00000100);
122 out_be32((void *)GPIO0_ISR3L, 0x00000000);
123 out_be32((void *)GPIO0_ISR3H, 0x00000000);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100124
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100125 out_be32((void *)GPIO1_OR, 0x80002408);
126 out_be32((void *)GPIO1_TCR, 0xd6003c08);
127 out_be32((void *)GPIO1_OSRL, 0x0a5a0000);
128 out_be32((void *)GPIO1_OSRH, 0x00000000);
129 out_be32((void *)GPIO1_TSRL, 0x00000000);
130 out_be32((void *)GPIO1_TSRH, 0x00000000);
131 out_be32((void *)GPIO1_ISR1L, 0x00005555);
132 out_be32((void *)GPIO1_ISR1H, 0x40000000);
133 out_be32((void *)GPIO1_ISR2L, 0x04010000);
134 out_be32((void *)GPIO1_ISR2H, 0x00000000);
135 out_be32((void *)GPIO1_ISR3L, 0x01400000);
136 out_be32((void *)GPIO1_ISR3H, 0x00000000);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100137
138 /* patch PLB:PCI divider for 66MHz PCI */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200139 mfcpr(CPR0_SPCID, reg);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100140 if (pci_is_66mhz() && (reg != 0x02000000)) {
Stefan Roesed1c3b272009-09-09 16:25:29 +0200141 mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100142
Stefan Roesed1c3b272009-09-09 16:25:29 +0200143 mfcpr(CPR0_ICFG, reg);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100144 reg |= CPR0_ICFG_RLI_MASK;
Stefan Roesed1c3b272009-09-09 16:25:29 +0200145 mtcpr(CPR0_ICFG, reg);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100146
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200147 mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100148 }
149
Matthias Fuchs034394a2008-03-30 18:52:44 +0200150 /*
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100151 * Setup the interrupt controller polarities, triggers, etc.
Matthias Fuchs034394a2008-03-30 18:52:44 +0200152 */
Stefan Roese952e7762009-09-24 09:55:50 +0200153 mtdcr(UIC0SR, 0xffffffff); /* clear all */
154 mtdcr(UIC0ER, 0x00000000); /* disable all */
155 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
156 mtdcr(UIC0PR, 0xfffff7ef);
157 mtdcr(UIC0TR, 0x00000000);
158 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
159 mtdcr(UIC0SR, 0xffffffff); /* clear all */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100160
Stefan Roese952e7762009-09-24 09:55:50 +0200161 mtdcr(UIC1SR, 0xffffffff); /* clear all */
162 mtdcr(UIC1ER, 0x00000000); /* disable all */
163 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
164 mtdcr(UIC1PR, 0xffffc7f5);
165 mtdcr(UIC1TR, 0x00000000);
166 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
167 mtdcr(UIC1SR, 0xffffffff); /* clear all */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100168
Stefan Roese952e7762009-09-24 09:55:50 +0200169 mtdcr(UIC2SR, 0xffffffff); /* clear all */
170 mtdcr(UIC2ER, 0x00000000); /* disable all */
171 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
172 mtdcr(UIC2PR, 0x27ffffff);
173 mtdcr(UIC2TR, 0x00000000);
174 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
175 mtdcr(UIC2SR, 0xffffffff); /* clear all */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100176
177 /* select Ethernet pins */
178 mfsdr(SDR0_PFC1, sdr0_pfc1);
Matthias Fuchs034394a2008-03-30 18:52:44 +0200179 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
180 SDR0_PFC1_SELECT_CONFIG_4;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100181 mfsdr(SDR0_PFC2, sdr0_pfc2);
Matthias Fuchs034394a2008-03-30 18:52:44 +0200182 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
183 SDR0_PFC2_SELECT_CONFIG_4;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100184
185 /* enable 2nd IIC */
186 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
187
188 mtsdr(SDR0_PFC2, sdr0_pfc2);
189 mtsdr(SDR0_PFC1, sdr0_pfc1);
190
191 /* setup NAND FLASH */
192 mfsdr(SDR0_CUST0, sdr0_cust0);
193 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
194 SDR0_CUST0_NDFC_ENABLE |
195 SDR0_CUST0_NDFC_BW_8_BIT |
196 SDR0_CUST0_NDFC_ARE_MASK |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100198 mtsdr(SDR0_CUST0, sdr0_cust0);
199
200 return 0;
201}
202
Matthias Fuchsbe270792008-10-28 13:37:00 +0100203#if defined(CONFIG_MISC_INIT_F)
204int misc_init_f(void)
205{
206 struct pci_controller hose;
207 hose.first_busno = 0;
208 hose.last_busno = 0;
209 hose.region_count = 0;
210
211 if (getenv("pciearly") && (!is_monarch())) {
212 printf("PCI: early target init\n");
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200213 pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
Matthias Fuchsbe270792008-10-28 13:37:00 +0100214 pci_target_init(&hose);
215 }
216 return 0;
217}
218#endif
219
Matthias Fuchs034394a2008-03-30 18:52:44 +0200220/*
221 * misc_init_r.
222 */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100223int misc_init_r(void)
224{
225 uint pbcr;
226 int size_val = 0;
227 u32 reg;
228 unsigned long usb2d0cr = 0;
229 unsigned long usb2phy0cr, usb2h0cr = 0;
230 unsigned long sdr0_pfc1;
Matthias Fuchsbe270792008-10-28 13:37:00 +0100231 unsigned long sdr0_srst0, sdr0_srst1;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100232 char *act = getenv("usbact");
233
234 /*
235 * FLASH stuff...
236 */
237
238 /* Re-do sizing to get full correct info */
239
240 /* adjust flash start and offset */
241 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
242 gd->bd->bi_flashoffset = 0;
243
244#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200245 mtdcr(EBC0_CFGADDR, PB2CR);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100246#else
Stefan Roesed1c3b272009-09-09 16:25:29 +0200247 mtdcr(EBC0_CFGADDR, PB0CR);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100248#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200249 pbcr = mfdcr(EBC0_CFGDATA);
Matthias Fuchs034394a2008-03-30 18:52:44 +0200250 size_val = ffs(gd->bd->bi_flashsize) - 21;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100251 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
252#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200253 mtdcr(EBC0_CFGADDR, PB2CR);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100254#else
Stefan Roesed1c3b272009-09-09 16:25:29 +0200255 mtdcr(EBC0_CFGADDR, PB0CR);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100256#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200257 mtdcr(EBC0_CFGDATA, pbcr);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100258
259 /*
260 * Re-check to get correct base address
261 */
262 flash_get_size(gd->bd->bi_flashstart, 0);
263
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200264#ifdef CONFIG_ENV_IS_IN_FLASH
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100265 /* Monitor protection ON by default */
266 (void)flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267 -CONFIG_SYS_MONITOR_LEN,
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100268 0xffffffff,
269 &flash_info[0]);
270
271 /* Env protection ON by default */
272 (void)flash_protect(FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200273 CONFIG_ENV_ADDR_REDUND,
274 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100275 &flash_info[0]);
276#endif
277
278 /*
279 * USB suff...
280 */
Matthias Fuchsbe270792008-10-28 13:37:00 +0100281 if ((act == NULL || strcmp(act, "host") == 0) &&
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100282 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
283 /* SDR Setting */
284 mfsdr(SDR0_PFC1, sdr0_pfc1);
285 mfsdr(SDR0_USB2D0CR, usb2d0cr);
286 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
287 mfsdr(SDR0_USB2H0CR, usb2h0cr);
288
289 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200290 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100291 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200292 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100293 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200294 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100295 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200296 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100297 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200298 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100299
Matthias Fuchs034394a2008-03-30 18:52:44 +0200300 /*
301 * An 8-bit/60MHz interface is the only possible alternative
302 * when connecting the Device to the PHY
303 */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100304 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200305 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100306
307 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
308 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
309
310 mtsdr(SDR0_PFC1, sdr0_pfc1);
311 mtsdr(SDR0_USB2D0CR, usb2d0cr);
312 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
313 mtsdr(SDR0_USB2H0CR, usb2h0cr);
314
Matthias Fuchsbe270792008-10-28 13:37:00 +0100315 /*
316 * Take USB out of reset:
317 * -Initial status = all cores are in reset
318 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
319 * -wait 1 ms
320 * -deassert reset to PHY
321 * -wait 1 ms
322 * -deassert reset to HOST
323 * -wait 4 ms
324 * -deassert all other resets
325 */
326 mfsdr(SDR0_SRST1, sdr0_srst1);
327 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
328 SDR0_SRST1_P4OPB0 | \
329 SDR0_SRST1_OPBA2 | \
330 SDR0_SRST1_PLB42OPB1 | \
331 SDR0_SRST1_OPB2PLB40);
332 mtsdr(SDR0_SRST1, sdr0_srst1);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100333 udelay(1000);
Matthias Fuchsbe270792008-10-28 13:37:00 +0100334
335 mfsdr(SDR0_SRST1, sdr0_srst1);
336 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
337 mtsdr(SDR0_SRST1, sdr0_srst1);
338 udelay(1000);
339
340 mfsdr(SDR0_SRST0, sdr0_srst0);
341 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
342 mtsdr(SDR0_SRST0, sdr0_srst0);
343 udelay(4000);
344
345 /* finally all the other resets */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100346 mtsdr(SDR0_SRST1, 0x00000000);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100347 mtsdr(SDR0_SRST0, 0x00000000);
348
Matthias Fuchsbe270792008-10-28 13:37:00 +0100349 if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
350 /* enable power on USB socket */
351 out_be32((void*)GPIO1_OR,
352 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
353 }
354
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100355 printf("USB: Host\n");
356
Matthias Fuchs034394a2008-03-30 18:52:44 +0200357 } else if ((strcmp(act, "dev") == 0) ||
358 (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100359 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
360
361 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200362 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100363 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200364 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100365 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200366 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100367 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200368 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100369 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
370
371 udelay (1000);
372 mtsdr(SDR0_SRST1, 0x672c6000);
373
374 udelay (1000);
375 mtsdr(SDR0_SRST0, 0x00000080);
376
377 udelay (1000);
378 mtsdr(SDR0_SRST1, 0x60206000);
379
380 *(unsigned int *)(0xe0000350) = 0x00000001;
381
382 udelay (1000);
383 mtsdr(SDR0_SRST1, 0x60306000);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100384
385 /* SDR Setting */
386 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
387 mfsdr(SDR0_USB2H0CR, usb2h0cr);
388 mfsdr(SDR0_USB2D0CR, usb2d0cr);
389 mfsdr(SDR0_PFC1, sdr0_pfc1);
390
391 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200392 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100393 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200394 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100395 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200396 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100397 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200398 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100399 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200400 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100401
402 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200403 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100404
405 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
406
407 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
Matthias Fuchs034394a2008-03-30 18:52:44 +0200408 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100409
410 mtsdr(SDR0_USB2H0CR, usb2h0cr);
411 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
412 mtsdr(SDR0_USB2D0CR, usb2d0cr);
413 mtsdr(SDR0_PFC1, sdr0_pfc1);
414
415 /*clear resets*/
416 udelay(1000);
417 mtsdr(SDR0_SRST1, 0x00000000);
418 udelay(1000);
419 mtsdr(SDR0_SRST0, 0x00000000);
420
421 printf("USB: Device\n");
422 }
423
424 /*
425 * Clear PLB4A0_ACR[WRP]
426 * This fix will make the MAL burst disabling patch for the Linux
427 * EMAC driver obsolete.
428 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200429 reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
430 mtdcr(PLB4_ACR, reg);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100431
432#ifdef CONFIG_FPGA
433 pmc440_init_fpga();
434#endif
435
436 /* turn off POST LED */
437 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
438 /* turn on RUN LED */
439 out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
440 return 0;
441}
442
443int is_monarch(void)
444{
445 if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
446 return 0;
447
448 return 1;
449}
450
451int pci_is_66mhz(void)
452{
453 if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
454 return 1;
455 return 0;
456}
457
458int board_revision(void)
459{
460 return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
461}
462
463int checkboard(void)
464{
465 puts("Board: esd GmbH - PMC440");
466
467 gd->board_type = board_revision();
468 printf(", Rev 1.%ld, ", gd->board_type);
469
470 if (!is_monarch()) {
471 puts("non-");
472 }
473
474 printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
475 return (0);
476}
477
478
479#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
480/*
481 * Assign interrupts to PCI devices. Some OSs rely on this.
482 */
Stefan Roesea760b022009-11-12 16:41:09 +0100483void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100484{
485 unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
486
487 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
488 int_line[PCI_DEV(dev) & 0x03]);
489}
490#endif
491
Matthias Fuchs034394a2008-03-30 18:52:44 +0200492/*
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200493 * pci_target_init
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100494 *
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200495 * The bootstrap configuration provides default settings for the pci
496 * inbound map (PIM). But the bootstrap config choices are limited and
497 * may not be sufficient for a given board.
498 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100500void pci_target_init(struct pci_controller *hose)
501{
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200502 char *ptmla_str, *ptmms_str;
503
504 /*
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100505 * Set up Direct MMIO registers
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200506 */
507 /*
508 * PowerPC440EPX PCI Master configuration.
509 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
510 * PLB address 0x80000000-0xBFFFFFFF
511 * ==> PCI address 0x80000000-0xBFFFFFFF
512 * Use byte reversed out routines to handle endianess.
513 * Make this region non-prefetchable.
514 */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200515 out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200516 /* - disabled b4 setting */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200517 out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
518 out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
519 out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
520 out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200521 /* and enable region */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100522
523 if (!is_monarch()) {
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200524 ptmla_str = getenv("ptm1la");
525 ptmms_str = getenv("ptm1ms");
526 if(NULL != ptmla_str && NULL != ptmms_str ) {
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200527 out32r(PCIL0_PTM1MS,
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200528 simple_strtoul(ptmms_str, NULL, 16));
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200529 out32r(PCIL0_PTM1LA,
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200530 simple_strtoul(ptmla_str, NULL, 16));
531 } else {
532 /* BAR1: default top 64MB of RAM */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200533 out32r(PCIL0_PTM1MS, 0xfc000001);
534 out32r(PCIL0_PTM1LA, 0x0c000000);
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200535 }
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100536 } else {
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200537 /* BAR1: default: complete 256MB RAM */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200538 out32r(PCIL0_PTM1MS, 0xf0000001);
539 out32r(PCIL0_PTM1LA, 0x00000000);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100540 }
541
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200542 ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */
543 ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */
544 if(NULL != ptmla_str && NULL != ptmms_str ) {
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200545 out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
546 out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200547 } else {
Matthias Fuchsbe270792008-10-28 13:37:00 +0100548 /* BAR2: default: 4MB FPGA */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200549 out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
550 out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200551 }
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100552
553 if (is_monarch()) {
554 /* BAR2: map FPGA registers behind system memory at 1GB */
Matthias Fuchsbe270792008-10-28 13:37:00 +0100555 pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100556 }
557
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200558 /*
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100559 * Set up Configuration registers
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200560 */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100561
562 /* Program the board's vendor id */
Matthias Fuchsbe270792008-10-28 13:37:00 +0100563 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
564 CONFIG_SYS_PCI_SUBSYS_VENDORID);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100565
Stefan Roese02e38922008-03-31 12:20:48 +0200566 /* disabled for PMC405 backward compatibility */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100567 /* Configure command register as bus master */
Matthias Fuchs034394a2008-03-30 18:52:44 +0200568 /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
569
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100570
571 /* 240nS PCI clock */
Matthias Fuchsbe270792008-10-28 13:37:00 +0100572 pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100573
574 /* No error reporting */
Matthias Fuchsbe270792008-10-28 13:37:00 +0100575 pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100576
577 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
578
579 if (!is_monarch()) {
580 /* Program the board's subsystem id/classcode */
Matthias Fuchsbe270792008-10-28 13:37:00 +0100581 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
582 CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
583 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
584 CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100585
586 /* PCI configuration done: release ERREADY */
Matthias Fuchsa6cc6c32008-03-30 18:52:06 +0200587 out_be32((void*)GPIO1_OR,
588 in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
589 out_be32((void*)GPIO1_TCR,
590 in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100591 } else {
592 /* Program the board's subsystem id/classcode */
Matthias Fuchsbe270792008-10-28 13:37:00 +0100593 pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
594 CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
595 pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
596 CONFIG_SYS_PCI_CLASSCODE_MONARCH);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100597 }
Matthias Fuchsbe270792008-10-28 13:37:00 +0100598
599 /* enable host configuration */
600 pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100601}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100603
Matthias Fuchs034394a2008-03-30 18:52:44 +0200604/*
Stefan Roese6c700492009-11-12 17:19:37 +0100605 * Override weak default pci_master_init()
Matthias Fuchs034394a2008-03-30 18:52:44 +0200606 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100608void pci_master_init(struct pci_controller *hose)
609{
Matthias Fuchs034394a2008-03-30 18:52:44 +0200610 /*
Stefan Roese6c700492009-11-12 17:19:37 +0100611 * Only configure the master in monach mode
Matthias Fuchs034394a2008-03-30 18:52:44 +0200612 */
Stefan Roese6c700492009-11-12 17:19:37 +0100613 if (is_monarch())
614 __pci_master_init(hose);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100615}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200616#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100617
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100618static void wait_for_pci_ready(void)
619{
620 int i;
621 char *s = getenv("pcidelay");
Matthias Fuchsbe270792008-10-28 13:37:00 +0100622 /*
623 * We have our own handling of the pcidelay variable.
624 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
625 * and adapter devices. For adapter devices we do not
626 * want this.
627 */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100628 if (s) {
629 int ms = simple_strtoul(s, NULL, 10);
630 printf("PCI: Waiting for %d ms\n", ms);
631 for (i=0; i<ms; i++)
632 udelay(1000);
633 }
634
635 if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
636 printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
637 while (1) {
638 if (ctrlc()) {
639 puts("abort\n");
640 break;
641 }
642 if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
643 printf("done\n");
644 break;
645 }
646 }
647 }
648}
649
Matthias Fuchs034394a2008-03-30 18:52:44 +0200650/*
Stefan Roese9a81c612009-10-29 16:54:52 +0100651 * Override weak is_pci_host()
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100652 *
Matthias Fuchs034394a2008-03-30 18:52:44 +0200653 * This routine is called to determine if a pci scan should be
654 * performed. With various hardware environments (especially cPCI and
655 * PPMC) it's insufficient to depend on the state of the arbiter enable
656 * bit in the strap register, or generic host/adapter assumptions.
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100657 *
Matthias Fuchs034394a2008-03-30 18:52:44 +0200658 * Rather than hard-code a bad assumption in the general 440 code, the
659 * 440 pci code requires the board to decide at runtime.
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100660 *
Matthias Fuchs034394a2008-03-30 18:52:44 +0200661 * Return 0 for adapter mode, non-zero for host (monarch) mode.
662 */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100663#if defined(CONFIG_PCI)
664int is_pci_host(struct pci_controller *hose)
665{
666 char *s = getenv("pciscan");
667 if (s == NULL)
668 if (is_monarch()) {
669 wait_for_pci_ready();
670 return 1;
671 } else
672 return 0;
673 else if (!strcmp(s, "yes"))
674 return 1;
675
676 return 0;
677}
678#endif /* defined(CONFIG_PCI) */
Matthias Fuchs034394a2008-03-30 18:52:44 +0200679
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100680#if defined(CONFIG_POST)
681/*
682 * Returns 1 if keys pressed to start the power-on long-running tests
683 * Called from board_init_f().
684 */
685int post_hotkeys_pressed(void)
686{
687 return 0; /* No hotkeys supported */
688}
689#endif /* CONFIG_POST */
690
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100691#ifdef CONFIG_RESET_PHY_R
692void reset_phy(void)
693{
Matthias Fuchs5b67a142008-12-10 15:12:56 +0100694 char *s;
695 unsigned short val_method, val_behavior;
696
697 /* special LED setup for NGCC/CANDES */
698 if ((s = getenv("bd_type")) &&
699 ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
700 val_method = 0x0e0a;
701 val_behavior = 0x0cf2;
702 } else {
703 /* PMC440 standard type */
704 val_method = 0x0e10;
705 val_behavior = 0x0cf0;
706 }
707
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100708 if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
709 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
Matthias Fuchs5b67a142008-12-10 15:12:56 +0100710 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
711 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100712 miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
713 }
714
715 if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
716 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
Matthias Fuchs5b67a142008-12-10 15:12:56 +0100717 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
718 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100719 miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
720 }
721}
722#endif
723
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200724#if defined(CONFIG_SYS_EEPROM_WREN)
Matthias Fuchs034394a2008-03-30 18:52:44 +0200725/*
726 * Input: <dev_addr> I2C address of EEPROM device to enable.
727 * <state> -1: deliver current state
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100728 * 0: disable write
729 * 1: enable write
Matthias Fuchs034394a2008-03-30 18:52:44 +0200730 * Returns: -1: wrong device address
731 * 0: dis-/en- able done
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100732 * 0/1: current state if <state> was -1.
733 */
734int eeprom_write_enable(unsigned dev_addr, int state)
735{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200736 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
737 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100738 return -1;
739 } else {
740 switch (state) {
741 case 1:
742 /* Enable write access, clear bit GPIO_SINT2. */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100743 out_be32((void *)GPIO0_OR,
744 in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100745 state = 0;
746 break;
747 case 0:
748 /* Disable write access, set bit GPIO_SINT2. */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100749 out_be32((void *)GPIO0_OR,
750 in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100751 state = 0;
752 break;
753 default:
754 /* Read current status back. */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100755 state = (0 == (in_be32((void *)GPIO0_OR)
756 & GPIO0_EP_EEP));
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100757 break;
758 }
759 }
760 return state;
761}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200762#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100763
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200764#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
Matthias Fuchs034394a2008-03-30 18:52:44 +0200765int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
766 uchar *buffer, unsigned cnt)
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100767{
768 unsigned end = offset + cnt;
769 unsigned blk_off;
770 int rcode = 0;
771
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200772#if defined(CONFIG_SYS_EEPROM_WREN)
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100773 eeprom_write_enable(dev_addr, 1);
774#endif
Matthias Fuchs034394a2008-03-30 18:52:44 +0200775 /*
776 * Write data until done or would cross a write page boundary.
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100777 * We must write the address again when changing pages
778 * because the address counter only increments within a page.
779 */
780
781 while (offset < end) {
782 unsigned alen, len;
783 unsigned maxlen;
784 uchar addr[2];
785
786 blk_off = offset & 0xFF; /* block offset */
787
788 addr[0] = offset >> 8; /* block number */
789 addr[1] = blk_off; /* block offset */
790 alen = 2;
791 addr[0] |= dev_addr; /* insert device address */
792
793 len = end - offset;
794
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200795#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100796#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
797
Matthias Fuchs034394a2008-03-30 18:52:44 +0200798 maxlen = BOOT_EEPROM_PAGE_SIZE -
799 BOOT_EEPROM_PAGE_OFFSET(blk_off);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100800 if (maxlen > I2C_RXTX_LEN)
801 maxlen = I2C_RXTX_LEN;
802
803 if (len > maxlen)
804 len = maxlen;
805
806 if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
807 rcode = 1;
808
809 buffer += len;
810 offset += len;
811
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200812#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
813 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100814#endif
815 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200816#if defined(CONFIG_SYS_EEPROM_WREN)
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100817 eeprom_write_enable(dev_addr, 0);
818#endif
819 return rcode;
820}
821
Matthias Fuchs034394a2008-03-30 18:52:44 +0200822int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
823 uchar *buffer, unsigned cnt)
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100824{
825 unsigned end = offset + cnt;
826 unsigned blk_off;
827 int rcode = 0;
828
Matthias Fuchs034394a2008-03-30 18:52:44 +0200829 /*
830 * Read data until done or would cross a page boundary.
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100831 * We must write the address again when changing pages
832 * because the next page may be in a different device.
833 */
834 while (offset < end) {
835 unsigned alen, len;
836 unsigned maxlen;
837 uchar addr[2];
838
839 blk_off = offset & 0xFF; /* block offset */
840
841 addr[0] = offset >> 8; /* block number */
842 addr[1] = blk_off; /* block offset */
843 alen = 2;
844
845 addr[0] |= dev_addr; /* insert device address */
846
847 len = end - offset;
848
849 maxlen = 0x100 - blk_off;
850 if (maxlen > I2C_RXTX_LEN)
851 maxlen = I2C_RXTX_LEN;
852 if (len > maxlen)
853 len = maxlen;
854
855 if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
856 rcode = 1;
857 buffer += len;
858 offset += len;
859 }
860
861 return rcode;
862}
863
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200864#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100865int usb_board_init(void)
866{
867 char *act = getenv("usbact");
868 int i;
869
Matthias Fuchsbe270792008-10-28 13:37:00 +0100870 if ((act == NULL || strcmp(act, "host") == 0) &&
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100871 !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
872 /* enable power on USB socket */
Matthias Fuchs034394a2008-03-30 18:52:44 +0200873 out_be32((void*)GPIO1_OR,
874 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
Matthias Fuchs72c5d522007-12-28 17:07:14 +0100875
876 for (i=0; i<1000; i++)
877 udelay(1000);
878
879 return 0;
880}
881
882int usb_board_stop(void)
883{
884 /* disable power on USB socket */
885 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
886 return 0;
887}
888
889int usb_board_init_fail(void)
890{
891 usb_board_stop();
892 return 0;
893}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200894#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
Matthias Fuchsbe270792008-10-28 13:37:00 +0100895
896#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
897void ft_board_setup(void *blob, bd_t *bd)
898{
899 int rc;
900
901 __ft_board_setup(blob, bd);
902
903 /*
904 * Disable PCI in non-monarch mode.
905 */
906 if (!is_monarch()) {
907 rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
908 "disabled", sizeof("disabled"), 1);
909 if (rc) {
910 printf("Unable to update property status in PCI node, err=%s\n",
911 fdt_strerror(rc));
912 }
913 }
914}
915#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */