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wdenk1df49e22002-09-17 21:37:55 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk1df49e22002-09-17 21:37:55 +00006 */
7
8#include <common.h>
9#include <malloc.h>
10#include <net.h>
Ben Warren10efa022008-08-31 20:37:00 -070011#include <netdev.h>
wdenk1df49e22002-09-17 21:37:55 +000012#include <asm/io.h>
13#include <pci.h>
Marian Balakowicz63ff0042005-10-28 22:30:33 +020014#include <miiphy.h>
wdenk1df49e22002-09-17 21:37:55 +000015
16#undef DEBUG
17
wdenk1df49e22002-09-17 21:37:55 +000018 /* Ethernet chip registers.
19 */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020020#define SCBStatus 0 /* Rx/Command Unit Status *Word* */
21#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
22#define SCBCmd 2 /* Rx/Command Unit Command *Word* */
23#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
24#define SCBPointer 4 /* General purpose pointer. */
25#define SCBPort 8 /* Misc. commands and operands. */
26#define SCBflash 12 /* Flash memory control. */
27#define SCBeeprom 14 /* EEPROM memory control. */
28#define SCBCtrlMDI 16 /* MDI interface control. */
29#define SCBEarlyRx 20 /* Early receive byte count. */
30#define SCBGenControl 28 /* 82559 General Control Register */
31#define SCBGenStatus 29 /* 82559 General Status register */
wdenk1df49e22002-09-17 21:37:55 +000032
33 /* 82559 SCB status word defnitions
34 */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020035#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
36#define SCB_STATUS_FR 0x4000 /* frame received */
37#define SCB_STATUS_CNA 0x2000 /* CU left active state */
38#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
39#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
40#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
41#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
wdenk1df49e22002-09-17 21:37:55 +000042
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020043#define SCB_INTACK_MASK 0xFD00 /* all the above */
wdenk1df49e22002-09-17 21:37:55 +000044
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020045#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
46#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
wdenk1df49e22002-09-17 21:37:55 +000047
48 /* System control block commands
49 */
50/* CU Commands */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020051#define CU_NOP 0x0000
52#define CU_START 0x0010
53#define CU_RESUME 0x0020
54#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
55#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
56#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
57#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
wdenk1df49e22002-09-17 21:37:55 +000058
59/* RUC Commands */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020060#define RUC_NOP 0x0000
61#define RUC_START 0x0001
62#define RUC_RESUME 0x0002
63#define RUC_ABORT 0x0004
64#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
65#define RUC_RESUMENR 0x0007
wdenk1df49e22002-09-17 21:37:55 +000066
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020067#define CU_CMD_MASK 0x00f0
68#define RU_CMD_MASK 0x0007
wdenk1df49e22002-09-17 21:37:55 +000069
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020070#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
71#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
wdenk1df49e22002-09-17 21:37:55 +000072
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020073#define CU_STATUS_MASK 0x00C0
74#define RU_STATUS_MASK 0x003C
wdenk1df49e22002-09-17 21:37:55 +000075
Wolfgang Denkc570b2f2005-09-26 01:06:33 +020076#define RU_STATUS_IDLE (0<<2)
77#define RU_STATUS_SUS (1<<2)
78#define RU_STATUS_NORES (2<<2)
79#define RU_STATUS_READY (4<<2)
80#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
wdenk1df49e22002-09-17 21:37:55 +000081#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
82#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
83
84 /* 82559 Port interface commands.
85 */
86#define I82559_RESET 0x00000000 /* Software reset */
87#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
88#define I82559_SELECTIVE_RESET 0x00000002
89#define I82559_DUMP 0x00000003
90#define I82559_DUMP_WAKEUP 0x00000007
91
92 /* 82559 Eeprom interface.
93 */
94#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
95#define EE_CS 0x02 /* EEPROM chip select. */
96#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
97#define EE_WRITE_0 0x01
98#define EE_WRITE_1 0x05
99#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
100#define EE_ENB (0x4800 | EE_CS)
101#define EE_CMD_BITS 3
102#define EE_DATA_BITS 16
103
104 /* The EEPROM commands include the alway-set leading bit.
105 */
106#define EE_EWENB_CMD (4 << addr_len)
107#define EE_WRITE_CMD (5 << addr_len)
108#define EE_READ_CMD (6 << addr_len)
109#define EE_ERASE_CMD (7 << addr_len)
110
111 /* Receive frame descriptors.
112 */
113struct RxFD {
114 volatile u16 status;
115 volatile u16 control;
116 volatile u32 link; /* struct RxFD * */
117 volatile u32 rx_buf_addr; /* void * */
118 volatile u32 count;
119
120 volatile u8 data[PKTSIZE_ALIGN];
121};
122
123#define RFD_STATUS_C 0x8000 /* completion of received frame */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200124#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
wdenk1df49e22002-09-17 21:37:55 +0000125
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200126#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
127#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
128#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
129#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
wdenk1df49e22002-09-17 21:37:55 +0000130
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200131#define RFD_COUNT_MASK 0x3fff
132#define RFD_COUNT_F 0x4000
133#define RFD_COUNT_EOF 0x8000
wdenk1df49e22002-09-17 21:37:55 +0000134
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200135#define RFD_RX_CRC 0x0800 /* crc error */
136#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
137#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
138#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
139#define RFD_RX_SHORT 0x0080 /* short frame error */
140#define RFD_RX_LENGTH 0x0020
141#define RFD_RX_ERROR 0x0010 /* receive error */
142#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
143#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
144#define RFD_RX_TCO 0x0001 /* TCO indication */
wdenk1df49e22002-09-17 21:37:55 +0000145
146 /* Transmit frame descriptors
147 */
148struct TxFD { /* Transmit frame descriptor set. */
149 volatile u16 status;
150 volatile u16 command;
151 volatile u32 link; /* void * */
152 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
153 volatile s32 count;
154
155 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
156 volatile s32 tx_buf_size0; /* Length of Tx frame. */
157 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
158 volatile s32 tx_buf_size1; /* Length of Tx frame. */
159};
160
161#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200162#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
163#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
164#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
165#define TxCB_CMD_S 0x4000 /* suspend on completion */
166#define TxCB_CMD_EL 0x8000 /* last command block in CBL */
wdenk1df49e22002-09-17 21:37:55 +0000167
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200168#define TxCB_COUNT_MASK 0x3fff
169#define TxCB_COUNT_EOF 0x8000
wdenk1df49e22002-09-17 21:37:55 +0000170
171 /* The Speedo3 Rx and Tx frame/buffer descriptors.
172 */
173struct descriptor { /* A generic descriptor. */
174 volatile u16 status;
175 volatile u16 command;
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200176 volatile u32 link; /* struct descriptor * */
wdenk1df49e22002-09-17 21:37:55 +0000177
178 unsigned char params[0];
179};
180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_CMD_EL 0x8000
182#define CONFIG_SYS_CMD_SUSPEND 0x4000
183#define CONFIG_SYS_CMD_INT 0x2000
184#define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
185#define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
wdenk1df49e22002-09-17 21:37:55 +0000186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_STATUS_C 0x8000
188#define CONFIG_SYS_STATUS_OK 0x2000
wdenk1df49e22002-09-17 21:37:55 +0000189
190 /* Misc.
191 */
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200192#define NUM_RX_DESC PKTBUFSRX
193#define NUM_TX_DESC 1 /* Number of TX descriptors */
wdenk1df49e22002-09-17 21:37:55 +0000194
195#define TOUT_LOOP 1000000
196
197#define ETH_ALEN 6
198
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200199static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
200static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
wdenk1df49e22002-09-17 21:37:55 +0000201static int rx_next; /* RX descriptor ring pointer */
202static int tx_next; /* TX descriptor ring pointer */
203static int tx_threshold;
204
205/*
206 * The parameters for a CmdConfigure operation.
207 * There are so many options that it would be difficult to document
208 * each bit. We mostly use the default or recommended settings.
209 */
210static const char i82557_config_cmd[] = {
211 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
212 0, 0x2E, 0, 0x60, 0,
213 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
214 0x3f, 0x05,
215};
216static const char i82558_config_cmd[] = {
217 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
218 0, 0x2E, 0, 0x60, 0x08, 0x88,
219 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
220 0x31, 0x05,
221};
222
223static void init_rx_ring (struct eth_device *dev);
224static void purge_tx_ring (struct eth_device *dev);
225
226static void read_hw_addr (struct eth_device *dev, bd_t * bis);
227
228static int eepro100_init (struct eth_device *dev, bd_t * bis);
Joe Hershbergerbccbe612012-05-21 14:45:25 +0000229static int eepro100_send(struct eth_device *dev, void *packet, int length);
wdenk1df49e22002-09-17 21:37:55 +0000230static int eepro100_recv (struct eth_device *dev);
231static void eepro100_halt (struct eth_device *dev);
232
Wolfgang Denk03b00402014-10-21 15:23:32 +0200233#if defined(CONFIG_E500)
wdenk42d1f032003-10-15 23:53:47 +0000234#define bus_to_phys(a) (a)
235#define phys_to_bus(a) (a)
236#else
wdenk1df49e22002-09-17 21:37:55 +0000237#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
238#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
wdenk42d1f032003-10-15 23:53:47 +0000239#endif
wdenk1df49e22002-09-17 21:37:55 +0000240
241static inline int INW (struct eth_device *dev, u_long addr)
242{
Bin Menge6655d72016-01-25 01:26:26 -0800243 return le16_to_cpu(*(volatile u16 *)(addr + (u_long)dev->iobase));
wdenk1df49e22002-09-17 21:37:55 +0000244}
245
246static inline void OUTW (struct eth_device *dev, int command, u_long addr)
247{
Bin Menge6655d72016-01-25 01:26:26 -0800248 *(volatile u16 *)((addr + (u_long)dev->iobase)) = cpu_to_le16(command);
wdenk1df49e22002-09-17 21:37:55 +0000249}
250
251static inline void OUTL (struct eth_device *dev, int command, u_long addr)
252{
Bin Menge6655d72016-01-25 01:26:26 -0800253 *(volatile u32 *)((addr + (u_long)dev->iobase)) = cpu_to_le32(command);
wdenk1df49e22002-09-17 21:37:55 +0000254}
255
Jon Loeliger07d38a12007-07-09 17:30:01 -0500256#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Wolfgang Denka9127332005-09-26 00:39:59 +0200257static inline int INL (struct eth_device *dev, u_long addr)
258{
Bin Menge6655d72016-01-25 01:26:26 -0800259 return le32_to_cpu(*(volatile u32 *)(addr + (u_long)dev->iobase));
Wolfgang Denka9127332005-09-26 00:39:59 +0200260}
261
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200262static int get_phyreg (struct eth_device *dev, unsigned char addr,
263 unsigned char reg, unsigned short *value)
Wolfgang Denka9127332005-09-26 00:39:59 +0200264{
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200265 int cmd;
266 int timeout = 50;
Wolfgang Denka9127332005-09-26 00:39:59 +0200267
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200268 /* read requested data */
269 cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
Wolfgang Denka9127332005-09-26 00:39:59 +0200270 OUTL (dev, cmd, SCBCtrlMDI);
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200271
Wolfgang Denka9127332005-09-26 00:39:59 +0200272 do {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200273 udelay(1000);
Wolfgang Denka9127332005-09-26 00:39:59 +0200274 cmd = INL (dev, SCBCtrlMDI);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200275 } while (!(cmd & (1 << 28)) && (--timeout));
276
277 if (timeout == 0)
278 return -1;
Wolfgang Denka9127332005-09-26 00:39:59 +0200279
280 *value = (unsigned short) (cmd & 0xffff);
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200281
Wolfgang Denka9127332005-09-26 00:39:59 +0200282 return 0;
283}
284
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200285static int set_phyreg (struct eth_device *dev, unsigned char addr,
286 unsigned char reg, unsigned short value)
Wolfgang Denka9127332005-09-26 00:39:59 +0200287{
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200288 int cmd;
289 int timeout = 50;
Wolfgang Denka9127332005-09-26 00:39:59 +0200290
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200291 /* write requested data */
292 cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
Wolfgang Denka9127332005-09-26 00:39:59 +0200293 OUTL (dev, cmd | value, SCBCtrlMDI);
294
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200295 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
296 udelay(1000);
297
298 if (timeout == 0)
299 return -1;
Wolfgang Denka9127332005-09-26 00:39:59 +0200300
301 return 0;
302}
Wolfgang Denka9127332005-09-26 00:39:59 +0200303
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200304/* Check if given phyaddr is valid, i.e. there is a PHY connected.
305 * Do this by checking model value field from ID2 register.
306 */
Ben Warrend7fb9bc2010-07-29 12:56:11 -0700307static struct eth_device* verify_phyaddr (const char *devname,
308 unsigned char addr)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200309{
310 struct eth_device *dev;
311 unsigned short value;
312 unsigned char model;
313
314 dev = eth_get_dev_by_name(devname);
315 if (dev == NULL) {
316 printf("%s: no such device\n", devname);
317 return NULL;
318 }
319
320 /* read id2 register */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500321 if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200322 printf("%s: mii read timeout!\n", devname);
323 return NULL;
324 }
325
326 /* get model */
327 model = (unsigned char)((value >> 4) & 0x003f);
328
329 if (model == 0) {
330 printf("%s: no PHY at address %d\n", devname, addr);
331 return NULL;
332 }
333
334 return dev;
335}
336
Mike Frysinger5700bb62010-07-27 18:35:08 -0400337static int eepro100_miiphy_read(const char *devname, unsigned char addr,
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200338 unsigned char reg, unsigned short *value)
339{
340 struct eth_device *dev;
341
342 dev = verify_phyaddr(devname, addr);
343 if (dev == NULL)
344 return -1;
345
346 if (get_phyreg(dev, addr, reg, value) != 0) {
347 printf("%s: mii read timeout!\n", devname);
348 return -1;
349 }
350
351 return 0;
352}
353
Mike Frysinger5700bb62010-07-27 18:35:08 -0400354static int eepro100_miiphy_write(const char *devname, unsigned char addr,
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200355 unsigned char reg, unsigned short value)
356{
357 struct eth_device *dev;
358
359 dev = verify_phyaddr(devname, addr);
360 if (dev == NULL)
361 return -1;
362
363 if (set_phyreg(dev, addr, reg, value) != 0) {
364 printf("%s: mii write timeout!\n", devname);
365 return -1;
366 }
367
368 return 0;
369}
370
Jon Loeliger07d38a12007-07-09 17:30:01 -0500371#endif
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200372
373/* Wait for the chip get the command.
374*/
wdenk1df49e22002-09-17 21:37:55 +0000375static int wait_for_eepro100 (struct eth_device *dev)
376{
377 int i;
378
379 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
380 if (i >= TOUT_LOOP) {
381 return 0;
382 }
383 }
384
385 return 1;
386}
387
388static struct pci_device_id supported[] = {
389 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
390 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
391 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
392 {}
393};
394
395int eepro100_initialize (bd_t * bis)
396{
397 pci_dev_t devno;
398 int card_number = 0;
399 struct eth_device *dev;
400 u32 iobase, status;
401 int idx = 0;
402
403 while (1) {
404 /* Find PCI device
405 */
406 if ((devno = pci_find_devices (supported, idx++)) < 0) {
407 break;
408 }
409
410 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
411 iobase &= ~0xf;
412
413#ifdef DEBUG
414 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
415 iobase);
416#endif
417
418 pci_write_config_dword (devno,
419 PCI_COMMAND,
420 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
421
422 /* Check if I/O accesses and Bus Mastering are enabled.
423 */
424 pci_read_config_dword (devno, PCI_COMMAND, &status);
425 if (!(status & PCI_COMMAND_MEMORY)) {
426 printf ("Error: Can not enable MEM access.\n");
427 continue;
428 }
429
430 if (!(status & PCI_COMMAND_MASTER)) {
431 printf ("Error: Can not enable Bus Mastering.\n");
432 continue;
433 }
434
435 dev = (struct eth_device *) malloc (sizeof *dev);
Nobuhiro Iwamatsu72c4c332010-10-19 14:03:41 +0900436 if (!dev) {
437 printf("eepro100: Can not allocate memory\n");
438 break;
439 }
440 memset(dev, 0, sizeof(*dev));
wdenk1df49e22002-09-17 21:37:55 +0000441
442 sprintf (dev->name, "i82559#%d", card_number);
wdenk7a8e9bed2003-05-31 18:35:21 +0000443 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
wdenk1df49e22002-09-17 21:37:55 +0000444 dev->iobase = bus_to_phys (iobase);
wdenk1df49e22002-09-17 21:37:55 +0000445 dev->init = eepro100_init;
446 dev->halt = eepro100_halt;
447 dev->send = eepro100_send;
448 dev->recv = eepro100_recv;
449
450 eth_register (dev);
451
Jon Loeliger07d38a12007-07-09 17:30:01 -0500452#if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200453 /* register mii command access routines */
454 miiphy_register(dev->name,
455 eepro100_miiphy_read, eepro100_miiphy_write);
456#endif
457
wdenk1df49e22002-09-17 21:37:55 +0000458 card_number++;
459
460 /* Set the latency timer for value.
461 */
462 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
463
464 udelay (10 * 1000);
465
466 read_hw_addr (dev, bis);
467 }
468
469 return card_number;
470}
471
472
473static int eepro100_init (struct eth_device *dev, bd_t * bis)
474{
Ben Warren422b1a02008-01-09 18:15:53 -0500475 int i, status = -1;
wdenk1df49e22002-09-17 21:37:55 +0000476 int tx_cur;
477 struct descriptor *ias_cmd, *cfg_cmd;
478
479 /* Reset the ethernet controller
480 */
481 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
482 udelay (20);
483
484 OUTL (dev, I82559_RESET, SCBPort);
485 udelay (20);
486
487 if (!wait_for_eepro100 (dev)) {
488 printf ("Error: Can not reset ethernet controller.\n");
489 goto Done;
490 }
491 OUTL (dev, 0, SCBPointer);
492 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
493
494 if (!wait_for_eepro100 (dev)) {
495 printf ("Error: Can not reset ethernet controller.\n");
496 goto Done;
497 }
498 OUTL (dev, 0, SCBPointer);
499 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
500
501 /* Initialize Rx and Tx rings.
502 */
503 init_rx_ring (dev);
504 purge_tx_ring (dev);
505
506 /* Tell the adapter where the RX ring is located.
507 */
508 if (!wait_for_eepro100 (dev)) {
509 printf ("Error: Can not reset ethernet controller.\n");
510 goto Done;
511 }
512
513 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
514 OUTW (dev, SCB_M | RUC_START, SCBCmd);
515
516 /* Send the Configure frame */
517 tx_cur = tx_next;
518 tx_next = ((tx_next + 1) % NUM_TX_DESC);
519
520 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521 cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
wdenk1df49e22002-09-17 21:37:55 +0000522 cfg_cmd->status = 0;
523 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
524
525 memcpy (cfg_cmd->params, i82558_config_cmd,
526 sizeof (i82558_config_cmd));
527
528 if (!wait_for_eepro100 (dev)) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200529 printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
wdenk1df49e22002-09-17 21:37:55 +0000530 goto Done;
531 }
532
533 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
534 OUTW (dev, SCB_M | CU_START, SCBCmd);
535
536 for (i = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537 !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
wdenk1df49e22002-09-17 21:37:55 +0000538 i++) {
539 if (i >= TOUT_LOOP) {
540 printf ("%s: Tx error buffer not ready\n", dev->name);
541 goto Done;
542 }
543 }
544
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
wdenk1df49e22002-09-17 21:37:55 +0000546 printf ("TX error status = 0x%08X\n",
547 le16_to_cpu (tx_ring[tx_cur].status));
548 goto Done;
549 }
550
551 /* Send the Individual Address Setup frame
552 */
553 tx_cur = tx_next;
554 tx_next = ((tx_next + 1) % NUM_TX_DESC);
555
556 ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557 ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
wdenk1df49e22002-09-17 21:37:55 +0000558 ias_cmd->status = 0;
559 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
560
561 memcpy (ias_cmd->params, dev->enetaddr, 6);
562
563 /* Tell the adapter where the TX ring is located.
564 */
565 if (!wait_for_eepro100 (dev)) {
566 printf ("Error: Can not reset ethernet controller.\n");
567 goto Done;
568 }
569
570 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
571 OUTW (dev, SCB_M | CU_START, SCBCmd);
572
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
wdenk1df49e22002-09-17 21:37:55 +0000574 i++) {
575 if (i >= TOUT_LOOP) {
576 printf ("%s: Tx error buffer not ready\n",
577 dev->name);
578 goto Done;
579 }
580 }
581
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200582 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
wdenk1df49e22002-09-17 21:37:55 +0000583 printf ("TX error status = 0x%08X\n",
584 le16_to_cpu (tx_ring[tx_cur].status));
585 goto Done;
586 }
587
Ben Warren422b1a02008-01-09 18:15:53 -0500588 status = 0;
wdenk1df49e22002-09-17 21:37:55 +0000589
590 Done:
591 return status;
592}
593
Joe Hershbergerbccbe612012-05-21 14:45:25 +0000594static int eepro100_send(struct eth_device *dev, void *packet, int length)
wdenk1df49e22002-09-17 21:37:55 +0000595{
596 int i, status = -1;
597 int tx_cur;
598
599 if (length <= 0) {
600 printf ("%s: bad packet size: %d\n", dev->name, length);
601 goto Done;
602 }
603
604 tx_cur = tx_next;
605 tx_next = (tx_next + 1) % NUM_TX_DESC;
606
607 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
608 TxCB_CMD_SF |
609 TxCB_CMD_S |
610 TxCB_CMD_EL );
611 tx_ring[tx_cur].status = 0;
612 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
613 tx_ring[tx_cur].link =
614 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
615 tx_ring[tx_cur].tx_desc_addr =
616 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
617 tx_ring[tx_cur].tx_buf_addr0 =
618 cpu_to_le32 (phys_to_bus ((u_long) packet));
619 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
620
621 if (!wait_for_eepro100 (dev)) {
622 printf ("%s: Tx error ethernet controller not ready.\n",
623 dev->name);
624 goto Done;
625 }
626
627 /* Send the packet.
628 */
629 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
630 OUTW (dev, SCB_M | CU_START, SCBCmd);
631
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200632 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
wdenk1df49e22002-09-17 21:37:55 +0000633 i++) {
634 if (i >= TOUT_LOOP) {
635 printf ("%s: Tx error buffer not ready\n", dev->name);
636 goto Done;
637 }
638 }
639
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200640 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
wdenk1df49e22002-09-17 21:37:55 +0000641 printf ("TX error status = 0x%08X\n",
642 le16_to_cpu (tx_ring[tx_cur].status));
643 goto Done;
644 }
645
646 status = length;
647
648 Done:
649 return status;
650}
651
652static int eepro100_recv (struct eth_device *dev)
653{
654 u16 status, stat;
655 int rx_prev, length = 0;
656
657 stat = INW (dev, SCBStatus);
658 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
659
660 for (;;) {
661 status = le16_to_cpu (rx_ring[rx_next].status);
662
663 if (!(status & RFD_STATUS_C)) {
664 break;
665 }
666
667 /* Valid frame status.
668 */
669 if ((status & RFD_STATUS_OK)) {
670 /* A valid frame received.
671 */
672 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
673
674 /* Pass the packet up to the protocol
675 * layers.
676 */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500677 net_process_received_packet((u8 *)rx_ring[rx_next].data,
678 length);
wdenk1df49e22002-09-17 21:37:55 +0000679 } else {
680 /* There was an error.
681 */
682 printf ("RX error status = 0x%08X\n", status);
683 }
684
685 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
686 rx_ring[rx_next].status = 0;
687 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
688
689 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
690 rx_ring[rx_prev].control = 0;
691
692 /* Update entry information.
693 */
694 rx_next = (rx_next + 1) % NUM_RX_DESC;
695 }
696
697 if (stat & SCB_STATUS_RNR) {
698
699 printf ("%s: Receiver is not ready, restart it !\n", dev->name);
700
701 /* Reinitialize Rx ring.
702 */
703 init_rx_ring (dev);
704
705 if (!wait_for_eepro100 (dev)) {
706 printf ("Error: Can not restart ethernet controller.\n");
707 goto Done;
708 }
709
710 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
711 OUTW (dev, SCB_M | RUC_START, SCBCmd);
712 }
713
714 Done:
715 return length;
716}
717
718static void eepro100_halt (struct eth_device *dev)
719{
720 /* Reset the ethernet controller
721 */
722 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
723 udelay (20);
724
725 OUTL (dev, I82559_RESET, SCBPort);
726 udelay (20);
727
728 if (!wait_for_eepro100 (dev)) {
729 printf ("Error: Can not reset ethernet controller.\n");
730 goto Done;
731 }
732 OUTL (dev, 0, SCBPointer);
733 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
734
735 if (!wait_for_eepro100 (dev)) {
736 printf ("Error: Can not reset ethernet controller.\n");
737 goto Done;
738 }
739 OUTL (dev, 0, SCBPointer);
740 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
741
742 Done:
743 return;
744}
745
746 /* SROM Read.
747 */
748static int read_eeprom (struct eth_device *dev, int location, int addr_len)
749{
750 unsigned short retval = 0;
751 int read_cmd = location | EE_READ_CMD;
752 int i;
753
754 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
755 OUTW (dev, EE_ENB, SCBeeprom);
756
757 /* Shift the read command bits out. */
758 for (i = 12; i >= 0; i--) {
759 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
760
761 OUTW (dev, EE_ENB | dataval, SCBeeprom);
762 udelay (1);
763 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
764 udelay (1);
765 }
766 OUTW (dev, EE_ENB, SCBeeprom);
767
768 for (i = 15; i >= 0; i--) {
769 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
770 udelay (1);
771 retval = (retval << 1) |
772 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
773 OUTW (dev, EE_ENB, SCBeeprom);
774 udelay (1);
775 }
776
777 /* Terminate the EEPROM access. */
778 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
779 return retval;
780}
781
782#ifdef CONFIG_EEPRO100_SROM_WRITE
783int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
784{
785 unsigned short dataval;
786 int enable_cmd = 0x3f | EE_EWENB_CMD;
787 int write_cmd = location | EE_WRITE_CMD;
788 int i;
789 unsigned long datalong, tmplong;
790
791 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
792 udelay(1);
793 OUTW(dev, EE_ENB, SCBeeprom);
794
795 /* Shift the enable command bits out. */
796 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
797 {
wdenk8bde7f72003-06-27 21:31:46 +0000798 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
799 OUTW(dev, EE_ENB | dataval, SCBeeprom);
800 udelay(1);
801 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
802 udelay(1);
wdenk1df49e22002-09-17 21:37:55 +0000803 }
804
805 OUTW(dev, EE_ENB, SCBeeprom);
806 udelay(1);
807 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
808 udelay(1);
809 OUTW(dev, EE_ENB, SCBeeprom);
810
811
812 /* Shift the write command bits out. */
813 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
814 {
wdenk8bde7f72003-06-27 21:31:46 +0000815 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
816 OUTW(dev, EE_ENB | dataval, SCBeeprom);
817 udelay(1);
818 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
819 udelay(1);
wdenk1df49e22002-09-17 21:37:55 +0000820 }
821
822 /* Write the data */
823 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
824
825 for (i = 0; i< EE_DATA_BITS; i++)
826 {
827 /* Extract and move data bit to bit DI */
828 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
829
830 OUTW(dev, EE_ENB | dataval, SCBeeprom);
831 udelay(1);
832 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
833 udelay(1);
834 OUTW(dev, EE_ENB | dataval, SCBeeprom);
835 udelay(1);
836
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200837 datalong = datalong << 1; /* Adjust significant data bit*/
wdenk1df49e22002-09-17 21:37:55 +0000838 }
839
840 /* Finish up command (toggle CS) */
841 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
Wolfgang Denkc570b2f2005-09-26 01:06:33 +0200842 udelay(1); /* delay for more than 250 ns */
wdenk1df49e22002-09-17 21:37:55 +0000843 OUTW(dev, EE_ENB, SCBeeprom);
844
845 /* Wait for programming ready (D0 = 1) */
846 tmplong = 10;
847 do
848 {
wdenk8bde7f72003-06-27 21:31:46 +0000849 dataval = INW(dev, SCBeeprom);
850 if (dataval & EE_DATA_READ)
851 break;
852 udelay(10000);
wdenk1df49e22002-09-17 21:37:55 +0000853 }
854 while (-- tmplong);
855
856 if (tmplong == 0)
857 {
wdenk8bde7f72003-06-27 21:31:46 +0000858 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
859 return -1;
wdenk1df49e22002-09-17 21:37:55 +0000860 }
861
862 /* Terminate the EEPROM access. */
863 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
864
865 return 0;
866}
867#endif
868
869static void init_rx_ring (struct eth_device *dev)
870{
871 int i;
872
873 for (i = 0; i < NUM_RX_DESC; i++) {
874 rx_ring[i].status = 0;
875 rx_ring[i].control =
876 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
877 rx_ring[i].link =
878 cpu_to_le32 (phys_to_bus
879 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
880 rx_ring[i].rx_buf_addr = 0xffffffff;
881 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
882 }
883
884 rx_next = 0;
885}
886
887static void purge_tx_ring (struct eth_device *dev)
888{
889 int i;
890
891 tx_next = 0;
892 tx_threshold = 0x01208000;
893
894 for (i = 0; i < NUM_TX_DESC; i++) {
895 tx_ring[i].status = 0;
896 tx_ring[i].command = 0;
897 tx_ring[i].link = 0;
898 tx_ring[i].tx_desc_addr = 0;
899 tx_ring[i].count = 0;
900
901 tx_ring[i].tx_buf_addr0 = 0;
902 tx_ring[i].tx_buf_size0 = 0;
903 tx_ring[i].tx_buf_addr1 = 0;
904 tx_ring[i].tx_buf_size1 = 0;
905 }
906}
907
908static void read_hw_addr (struct eth_device *dev, bd_t * bis)
909{
wdenk1df49e22002-09-17 21:37:55 +0000910 u16 sum = 0;
911 int i, j;
912 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
913
914 for (j = 0, i = 0; i < 0x40; i++) {
915 u16 value = read_eeprom (dev, i, addr_len);
916
wdenk1df49e22002-09-17 21:37:55 +0000917 sum += value;
918 if (i < 3) {
919 dev->enetaddr[j++] = value;
920 dev->enetaddr[j++] = value >> 8;
921 }
922 }
923
924 if (sum != 0xBABA) {
925 memset (dev->enetaddr, 0, ETH_ALEN);
926#ifdef DEBUG
927 printf ("%s: Invalid EEPROM checksum %#4.4x, "
928 "check settings before activating this device!\n",
929 dev->name, sum);
930#endif
931 }
932}