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Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05301/*
2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Based on davinci_dvevm.h. Original Copyrights follow:
5 *
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05309 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * Board
16 */
Ben Gardiner3d248d32010-10-14 17:26:29 -040017#define CONFIG_DRIVER_TI_EMAC
Lad, Prabhakar63777662012-06-24 21:35:23 +000018/* check if direct NOR boot config is used */
19#ifndef CONFIG_DIRECT_NOR_BOOT
Stefano Babicd73a8a12010-11-11 15:38:02 +010020#define CONFIG_USE_SPIFLASH
Lad, Prabhakar63777662012-06-24 21:35:23 +000021#endif
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053022
23/*
24 * SoC Configuration
25 */
26#define CONFIG_MACH_DAVINCI_DA850_EVM
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053027#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
Christian Riesch52b0f872011-11-28 23:46:18 +000028#define CONFIG_SOC_DA850 /* TI DA850 SoC */
Christian Rieschb67d8812012-02-02 00:44:39 +000029#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053030#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
31#define CONFIG_SYS_OSCIN_FREQ 24000000
32#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
33#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Sughosh Ganu6b873dc2012-02-02 00:44:41 +000034#define CONFIG_SYS_DA850_PLL_INIT
35#define CONFIG_SYS_DA850_DDR_INIT
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053036
Lad, Prabhakar63777662012-06-24 21:35:23 +000037#ifdef CONFIG_DIRECT_NOR_BOOT
38#define CONFIG_ARCH_CPU_INIT
39#define CONFIG_DA8XX_GPIO
40#define CONFIG_SYS_TEXT_BASE 0x60000000
41#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
42#define CONFIG_DA850_LOWLEVEL
43#else
44#define CONFIG_SYS_TEXT_BASE 0xc1080000
45#endif
46
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053047/*
48 * Memory Info
49 */
50#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053051#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
52#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
Ben Gardiner97003752010-08-23 09:08:15 -040053#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053054
55/* memtest start addr */
56#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
57
58/* memtest will be run on 16MB */
59#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
60
61#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053062
Christian Riesch3d2c8e62011-12-09 09:47:37 +000063#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
64 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
65 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
66 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
67 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
68 DAVINCI_SYSCFG_SUSPSRC_I2C)
69
70/*
71 * PLL configuration
72 */
73#define CONFIG_SYS_DV_CLKMODE 0
74#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
75#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
76#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
77#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
78#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
79#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
80#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
81#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
82
83#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
84#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
85#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
86#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
87
88#define CONFIG_SYS_DA850_PLL0_PLLM 24
89#define CONFIG_SYS_DA850_PLL1_PLLM 21
90
91/*
92 * DDR2 memory configuration
93 */
94#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
95 DV_DDR_PHY_EXT_STRBEN | \
96 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
97
98#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
99 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
100 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
101 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
102 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
103 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
104 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
105 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
106
107/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
108#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
109
110#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
111 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
112 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
113 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
114 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
115 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
116 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
117 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
118 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
119
120#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
121 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
122 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
123 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
124 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
125 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
126 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
127 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
128
129#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
130#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
131
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530132/*
133 * Serial Driver info
134 */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530135#define CONFIG_SYS_NS16550_SERIAL
136#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
137#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
138#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
139#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
140#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530141
Stefano Babicd73a8a12010-11-11 15:38:02 +0100142#define CONFIG_SPI
Stefano Babicd73a8a12010-11-11 15:38:02 +0100143#define CONFIG_DAVINCI_SPI
144#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
145#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
146#define CONFIG_SF_DEFAULT_SPEED 30000000
147#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
148
Lad, Prabhakar42612102012-06-24 21:35:19 +0000149#ifdef CONFIG_USE_SPIFLASH
150#define CONFIG_SPL_SPI_SUPPORT
151#define CONFIG_SPL_SPI_FLASH_SUPPORT
152#define CONFIG_SPL_SPI_LOAD
Lad, Prabhakar42612102012-06-24 21:35:19 +0000153#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
Peter Howard2a10f8b2014-12-17 12:14:36 +1100154#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
Lad, Prabhakar42612102012-06-24 21:35:19 +0000155#endif
156
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530157/*
158 * I2C Configuration
159 */
Vitaly Andrianove8459dc2014-04-04 13:16:52 -0400160#define CONFIG_SYS_I2C
161#define CONFIG_SYS_I2C_DAVINCI
162#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
163#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500164#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530165
166/*
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400167 * Flash & Environment
168 */
169#ifdef CONFIG_USE_NAND
170#undef CONFIG_ENV_IS_IN_FLASH
171#define CONFIG_NAND_DAVINCI
172#define CONFIG_SYS_NO_FLASH
173#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
174#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
175#define CONFIG_ENV_SIZE (128 << 10)
176#define CONFIG_SYS_NAND_USE_FLASH_BBT
177#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
178#define CONFIG_SYS_NAND_PAGE_2K
179#define CONFIG_SYS_NAND_CS 3
180#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Eric Benard34fa0702013-04-22 05:55:00 +0000181#define CONFIG_SYS_NAND_MASK_CLE 0x10
182#define CONFIG_SYS_NAND_MASK_ALE 0x8
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400183#undef CONFIG_SYS_NAND_HW_ECC
184#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000185#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
186#define CONFIG_SYS_NAND_5_ADDR_CYCLE
187#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
188#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
189#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
190#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
191#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
192#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
193#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
194 CONFIG_SYS_NAND_U_BOOT_SIZE - \
195 CONFIG_SYS_MALLOC_LEN - \
196 GENERATED_GBL_DATA_SIZE)
197#define CONFIG_SYS_NAND_ECCPOS { \
198 24, 25, 26, 27, 28, \
199 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
200 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
201 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
202 59, 60, 61, 62, 63 }
203#define CONFIG_SYS_NAND_PAGE_COUNT 64
204#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
205#define CONFIG_SYS_NAND_ECCSIZE 512
206#define CONFIG_SYS_NAND_ECCBYTES 10
207#define CONFIG_SYS_NAND_OOBSIZE 64
208#define CONFIG_SPL_NAND_SUPPORT
Scott Wood6f2f01b2012-09-20 19:09:07 -0500209#define CONFIG_SPL_NAND_BASE
210#define CONFIG_SPL_NAND_DRIVERS
211#define CONFIG_SPL_NAND_ECC
Lad, Prabhakar122f9c92012-06-24 21:35:22 +0000212#define CONFIG_SPL_NAND_SIMPLE
213#define CONFIG_SPL_NAND_LOAD
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400214#endif
215
216/*
Ben Gardiner3d248d32010-10-14 17:26:29 -0400217 * Network & Ethernet Configuration
218 */
219#ifdef CONFIG_DRIVER_TI_EMAC
Ben Gardiner3d248d32010-10-14 17:26:29 -0400220#define CONFIG_MII
Ben Gardiner3d248d32010-10-14 17:26:29 -0400221#define CONFIG_BOOTP_DNS
222#define CONFIG_BOOTP_DNS2
223#define CONFIG_BOOTP_SEND_HOSTNAME
224#define CONFIG_NET_RETRY_COUNT 10
Ben Gardiner3d248d32010-10-14 17:26:29 -0400225#endif
226
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -0400227#ifdef CONFIG_USE_NOR
228#define CONFIG_ENV_IS_IN_FLASH
229#define CONFIG_FLASH_CFI_DRIVER
230#define CONFIG_SYS_FLASH_CFI
231#define CONFIG_SYS_FLASH_PROTECTION
232#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
233#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
234#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
235#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
236#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
237#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
238#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
239 + 3)
240#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
241#endif
242
Stefano Babicd73a8a12010-11-11 15:38:02 +0100243#ifdef CONFIG_USE_SPIFLASH
244#undef CONFIG_ENV_IS_IN_FLASH
245#undef CONFIG_ENV_IS_IN_NAND
246#define CONFIG_ENV_IS_IN_SPI_FLASH
247#define CONFIG_ENV_SIZE (64 << 10)
Peter Howard2a10f8b2014-12-17 12:14:36 +1100248#define CONFIG_ENV_OFFSET (512 << 10)
Stefano Babicd73a8a12010-11-11 15:38:02 +0100249#define CONFIG_ENV_SECT_SIZE (64 << 10)
250#define CONFIG_SYS_NO_FLASH
251#endif
252
Ben Gardiner3d248d32010-10-14 17:26:29 -0400253/*
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530254 * U-Boot general configuration
255 */
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400256#define CONFIG_MISC_INIT_R
Christian Rieschae5c77d2011-10-13 00:52:29 +0000257#define CONFIG_BOARD_EARLY_INIT_F
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530258#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530259#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
260#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
261#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
262#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
263#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
264#define CONFIG_VERSION_VARIABLE
265#define CONFIG_AUTO_COMPLETE
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530266#define CONFIG_CMDLINE_EDITING
267#define CONFIG_SYS_LONGHELP
268#define CONFIG_CRC32_VERIFY
269#define CONFIG_MX_CYCLIC
270
271/*
272 * Linux Information
273 */
Ben Gardiner59e0d612010-10-14 17:26:32 -0400274#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400275#define CONFIG_HWCONFIG /* enable hwconfig */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530276#define CONFIG_CMDLINE_TAG
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500277#define CONFIG_REVISION_TAG
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530278#define CONFIG_SETUP_MEMORY_TAGS
279#define CONFIG_BOOTARGS \
280 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400281#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530282
283/*
284 * U-Boot commands
285 */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530286#define CONFIG_CMD_ENV
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530287#define CONFIG_CMD_DIAG
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530288#define CONFIG_CMD_SAVES
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530289
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000290#ifdef CONFIG_CMD_BDI
291#define CONFIG_CLOCKS
292#endif
293
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530294#ifndef CONFIG_DRIVER_TI_EMAC
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530295#endif
296
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400297#ifdef CONFIG_USE_NAND
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400298#define CONFIG_CMD_NAND
Ben Gardiner771d0282010-10-14 17:26:27 -0400299
300#define CONFIG_CMD_MTDPARTS
301#define CONFIG_MTD_DEVICE
302#define CONFIG_MTD_PARTITIONS
303#define CONFIG_LZO
304#define CONFIG_RBTREE
305#define CONFIG_CMD_UBI
306#define CONFIG_CMD_UBIFS
Ben Gardiner6b2c6462010-10-14 17:26:25 -0400307#endif
308
Stefano Babicd73a8a12010-11-11 15:38:02 +0100309#ifdef CONFIG_USE_SPIFLASH
Stefano Babicd73a8a12010-11-11 15:38:02 +0100310#endif
311
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530312#if !defined(CONFIG_USE_NAND) && \
313 !defined(CONFIG_USE_NOR) && \
314 !defined(CONFIG_USE_SPIFLASH)
315#define CONFIG_ENV_IS_NOWHERE
316#define CONFIG_SYS_NO_FLASH
317#define CONFIG_ENV_SIZE (16 << 10)
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530318#undef CONFIG_CMD_ENV
319#endif
320
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000321/* SD/MMC configuration */
Rajashekhara, Sudhakar4a5edda2012-06-24 21:35:17 +0000322#ifndef CONFIG_USE_NOR
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000323#define CONFIG_MMC
324#define CONFIG_DAVINCI_MMC_SD1
325#define CONFIG_GENERIC_MMC
326#define CONFIG_DAVINCI_MMC
Rajashekhara, Sudhakar4a5edda2012-06-24 21:35:17 +0000327#endif
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000328
329/*
330 * Enable MMC commands only when
331 * MMC support is present
332 */
333#ifdef CONFIG_MMC
334#define CONFIG_DOS_PARTITION
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000335#endif
336
Lad, Prabhakar63777662012-06-24 21:35:23 +0000337#ifndef CONFIG_DIRECT_NOR_BOOT
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000338/* defines for SPL */
Tom Rini3f7f2412012-08-14 12:27:13 -0700339#define CONFIG_SPL_FRAMEWORK
340#define CONFIG_SPL_BOARD_INIT
341#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
342 CONFIG_SYS_MALLOC_LEN)
343#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
344#define CONFIG_SPL_SPI_SUPPORT
345#define CONFIG_SPL_SPI_FLASH_SUPPORT
346#define CONFIG_SPL_SPI_LOAD
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000347#define CONFIG_SPL_SERIAL_SUPPORT
348#define CONFIG_SPL_LIBCOMMON_SUPPORT
349#define CONFIG_SPL_LIBGENERIC_SUPPORT
Sughosh Ganu6b873dc2012-02-02 00:44:41 +0000350#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000351#define CONFIG_SPL_STACK 0x8001ff00
352#define CONFIG_SPL_TEXT_BASE 0x80000000
Albert ARIBAUDb7b5f1a2013-04-12 05:14:32 +0000353#define CONFIG_SPL_MAX_FOOTPRINT 32768
Christian Riesch532d5312014-05-07 10:16:28 +0200354#define CONFIG_SPL_PAD_TO 32768
Lad, Prabhakar63777662012-06-24 21:35:23 +0000355#endif
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000356
357/* Load U-Boot Image From MMC */
358#ifdef CONFIG_SPL_MMC_LOAD
359#define CONFIG_SPL_MMC_SUPPORT
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000360#define CONFIG_SPL_LIBDISK_SUPPORT
Tom Rini3f7f2412012-08-14 12:27:13 -0700361#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75
362#undef CONFIG_SPL_SPI_SUPPORT
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000363#undef CONFIG_SPL_SPI_LOAD
364#endif
365
Heiko Schocherab86f722010-09-17 13:10:42 +0200366/* additions for new relocation code, must added to all boards */
Heiko Schocherab86f722010-09-17 13:10:42 +0200367#define CONFIG_SYS_SDRAM_BASE 0xc0000000
Lad, Prabhakar63777662012-06-24 21:35:23 +0000368
369#ifdef CONFIG_DIRECT_NOR_BOOT
370#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
371#else
Heiko Schocherab86f722010-09-17 13:10:42 +0200372#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200373 GENERATED_GBL_DATA_SIZE)
Lad, Prabhakar63777662012-06-24 21:35:23 +0000374#endif /* CONFIG_DIRECT_NOR_BOOT */
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530375#endif /* __CONFIG_H */