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Stefan Roese4745aca2007-02-20 10:57:08 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese4745aca2007-02-20 10:57:08 +01008 */
9
10/************************************************************************
11 * katmai.h - configuration for AMCC Katmai (440SPe)
12 ***********************************************************************/
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020016
Stefan Roese4745aca2007-02-20 10:57:08 +010017/*-----------------------------------------------------------------------
18 * High Level Configuration Options
19 *----------------------------------------------------------------------*/
20#define CONFIG_KATMAI 1 /* Board is Katmai */
Stefan Roese4745aca2007-02-20 10:57:08 +010021#define CONFIG_440 1 /* ... PPC440 family */
22#define CONFIG_440SPE 1 /* Specifc SPe support */
Stefan Roese2a72e9e2010-04-09 14:03:59 +020023#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
Stefan Roese4745aca2007-02-20 10:57:08 +010024#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
Stefan Roese490f2042008-06-06 15:55:03 +020026
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
28
Stefan Roese490f2042008-06-06 15:55:03 +020029/*
Stefan Roese5d812b82008-07-09 17:33:57 +020030 * Enable this board for more than 2GB of SDRAM
31 */
32#define CONFIG_PHYS_64BIT
33#define CONFIG_VERY_BIG_RAM
Stefan Roese5d812b82008-07-09 17:33:57 +020034
35/*
Stefan Roese490f2042008-06-06 15:55:03 +020036 * Include common defines/options for all AMCC eval boards
37 */
38#define CONFIG_HOSTNAME katmai
39#include "amcc-common.h"
Stefan Roese4745aca2007-02-20 10:57:08 +010040
41#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Stefan Roese4745aca2007-02-20 10:57:08 +010042#undef CONFIG_SHOW_BOOT_PROGRESS
43
44/*-----------------------------------------------------------------------
45 * Base addresses -- Note these are effective addresses where the
46 * actual resources get mapped (not physical addresses)
47 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
Stefan Roese4745aca2007-02-20 10:57:08 +010050
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
52#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
53#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
Stefan Roese4745aca2007-02-20 10:57:08 +010054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
56#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
57#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
Stefan Roese4745aca2007-02-20 10:57:08 +010058
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
60#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
61#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
62#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
63#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
64#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
Stefan Roese4745aca2007-02-20 10:57:08 +010065
Stefan Roese97923772007-10-05 09:18:23 +020066/* base address of inbound PCIe window */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
Stefan Roese97923772007-10-05 09:18:23 +020068
Stefan Roese4745aca2007-02-20 10:57:08 +010069/* System RAM mapped to PCI space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
71#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
Stefan Roese4745aca2007-02-20 10:57:08 +010072#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
Stefan Roese4745aca2007-02-20 10:57:08 +010075
76/*-----------------------------------------------------------------------
77 * Initial RAM & stack pointer (placed in internal SRAM)
78 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_TEMP_STACK_OCM 1
80#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
81#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +020082#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Stefan Roese4745aca2007-02-20 10:57:08 +010083
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020084#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020085#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Stefan Roese4745aca2007-02-20 10:57:08 +010086
87/*-----------------------------------------------------------------------
88 * Serial Port
89 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020090#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Stefan Roese4745aca2007-02-20 10:57:08 +010092
93/*-----------------------------------------------------------------------
94 * DDR SDRAM
95 *----------------------------------------------------------------------*/
96#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
Stefan Roeseba58e4c2007-03-01 21:11:36 +010097#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
Stefan Roese2721a682007-03-08 10:07:18 +010098#define CONFIG_DDR_ECC 1 /* with ECC support */
Stefan Roese845c6c92008-01-05 09:12:41 +010099#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
Stefan Roese4745aca2007-02-20 10:57:08 +0100100#undef CONFIG_STRESS
Stefan Roese4745aca2007-02-20 10:57:08 +0100101
102/*-----------------------------------------------------------------------
103 * I2C
104 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000105#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Stefan Roese4745aca2007-02-20 10:57:08 +0100106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
Stefan Roese4745aca2007-02-20 10:57:08 +0100108
109#define IIC0_BOOTPROM_ADDR 0x50
110#define IIC0_ALT_BOOTPROM_ADDR 0x54
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
113#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
114#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
115#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese4745aca2007-02-20 10:57:08 +0100116
Stefan Roeseefe12bc2009-11-09 14:15:42 +0100117/* I2C bootstrap EEPROM */
118#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
119#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
120#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
121
Stefan Roese4745aca2007-02-20 10:57:08 +0100122/* I2C RTC */
123#define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
125#define CONFIG_SYS_I2C_RTC_ADDR 0x68
126#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
Stefan Roese4745aca2007-02-20 10:57:08 +0100127
128/* I2C DTT */
129#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
Stefan Roese4745aca2007-02-20 10:57:08 +0100131/*
132 * standard dtt sensor configuration - bottom bit will determine local or
133 * remote sensor of the ADM1021, the rest determines index into
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134 * CONFIG_SYS_DTT_ADM1021 array below.
Stefan Roese4745aca2007-02-20 10:57:08 +0100135 */
136#define CONFIG_DTT_SENSORS { 0, 1 }
137
138/*
139 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
140 * there will be one entry in this array for each two (dummy) sensors in
141 * CONFIG_DTT_SENSORS.
142 *
143 * For Katmai board:
144 * - only one ADM1021
145 * - i2c addr 0x18
146 * - conversion rate 0x02 = 0.25 conversions/second
147 * - ALERT ouput disabled
148 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
149 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
Stefan Roese4745aca2007-02-20 10:57:08 +0100152
153/*-----------------------------------------------------------------------
154 * Environment
155 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200156#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
Stefan Roese4745aca2007-02-20 10:57:08 +0100157
Stefan Roese490f2042008-06-06 15:55:03 +0200158/*
159 * Default environment variables
160 */
Stefan Roese4745aca2007-02-20 10:57:08 +0100161#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200162 CONFIG_AMCC_DEF_ENV \
163 CONFIG_AMCC_DEF_ENV_POWERPC \
Stefan Roese490f2042008-06-06 15:55:03 +0200164 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roesefc21cd52010-08-03 10:29:50 +0200165 "kernel_addr=ff000000\0" \
166 "fdt_addr=ff1e0000\0" \
167 "ramdisk_addr=ff200000\0" \
Grzegorz Bernacki6efc1fc2007-09-07 18:35:37 +0200168 "pciconfighost=1\0" \
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200169 "pcie_mode=RP:RP:RP\0" \
Stefan Roese4745aca2007-02-20 10:57:08 +0100170 ""
Stefan Roese4745aca2007-02-20 10:57:08 +0100171
Jon Loeligerbc234c12007-07-04 22:32:51 -0500172/*
Stefan Roese490f2042008-06-06 15:55:03 +0200173 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -0500174 */
Stefan Roeseefe12bc2009-11-09 14:15:42 +0100175#define CONFIG_CMD_CHIP_CONFIG
Jon Loeligerbc234c12007-07-04 22:32:51 -0500176#define CONFIG_CMD_DATE
Stefan Roesee3722862010-07-22 19:06:14 +0200177#define CONFIG_CMD_ECCTEST
Jon Loeligerbc234c12007-07-04 22:32:51 -0500178#define CONFIG_CMD_PCI
Jon Loeligerbc234c12007-07-04 22:32:51 -0500179#define CONFIG_CMD_SDRAM
Stefan Roese4745aca2007-02-20 10:57:08 +0100180
181#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
Stefan Roese4745aca2007-02-20 10:57:08 +0100182#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
183#define CONFIG_HAS_ETH0
184#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
185#define CONFIG_PHY_RESET_DELAY 1000
186#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
187#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Stefan Roese4745aca2007-02-20 10:57:08 +0100188
189/*-----------------------------------------------------------------------
190 * FLASH related
191 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200193#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
195#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Stefan Roese4745aca2007-02-20 10:57:08 +0100196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
198#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
199#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Stefan Roese4745aca2007-02-20 10:57:08 +0100200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#undef CONFIG_SYS_FLASH_CHECKSUM
202#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
203#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese4745aca2007-02-20 10:57:08 +0100204
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200205#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200207#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese4745aca2007-02-20 10:57:08 +0100208
209/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200210#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
211#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese4745aca2007-02-20 10:57:08 +0100212
213/*-----------------------------------------------------------------------
214 * PCI stuff
215 *-----------------------------------------------------------------------
216 */
217/* General PCI */
218#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000219#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese4745aca2007-02-20 10:57:08 +0100220#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
221#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
Grzegorz Bernacki6efc1fc2007-09-07 18:35:37 +0200222#define CONFIG_PCI_CONFIG_HOST_BRIDGE
Stefan Roese4745aca2007-02-20 10:57:08 +0100223
224/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
226#undef CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese4745aca2007-02-20 10:57:08 +0100227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
229#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
230/* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
Stefan Roese4745aca2007-02-20 10:57:08 +0100231
232/*
233 * NETWORK Support (PCI):
234 */
235/* Support for Intel 82557/82559/82559ER chips. */
236#define CONFIG_EEPRO100
237
238/*-----------------------------------------------------------------------
239 * Xilinx System ACE support
240 *----------------------------------------------------------------------*/
241#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
243#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
Stefan Roese4745aca2007-02-20 10:57:08 +0100244#define CONFIG_DOS_PARTITION 1
245
246/*-----------------------------------------------------------------------
247 * External Bus Controller (EBC) Setup
248 *----------------------------------------------------------------------*/
249
250/* Memory Bank 0 (Flash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100252 EBC_BXAP_TWT_ENCODE(7) | \
253 EBC_BXAP_BCE_DISABLE | \
254 EBC_BXAP_BCT_2TRANS | \
255 EBC_BXAP_CSN_ENCODE(0) | \
256 EBC_BXAP_OEN_ENCODE(0) | \
257 EBC_BXAP_WBN_ENCODE(0) | \
258 EBC_BXAP_WBF_ENCODE(0) | \
259 EBC_BXAP_TH_ENCODE(0) | \
260 EBC_BXAP_RE_DISABLED | \
261 EBC_BXAP_SOR_DELAYED | \
262 EBC_BXAP_BEM_WRITEONLY | \
263 EBC_BXAP_PEN_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100265 EBC_BXCR_BS_16MB | \
266 EBC_BXCR_BU_RW | \
267 EBC_BXCR_BW_16BIT)
268
269/* Memory Bank 1 (Xilinx System ACE controller) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
Stefan Roesed2168622007-04-19 09:53:52 +0200271 EBC_BXAP_TWT_ENCODE(4) | \
272 EBC_BXAP_BCE_DISABLE | \
273 EBC_BXAP_BCT_2TRANS | \
274 EBC_BXAP_CSN_ENCODE(0) | \
275 EBC_BXAP_OEN_ENCODE(0) | \
276 EBC_BXAP_WBN_ENCODE(0) | \
277 EBC_BXAP_WBF_ENCODE(0) | \
278 EBC_BXAP_TH_ENCODE(0) | \
279 EBC_BXAP_RE_DISABLED | \
280 EBC_BXAP_SOR_NONDELAYED | \
281 EBC_BXAP_BEM_WRITEONLY | \
282 EBC_BXAP_PEN_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100284 EBC_BXCR_BS_1MB | \
285 EBC_BXCR_BU_RW | \
286 EBC_BXCR_BW_16BIT)
287
288/*-------------------------------------------------------------------------
289 * Initialize EBC CONFIG -
290 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
291 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
292 *-------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100294 EBC_CFG_PTD_ENABLE | \
295 EBC_CFG_RTC_16PERCLK | \
296 EBC_CFG_ATC_PREVIOUS | \
297 EBC_CFG_DTC_PREVIOUS | \
298 EBC_CFG_CTC_PREVIOUS | \
299 EBC_CFG_OEO_PREVIOUS | \
300 EBC_CFG_EMC_DEFAULT | \
301 EBC_CFG_PME_DISABLE | \
302 EBC_CFG_PR_16)
303
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100304/*-----------------------------------------------------------------------
305 * GPIO Setup
306 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
308#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
309#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
310#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
313 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
314 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
315 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
316#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
317#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
318#define CONFIG_SYS_GPIO_ODR 0
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100319
Stefan Roese4745aca2007-02-20 10:57:08 +0100320#endif /* __CONFIG_H */