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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26
27#include <mpc8xx.h>
28#include <commproc.h>
29
30#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
31void cpm_load_patch (volatile immap_t * immr);
32#endif
33
34/*
35 * Breath some life into the CPU...
36 *
37 * Set up the memory map,
38 * initialize a bunch of registers,
39 * initialize the UPM's
40 */
41void cpu_init_f (volatile immap_t * immr)
42{
43#ifndef CONFIG_MBX
44 volatile memctl8xx_t *memctl = &immr->im_memctl;
45 ulong reg;
46#endif
47
48 /* SYPCR - contains watchdog control (11-9) */
49
50 immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
51
52#if defined(CONFIG_WATCHDOG)
53 reset_8xx_watchdog (immr);
54#endif /* CONFIG_WATCHDOG */
55
56 /* SIUMCR - contains debug pin configuration (11-6) */
57
58 immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
59
60 /* initialize timebase status and control register (11-26) */
61 /* unlock TBSCRK */
62
63 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
64 immr->im_sit.sit_tbscr = CFG_TBSCR;
65
66 /* initialize the PIT (11-31) */
67
68 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
69 immr->im_sit.sit_piscr = CFG_PISCR;
70
wdenk1cb8e982003-03-06 21:55:29 +000071 /* System integration timers. Don't change EBDF! (15-27) */
72
73 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
74 reg = immr->im_clkrst.car_sccr;
75 reg &= SCCR_MASK;
76 reg |= CFG_SCCR;
77 immr->im_clkrst.car_sccr = reg;
78
wdenk4a9cbbe2002-08-27 09:48:53 +000079 /* PLL (CPU clock) settings (15-30) */
80
81 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
82
83#ifndef CONFIG_MBX /* MBX board does things different */
84
85 /* If CFG_PLPRCR (set in the various *_config.h files) tries to
86 * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
87 * otherwise OR in CFG_PLPRCR so we do not change the currentMF
88 * field value.
89 */
90#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
91 reg = CFG_PLPRCR; /* reset control bits */
92#else
93 reg = immr->im_clkrst.car_plprcr;
94 reg &= PLPRCR_MF_MSK; /* isolate MF field */
95 reg |= CFG_PLPRCR; /* reset control bits */
96#endif
97 immr->im_clkrst.car_plprcr = reg;
98
wdenk4a9cbbe2002-08-27 09:48:53 +000099 /*
100 * Memory Controller:
101 */
102
103 /* perform BR0 reset that MPC850 Rev. A can't guarantee */
104 reg = memctl->memc_br0;
105 reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
106 reg |= BR_V; /* then add just the "Bank Valid" bit */
107 memctl->memc_br0 = reg;
108
109 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
110 * preliminary addresses - these have to be modified later
111 * when FLASH size has been determined
112 *
113 * Depending on the size of the memory region defined by
114 * CFG_OR0_REMAP some boards (wide address mask) allow to map the
115 * CFG_MONITOR_BASE, while others (narrower address mask) can't
116 * map CFG_MONITOR_BASE.
117 *
118 * For example, for CONFIG_IVMS8, the CFG_MONITOR_BASE is
119 * 0xff000000, but CFG_OR0_REMAP's address mask is 0xfff80000.
120 *
121 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
122 * base address remains as 0x00000000. However, the address mask
123 * have been narrowed to 512Kb, so CFG_MONITOR_BASE wasn't mapped
124 * into the Bank0.
125 *
126 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
127 * CFG_BR0_PRELIM in advance.
128 *
129 * [Thanks to Michael Liao for this explanation.
130 * I owe him a free beer. - wd]
131 */
132
133#if defined(CONFIG_GTH) || \
134 defined(CONFIG_HERMES) || \
135 defined(CONFIG_ICU862) || \
136 defined(CONFIG_IP860) || \
137 defined(CONFIG_IVML24) || \
138 defined(CONFIG_IVMS8) || \
139 defined(CONFIG_LWMON) || \
140 defined(CONFIG_MHPC) || \
141 defined(CONFIG_PCU_E) || \
142 defined(CONFIG_R360MPI) || \
143 defined(CONFIG_RPXCLASSIC) || \
144 defined(CONFIG_RPXLITE) || \
145 defined(CONFIG_SPD823TS) || \
146 (defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
147
148 memctl->memc_br0 = CFG_BR0_PRELIM;
149#endif
150
151#if defined(CFG_OR0_REMAP)
152 memctl->memc_or0 = CFG_OR0_REMAP;
153#endif
154#if defined(CFG_OR1_REMAP)
155 memctl->memc_or1 = CFG_OR1_REMAP;
156#endif
157#if defined(CFG_OR5_REMAP)
158 memctl->memc_or5 = CFG_OR5_REMAP;
159#endif
160
161 /* now restrict to preliminary range */
162 memctl->memc_br0 = CFG_BR0_PRELIM;
163 memctl->memc_or0 = CFG_OR0_PRELIM;
164
165#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
166 memctl->memc_or1 = CFG_OR1_PRELIM;
167 memctl->memc_br1 = CFG_BR1_PRELIM;
168#endif
169
170#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
171 memctl->memc_br0 = 0;
172#endif
173
174#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
175 memctl->memc_or2 = CFG_OR2_PRELIM;
176 memctl->memc_br2 = CFG_BR2_PRELIM;
177#endif
178
179#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
180 memctl->memc_or3 = CFG_OR3_PRELIM;
181 memctl->memc_br3 = CFG_BR3_PRELIM;
182#endif
183
184#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
185 memctl->memc_or4 = CFG_OR4_PRELIM;
186 memctl->memc_br4 = CFG_BR4_PRELIM;
187#endif
188
189#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
190 memctl->memc_or5 = CFG_OR5_PRELIM;
191 memctl->memc_br5 = CFG_BR5_PRELIM;
192#endif
193
194#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
195 memctl->memc_or6 = CFG_OR6_PRELIM;
196 memctl->memc_br6 = CFG_BR6_PRELIM;
197#endif
198
199#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
200 memctl->memc_or7 = CFG_OR7_PRELIM;
201 memctl->memc_br7 = CFG_BR7_PRELIM;
202#endif
203
204#endif /* ! CONFIG_MBX */
205
206 /*
207 * Reset CPM
208 */
209 immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
210 do { /* Spin until command processed */
211 __asm__ ("eieio");
212 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
213
214#ifdef CONFIG_MBX
215 /*
216 * on the MBX, things are a little bit different:
217 * - we need to read the VPD to get board information
218 * - the plprcr is set up dynamically
219 * - the memory controller is set up dynamically
220 */
221 mbx_init ();
222#endif /* CONFIG_MBX */
223
224#ifdef CONFIG_RPXCLASSIC
225 rpxclassic_init ();
226#endif
227
228#ifdef CFG_RCCR /* must be done before cpm_load_patch() */
229 /* write config value */
230 immr->im_cpm.cp_rccr = CFG_RCCR;
231#endif
232
233#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH)
234 cpm_load_patch (immr); /* load mpc8xx microcode patch */
235#endif
236}
237
238/*
239 * initialize higher level parts of CPU like timers
240 */
241int cpu_init_r (void)
242{
243#if defined(CFG_RTCSC) || defined(CFG_RMDS)
244 DECLARE_GLOBAL_DATA_PTR;
245
246 bd_t *bd = gd->bd;
247 volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
248#endif
249
250#ifdef CFG_RTCSC
251 /* Unlock RTSC register */
252 immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
253 /* write config value */
254 immr->im_sit.sit_rtcsc = CFG_RTCSC;
255#endif
256
257#ifdef CFG_RMDS
258 /* write config value */
259 immr->im_cpm.cp_rmds = CFG_RMDS;
260#endif
261 return (0);
262}