Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 1d0350ed0b1b0f63e3fb5db6b19397b84a2ea1c7 / . / include / SA-1100.h
blob: f1f9625c3da08b7d1c5270ccc9930114b7b2d26a [file] [log] [blame]
wdenk3b58acd2002-03-27 13:48:44 +0000[diff] [blame]1/*
2 * FILE SA-1100.h
3 *
4 * Version 1.2
5 * Author Copyright (c) Marc A. Viredaz, 1998
6 * DEC Western Research Laboratory, Palo Alto, CA
7 * Date January 1998 (April 1997)
8 * System StrongARM SA-1100
9 * Language C or ARM Assembly
10 * Purpose Definition of constants related to the StrongARM
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
12 * architecture version 4). This file is based on the
13 * StrongARM SA-1100 data sheet version 2.2.
14 *
15 * Language-specific definitions are selected by the
16 * macro "LANGUAGE", which should be defined as either
17 * "C" (default) or "Assembly".
18 */
19
20
21#ifndef LANGUAGE
22# ifdef __ASSEMBLY__
23# define LANGUAGE Assembly
24# else
25# define LANGUAGE C
26# endif
27#endif
28
29#ifndef io_p2v
30#define io_p2v(PhAdd) (PhAdd)
31#endif
32
33#include <asm/arch-sa1100/bitfield.h>
34
35#define C 0
36#define Assembly 1
37
38
39#if LANGUAGE == C
40typedef unsigned short Word16 ;
41typedef unsigned int Word32 ;
42typedef Word32 Word ;
43typedef Word Quad [4] ;
44typedef void *Address ;
45typedef void (*ExcpHndlr) (void) ;
46#endif /* LANGUAGE == C */
47
48
49/*
50 * Memory
51 */
52
53#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */
54
55#define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */
56#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */
57 /* [byte] */
58#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */
59 /* [byte] */
60#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */
61 /* [byte] */
62#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */
63 /* [byte] */
64
65#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */
66#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */
67#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */
68#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */
69#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */
70
71#define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */
72
73#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \
74 (0x00000000 + (Nb)*StMemBnkSp)
75#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */
76#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */
77#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */
78#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */
79
80#if LANGUAGE == C
81typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
82#define StMemBnk /* Static Memory Bank [0..3] */ \
83 ((StMemBnkType *) io_p2v (_StMemBnk (0)))
84#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */
85#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */
86#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */
87#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */
88#endif /* LANGUAGE == C */
89
90#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \
91 (0xC0000000 + (Nb)*DRAMBnkSp)
92#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */
93#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */
94#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */
95#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */
96
97#if LANGUAGE == C
98typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
99#define DRAMBnk /* DRAM Bank [0..3] */ \
100 ((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
101#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */
102#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */
103#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */
104#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */
105#endif /* LANGUAGE == C */
106
107#define _ZeroMem 0xE0000000 /* Zero Memory bank */
108
109#if LANGUAGE == C
110typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
111#define ZeroMem /* Zero Memory bank */ \
112 (*((ZeroMemType *) io_p2v (_ZeroMem)))
113#endif /* LANGUAGE == C */
114
115
116/*
117 * Personal Computer Memory Card International Association (PCMCIA) sockets
118 */
119
120#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
121#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
122#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
123#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
124#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
125
126#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
127#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
128#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
129#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
130
131#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
132#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
133#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
134#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
135
136#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
137 (0x20000000 + (Nb)*PCMCIASp)
138#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
139#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
140 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
141#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
142 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
143
144#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
145#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
146#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
147#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
148
149#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
150#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
151#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
152#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
153
154#if LANGUAGE == C
155
156typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
157typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
158
159#define PCMCIA0 /* PCMCIA 0 */ \
160 (*((PCMCIAType *) io_p2v (_PCMCIA0)))
161#define PCMCIA0IO /* PCMCIA 0 I/O */ \
162 (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
163#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \
164 (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
165#define PCMCIA0Mem /* PCMCIA 0 Memory */ \
166 (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
167
168#define PCMCIA1 /* PCMCIA 1 */ \
169 (*((PCMCIAType *) io_p2v (_PCMCIA1)))
170#define PCMCIA1IO /* PCMCIA 1 I/O */ \
171 (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
172#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \
173 (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
174#define PCMCIA1Mem /* PCMCIA 1 Memory */ \
175 (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
176
177#endif /* LANGUAGE == C */
178
179
180/*
181 * Universal Serial Bus (USB) Device Controller (UDC) control registers
182 *
183 * Registers
184 * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
185 * Controller (UDC) Control Register (read/write).
186 * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
187 * Controller (UDC) Address Register (read/write).
188 * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
189 * Controller (UDC) Output Maximum Packet size register
190 * (read/write).
191 * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
192 * Controller (UDC) Input Maximum Packet size register
193 * (read/write).
194 * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
195 * Controller (UDC) Control/Status register end-point 0
196 * (read/write).
197 * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
198 * Controller (UDC) Control/Status register end-point 1
199 * (output, read/write).
200 * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
201 * Controller (UDC) Control/Status register end-point 2
202 * (input, read/write).
203 * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
204 * Controller (UDC) Data register end-point 0
205 * (read/write).
206 * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
207 * Controller (UDC) Write Count register end-point 0
208 * (read).
209 * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
210 * Controller (UDC) Data Register (read/write).
211 * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
212 * Controller (UDC) Status Register (read/write).
213 */
214
215#define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */
216#define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */
217#define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */
218 /* Packet size reg. */
219#define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */
220 /* Packet size reg. */
221#define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */
222 /* reg. end-point 0 */
223#define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */
224 /* reg. end-point 1 (output) */
225#define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */
226 /* reg. end-point 2 (input) */
227#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */
228 /* end-point 0 */
229#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */
230 /* reg. end-point 0 */
231#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */
232#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */
233
234#if LANGUAGE == C
235#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \
236 (*((volatile Word *) io_p2v (_Ser0UDCCR)))
237#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \
238 (*((volatile Word *) io_p2v (_Ser0UDCAR)))
239#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \
240 /* Packet size reg. */ \
241 (*((volatile Word *) io_p2v (_Ser0UDCOMP)))
242#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \
243 /* Packet size reg. */ \
244 (*((volatile Word *) io_p2v (_Ser0UDCIMP)))
245#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \
246 /* reg. end-point 0 */ \
247 (*((volatile Word *) io_p2v (_Ser0UDCCS0)))
248#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \
249 /* reg. end-point 1 (output) */ \
250 (*((volatile Word *) io_p2v (_Ser0UDCCS1)))
251#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \
252 /* reg. end-point 2 (input) */ \
253 (*((volatile Word *) io_p2v (_Ser0UDCCS2)))
254#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \
255 /* end-point 0 */ \
256 (*((volatile Word *) io_p2v (_Ser0UDCD0)))
257#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \
258 /* reg. end-point 0 */ \
259 (*((volatile Word *) io_p2v (_Ser0UDCWC)))
260#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \
261 (*((volatile Word *) io_p2v (_Ser0UDCDR)))
262#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \
263 (*((volatile Word *) io_p2v (_Ser0UDCSR)))
264#endif /* LANGUAGE == C */
265
266#define UDCCR_UDD 0x00000001 /* UDC Disable */
267#define UDCCR_UDA 0x00000002 /* UDC Active (read) */
268#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
269#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
270 /* (disable) */
271#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
272 /* (disable) */
273#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
274 /* (disable) */
275#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
276 /* (disable) */
277#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */
278#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
279
280#define UDCAR_ADD Fld (7, 0) /* function ADDress */
281
282#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
283 /* [byte] */
284#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
285 /* [1..256 byte] */ \
286 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
287
288#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
289 /* [byte] */
290#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
291 /* [1..256 byte] */ \
292 (((Size) - 1) << FShft (UDCIMP_INMAXP))
293
294#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
295#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
296#define UDCCS0_SST 0x00000004 /* Sent STall */
297#define UDCCS0_FST 0x00000008 /* Force STall */
298#define UDCCS0_DE 0x00000010 /* Data End */
299#define UDCCS0_SE 0x00000020 /* Setup End (read) */
300#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
301 /* (write) */
302#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
303
304#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
305 /* Service request (read) */
306#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
307#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
308#define UDCCS1_SST 0x00000008 /* Sent STall */
309#define UDCCS1_FST 0x00000010 /* Force STall */
310#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
311
312#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
313 /* Service request (read) */
314#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
315#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
316#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
317#define UDCCS2_SST 0x00000010 /* Sent STall */
318#define UDCCS2_FST 0x00000020 /* Force STall */
319
320#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
321
322#define UDCWC_WC Fld (4, 0) /* Write Count */
323
324#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
325
326#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
327#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
328#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
329#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
330#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
331#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
332
333
334/*
335 * Universal Asynchronous Receiver/Transmitter (UART) control registers
336 *
337 * Registers
338 * Ser1UTCR0 Serial port 1 Universal Asynchronous
339 * Receiver/Transmitter (UART) Control Register 0
340 * (read/write).
341 * Ser1UTCR1 Serial port 1 Universal Asynchronous
342 * Receiver/Transmitter (UART) Control Register 1
343 * (read/write).
344 * Ser1UTCR2 Serial port 1 Universal Asynchronous
345 * Receiver/Transmitter (UART) Control Register 2
346 * (read/write).
347 * Ser1UTCR3 Serial port 1 Universal Asynchronous
348 * Receiver/Transmitter (UART) Control Register 3
349 * (read/write).
350 * Ser1UTDR Serial port 1 Universal Asynchronous
351 * Receiver/Transmitter (UART) Data Register
352 * (read/write).
353 * Ser1UTSR0 Serial port 1 Universal Asynchronous
354 * Receiver/Transmitter (UART) Status Register 0
355 * (read/write).
356 * Ser1UTSR1 Serial port 1 Universal Asynchronous
357 * Receiver/Transmitter (UART) Status Register 1 (read).
358 *
359 * Ser2UTCR0 Serial port 2 Universal Asynchronous
360 * Receiver/Transmitter (UART) Control Register 0
361 * (read/write).
362 * Ser2UTCR1 Serial port 2 Universal Asynchronous
363 * Receiver/Transmitter (UART) Control Register 1
364 * (read/write).
365 * Ser2UTCR2 Serial port 2 Universal Asynchronous
366 * Receiver/Transmitter (UART) Control Register 2
367 * (read/write).
368 * Ser2UTCR3 Serial port 2 Universal Asynchronous
369 * Receiver/Transmitter (UART) Control Register 3
370 * (read/write).
371 * Ser2UTCR4 Serial port 2 Universal Asynchronous
372 * Receiver/Transmitter (UART) Control Register 4
373 * (read/write).
374 * Ser2UTDR Serial port 2 Universal Asynchronous
375 * Receiver/Transmitter (UART) Data Register
376 * (read/write).
377 * Ser2UTSR0 Serial port 2 Universal Asynchronous
378 * Receiver/Transmitter (UART) Status Register 0
379 * (read/write).
380 * Ser2UTSR1 Serial port 2 Universal Asynchronous
381 * Receiver/Transmitter (UART) Status Register 1 (read).
382 *
383 * Ser3UTCR0 Serial port 3 Universal Asynchronous
384 * Receiver/Transmitter (UART) Control Register 0
385 * (read/write).
386 * Ser3UTCR1 Serial port 3 Universal Asynchronous
387 * Receiver/Transmitter (UART) Control Register 1
388 * (read/write).
389 * Ser3UTCR2 Serial port 3 Universal Asynchronous
390 * Receiver/Transmitter (UART) Control Register 2
391 * (read/write).
392 * Ser3UTCR3 Serial port 3 Universal Asynchronous
393 * Receiver/Transmitter (UART) Control Register 3
394 * (read/write).
395 * Ser3UTDR Serial port 3 Universal Asynchronous
396 * Receiver/Transmitter (UART) Data Register
397 * (read/write).
398 * Ser3UTSR0 Serial port 3 Universal Asynchronous
399 * Receiver/Transmitter (UART) Status Register 0
400 * (read/write).
401 * Ser3UTSR1 Serial port 3 Universal Asynchronous
402 * Receiver/Transmitter (UART) Status Register 1 (read).
403 *
404 * Clocks
405 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
406 * or 3.5795 MHz).
407 * fua, Tua Frequency, period of the UART communication.
408 */
409
410#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \
411 (0x80010000 + ((Nb) - 1)*0x00020000)
412#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \
413 (0x80010004 + ((Nb) - 1)*0x00020000)
414#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \
415 (0x80010008 + ((Nb) - 1)*0x00020000)
416#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \
417 (0x8001000C + ((Nb) - 1)*0x00020000)
418#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \
419 (0x80010010 + ((Nb) - 1)*0x00020000)
420#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \
421 (0x80010014 + ((Nb) - 1)*0x00020000)
422#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \
423 (0x8001001C + ((Nb) - 1)*0x00020000)
424#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \
425 (0x80010020 + ((Nb) - 1)*0x00020000)
426
427#define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
428#define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
429#define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
430#define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
431#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
432#define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
433#define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
434
435#define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
436#define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
437#define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
438#define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
439#define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
440#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
441#define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
442#define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
443
444#define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
445#define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
446#define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
447#define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
448#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
449#define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
450#define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
451
452#if LANGUAGE == C
453
454#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \
455 (*((volatile Word *) io_p2v (_Ser1UTCR0)))
456#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \
457 (*((volatile Word *) io_p2v (_Ser1UTCR1)))
458#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \
459 (*((volatile Word *) io_p2v (_Ser1UTCR2)))
460#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \
461 (*((volatile Word *) io_p2v (_Ser1UTCR3)))
462#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \
463 (*((volatile Word *) io_p2v (_Ser1UTDR)))
464#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \
465 (*((volatile Word *) io_p2v (_Ser1UTSR0)))
466#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \
467 (*((volatile Word *) io_p2v (_Ser1UTSR1)))
468
469#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \
470 (*((volatile Word *) io_p2v (_Ser2UTCR0)))
471#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \
472 (*((volatile Word *) io_p2v (_Ser2UTCR1)))
473#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \
474 (*((volatile Word *) io_p2v (_Ser2UTCR2)))
475#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \
476 (*((volatile Word *) io_p2v (_Ser2UTCR3)))
477#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \
478 (*((volatile Word *) io_p2v (_Ser2UTCR4)))
479#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \
480 (*((volatile Word *) io_p2v (_Ser2UTDR)))
481#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \
482 (*((volatile Word *) io_p2v (_Ser2UTSR0)))
483#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \
484 (*((volatile Word *) io_p2v (_Ser2UTSR1)))
485
486#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \
487 (*((volatile Word *) io_p2v (_Ser3UTCR0)))
488#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \
489 (*((volatile Word *) io_p2v (_Ser3UTCR1)))
490#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \
491 (*((volatile Word *) io_p2v (_Ser3UTCR2)))
492#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \
493 (*((volatile Word *) io_p2v (_Ser3UTCR3)))
494#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \
495 (*((volatile Word *) io_p2v (_Ser3UTDR)))
496#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \
497 (*((volatile Word *) io_p2v (_Ser3UTSR0)))
498#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \
499 (*((volatile Word *) io_p2v (_Ser3UTSR1)))
500
501#elif LANGUAGE == Assembly
502#define Ser1UTCR0 ( io_p2v (_Ser1UTCR0))
503#define Ser1UTCR1 ( io_p2v (_Ser1UTCR1))
504#define Ser1UTCR2 ( io_p2v (_Ser1UTCR2))
505#define Ser1UTCR3 ( io_p2v (_Ser1UTCR3))
506#define Ser1UTDR ( io_p2v (_Ser1UTDR))
507#define Ser1UTSR0 ( io_p2v (_Ser1UTSR0))
508#define Ser1UTSR1 ( io_p2v (_Ser1UTSR1))
509
510#define Ser2UTCR0 ( io_p2v (_Ser2UTCR0))
511#define Ser2UTCR1 ( io_p2v (_Ser2UTCR1))
512#define Ser2UTCR2 ( io_p2v (_Ser2UTCR2))
513#define Ser2UTCR3 ( io_p2v (_Ser2UTCR3))
514#define Ser2UTCR4 ( io_p2v (_Ser2UTCR4))
515#define Ser2UTDR ( io_p2v (_Ser2UTDR))
516#define Ser2UTSR0 ( io_p2v (_Ser2UTSR0))
517#define Ser2UTSR1 ( io_p2v (_Ser2UTSR1))
518
519#define Ser3UTCR0 ( io_p2v (_Ser3UTCR0))
520#define Ser3UTCR1 ( io_p2v (_Ser3UTCR1))
521#define Ser3UTCR2 ( io_p2v (_Ser3UTCR2))
522#define Ser3UTCR3 ( io_p2v (_Ser3UTCR3))
523#define Ser3UTDR ( io_p2v (_Ser3UTDR))
524#define Ser3UTSR0 ( io_p2v (_Ser3UTSR0))
525#define Ser3UTSR1 ( io_p2v (_Ser3UTSR1))
526
527#endif /* LANGUAGE == C */
528
529#define UTCR0_PE 0x00000001 /* Parity Enable */
530#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
531#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
532#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
533#define UTCR0_SBS 0x00000004 /* Stop Bit Select */
534#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
535#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
536#define UTCR0_DSS 0x00000008 /* Data Size Select */
537#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
538#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
539#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
540 /* (ser. port 1: GPIO [18], */
541 /* ser. port 3: GPIO [20]) */
542#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
543#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
544#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
545#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
546#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
547#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
548#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
549 (UTCR0_1StpBit + UTCR0_8BitData)
550
551#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
552#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
553 /* fua = fxtl/(16*(BRD[11:0] + 1)) */
554 /* Tua = 16*(BRD [11:0] + 1)*Txtl */
555#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
556 (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
557 FShft (UTCR1_BRD))
558#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
559 (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
560 FShft (UTCR2_BRD))
561 /* fua = fxtl/(16*Floor (Div/16)) */
562 /* Tua = 16*Floor (Div/16)*Txtl */
563#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
564 (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
565 FShft (UTCR1_BRD))
566#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
567 (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
568 FShft (UTCR2_BRD))
569 /* fua = fxtl/(16*Ceil (Div/16)) */
570 /* Tua = 16*Ceil (Div/16)*Txtl */
571
572#define UTCR3_RXE 0x00000001 /* Receive Enable */
573#define UTCR3_TXE 0x00000002 /* Transmit Enable */
574#define UTCR3_BRK 0x00000004 /* BReaK mode */
575#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
576 /* more Interrupt Enable */
577#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
578 /* Interrupt Enable */
579#define UTCR3_LBM 0x00000020 /* Look-Back Mode */
580#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
581 /* TIE, LBM can be set or cleared) */ \
582 (UTCR3_RXE + UTCR3_TXE)
583
584#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
585 /* (HP-SIR) modulation Enable */
586#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
587#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
588#define UTCR4_LPM 0x00000002 /* Low-Power Mode */
589#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
590#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
591
592#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
593#if 0 /* Hidden receive FIFO bits */
594#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
595#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
596#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
597#endif /* 0 */
598
599#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
600 /* Service request (read) */
601#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
602 /* more Service request (read) */
603#define UTSR0_RID 0x00000004 /* Receiver IDle */
604#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
605#define UTSR0_REB 0x00000010 /* Receive End of Break */
606#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
607
608#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
609#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
610#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
611#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
612#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
613#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
614
615
616/*
617 * Synchronous Data Link Controller (SDLC) control registers
618 *
619 * Registers
620 * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
621 * Control Register 0 (read/write).
622 * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
623 * Control Register 1 (read/write).
624 * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
625 * Control Register 2 (read/write).
626 * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
627 * Control Register 3 (read/write).
628 * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
629 * Control Register 4 (read/write).
630 * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
631 * Data Register (read/write).
632 * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
633 * Status Register 0 (read/write).
634 * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
635 * Status Register 1 (read/write).
636 *
637 * Clocks
638 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
639 * or 3.5795 MHz).
640 * fsd, Tsd Frequency, period of the SDLC communication.
641 */
642
643#define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */
644#define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */
645#define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */
646#define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */
647#define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */
648#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */
649#define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */
650#define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */
651
652#if LANGUAGE == C
653#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \
654 (*((volatile Word *) io_p2v (_Ser1SDCR0)))
655#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \
656 (*((volatile Word *) io_p2v (_Ser1SDCR1)))
657#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \
658 (*((volatile Word *) io_p2v (_Ser1SDCR2)))
659#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \
660 (*((volatile Word *) io_p2v (_Ser1SDCR3)))
661#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \
662 (*((volatile Word *) io_p2v (_Ser1SDCR4)))
663#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \
664 (*((volatile Word *) io_p2v (_Ser1SDDR)))
665#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \
666 (*((volatile Word *) io_p2v (_Ser1SDSR0)))
667#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \
668 (*((volatile Word *) io_p2v (_Ser1SDSR1)))
669#endif /* LANGUAGE == C */
670
671#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
672#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
673#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
674#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
675#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
676#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
677#define SDCR0_LBM 0x00000004 /* Look-Back Mode */
678#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
679#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
680#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
681#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
682#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
683 /* (GPIO [16]) */
684#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
685#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
686#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
687#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
688#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
689#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
690#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
691#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
692
693#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
694 /* (GPIO [17]) */
695#define SDCR1_TXE 0x00000002 /* Transmit Enable */
696#define SDCR1_RXE 0x00000004 /* Receive Enable */
697#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
698 /* more Interrupt Enable */
699#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
700 /* Interrupt Enable */
701#define SDCR1_AME 0x00000020 /* Address Match Enable */
702#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
703#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
704#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
705#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
706
707#define SDCR2_AMV Fld (8, 0) /* Address Match Value */
708
709#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
710#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
711 /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
712 /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
713#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
714 (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
715 FShft (SDCR3_BRD))
716#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
717 (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
718 FShft (SDCR4_BRD))
719 /* fsd = fxtl/(16*Floor (Div/16)) */
720 /* Tsd = 16*Floor (Div/16)*Txtl */
721#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
722 (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
723 FShft (SDCR3_BRD))
724#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
725 (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
726 FShft (SDCR4_BRD))
727 /* fsd = fxtl/(16*Ceil (Div/16)) */
728 /* Tsd = 16*Ceil (Div/16)*Txtl */
729
730#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
731#if 0 /* Hidden receive FIFO bits */
732#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
733#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
734#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
735#endif /* 0 */
736
737#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
738#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
739#define SDSR0_RAB 0x00000004 /* Receive ABort */
740#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
741 /* Service request (read) */
742#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
743 /* more Service request (read) */
744
745#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
746#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
747#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
748#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
749#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
750#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
751#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
752#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
753
754
755/*
756 * High-Speed Serial to Parallel controller (HSSP) control registers
757 *
758 * Registers
759 * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
760 * controller (HSSP) Control Register 0 (read/write).
761 * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
762 * controller (HSSP) Control Register 1 (read/write).
763 * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
764 * controller (HSSP) Data Register (read/write).
765 * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
766 * controller (HSSP) Status Register 0 (read/write).
767 * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
768 * controller (HSSP) Status Register 1 (read).
769 * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
770 * controller (HSSP) Control Register 2 (read/write).
771 * [The HSCR2 register is only implemented in
772 * versions 2.0 (rev. = 8) and higher of the StrongARM
773 * SA-1100.]
774 */
775
776#define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */
777#define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */
778#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */
779#define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */
780#define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */
781#define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */
782
783#if LANGUAGE == C
784#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \
785 (*((volatile Word *) io_p2v (_Ser2HSCR0)))
786#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \
787 (*((volatile Word *) io_p2v (_Ser2HSCR1)))
788#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \
789 (*((volatile Word *) io_p2v (_Ser2HSDR)))
790#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \
791 (*((volatile Word *) io_p2v (_Ser2HSSR0)))
792#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \
793 (*((volatile Word *) io_p2v (_Ser2HSSR1)))
794#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \
795 (*((volatile Word *) io_p2v (_Ser2HSCR2)))
796#endif /* LANGUAGE == C */
797
798#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
799#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
800#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
801#define HSCR0_LBM 0x00000002 /* Look-Back Mode */
802#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
803#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
804#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
805#define HSCR0_TXE 0x00000008 /* Transmit Enable */
806#define HSCR0_RXE 0x00000010 /* Receive Enable */
807#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
808 /* more Interrupt Enable */
809#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
810 /* Interrupt Enable */
811#define HSCR0_AME 0x00000080 /* Address Match Enable */
812
813#define HSCR1_AMV Fld (8, 0) /* Address Match Value */
814
815#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
816#if 0 /* Hidden receive FIFO bits */
817#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
818#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
819#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
820#endif /* 0 */
821
822#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
823#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
824#define HSSR0_RAB 0x00000004 /* Receive ABort */
825#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
826 /* Service request (read) */
827#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
828 /* more Service request (read) */
829#define HSSR0_FRE 0x00000020 /* receive FRaming Error */
830
831#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
832#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
833#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
834#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
835#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
836#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
837#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
838
839#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
840#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
841 /* (inverted) */
842#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
843 /* (non-inverted) */
844#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
845#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
846 /* (inverted) */
847#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
848 /* (non-inverted) */
849
850
851/*
852 * Multi-media Communications Port (MCP) control registers
853 *
854 * Registers
855 * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
856 * Control Register 0 (read/write).
857 * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
858 * Data Register 0 (audio, read/write).
859 * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
860 * Data Register 1 (telecom, read/write).
861 * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
862 * Data Register 2 (CODEC registers, read/write).
863 * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
864 * Status Register (read/write).
865 * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
866 * Control Register 1 (read/write).
867 * [The MCCR1 register is only implemented in
868 * versions 2.0 (rev. = 8) and higher of the StrongARM
869 * SA-1100.]
870 *
871 * Clocks
872 * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
873 * 12 MHz, or GPIO [21]).
874 * faud, Taud Frequency, period of the audio sampling.
875 * ftcm, Ttcm Frequency, period of the telecom sampling.
876 */
877
878#define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */
879#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */
880 /* (audio) */
881#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */
882 /* (telecom) */
883#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */
884 /* (CODEC reg.) */
885#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */
886#define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */
887
888#if LANGUAGE == C
889#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \
890 (*((volatile Word *) io_p2v (_Ser4MCCR0)))
891#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \
892 /* (audio) */ \
893 (*((volatile Word *) io_p2v (_Ser4MCDR0)))
894#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \
895 /* (telecom) */ \
896 (*((volatile Word *) io_p2v (_Ser4MCDR1)))
897#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \
898 /* (CODEC reg.) */ \
899 (*((volatile Word *) io_p2v (_Ser4MCDR2)))
900#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \
901 (*((volatile Word *) io_p2v (_Ser4MCSR)))
902#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \
903 (*((volatile Word *) io_p2v (_Ser4MCCR1)))
904#endif /* LANGUAGE == C */
905
906#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
907 /* [6..127] */
908 /* faud = fmc/(32*ASD) */
909 /* Taud = 32*ASD*Tmc */
910#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
911 /* [192..4064] */ \
912 ((Div)/32 << FShft (MCCR0_ASD))
913 /* faud = fmc/(32*Floor (Div/32)) */
914 /* Taud = 32*Floor (Div/32)*Tmc */
915#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
916 (((Div) + 31)/32 << FShft (MCCR0_ASD))
917 /* faud = fmc/(32*Ceil (Div/32)) */
918 /* Taud = 32*Ceil (Div/32)*Tmc */
919#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
920 /* Divisor/32 [16..127] */
921 /* ftcm = fmc/(32*TSD) */
922 /* Ttcm = 32*TSD*Tmc */
923#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
924 /* [512..4064] */ \
925 ((Div)/32 << FShft (MCCR0_TSD))
926 /* ftcm = fmc/(32*Floor (Div/32)) */
927 /* Ttcm = 32*Floor (Div/32)*Tmc */
928#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
929 (((Div) + 31)/32 << FShft (MCCR0_TSD))
930 /* ftcm = fmc/(32*Ceil (Div/32)) */
931 /* Ttcm = 32*Ceil (Div/32)*Tmc */
932#define MCCR0_MCE 0x00010000 /* MCP Enable */
933#define MCCR0_ECS 0x00020000 /* External Clock Select */
934#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
935#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
936#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
937 /* sampling/storing Mode */
938#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
939#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
940#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
941 /* or less interrupt Enable */
942#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
943 /* or more interrupt Enable */
944#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
945 /* or less interrupt Enable */
946#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
947 /* more interrupt Enable */
948#define MCCR0_LBM 0x00800000 /* Look-Back Mode */
949#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
950#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
951 (((Div) - 1) << FShft (MCCR0_ECP))
952
953#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
954 /* FIFOs */
955
956#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
957 /* FIFOs */
958
959 /* receive/transmit CODEC reg. */
960 /* FIFOs: */
961#define MCDR2_DATA Fld (16, 0) /* reg. DATA */
962#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
963#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
964#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
965#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
966
967#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
968 /* or less Service request (read) */
969#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
970 /* more Service request (read) */
971#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
972 /* or less Service request (read) */
973#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
974 /* or more Service request (read) */
975#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
976#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
977#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
978#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
979#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
980 /* (read) */
981#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
982 /* (read) */
983#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
984 /* (read) */
985#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
986 /* (read) */
987#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
988 /* (read) */
989#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
990 /* (read) */
991#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
992#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
993
994#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
995#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
996 /* (11.981 MHz) */
997#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
998 /* (9.585 MHz) */
999
1000
1001/*
1002 * Synchronous Serial Port (SSP) control registers
1003 *
1004 * Registers
1005 * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
1006 * Register 0 (read/write).
1007 * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
1008 * Register 1 (read/write).
1009 * [Bits SPO and SP are only implemented in versions 2.0
1010 * (rev. = 8) and higher of the StrongARM SA-1100.]
1011 * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
1012 * Register (read/write).
1013 * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
1014 * Register (read/write).
1015 *
1016 * Clocks
1017 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
1018 * or 3.5795 MHz).
1019 * fss, Tss Frequency, period of the SSP communication.
1020 */
1021
1022#define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */
1023#define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */
1024#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */
1025#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */
1026
1027#if LANGUAGE == C
1028#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \
1029 (*((volatile Word *) io_p2v (_Ser4SSCR0)))
1030#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \
1031 (*((volatile Word *) io_p2v (_Ser4SSCR1)))
1032#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \
1033 (*((volatile Word *) io_p2v (_Ser4SSDR)))
1034#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \
1035 (*((volatile Word *) io_p2v (_Ser4SSSR)))
1036#endif /* LANGUAGE == C */
1037
1038#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
1039#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
1040 (((Size) - 1) << FShft (SSCR0_DSS))
1041#define SSCR0_FRF Fld (2, 4) /* FRame Format */
1042#define SSCR0_Motorola /* Motorola Serial Peripheral */ \
1043 /* Interface (SPI) format */ \
1044 (0 << FShft (SSCR0_FRF))
1045#define SSCR0_TI /* Texas Instruments Synchronous */ \
1046 /* Serial format */ \
1047 (1 << FShft (SSCR0_FRF))
1048#define SSCR0_National /* National Microwire format */ \
1049 (2 << FShft (SSCR0_FRF))
1050#define SSCR0_SSE 0x00000080 /* SSP Enable */
1051#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
1052 /* fss = fxtl/(2*(SCR + 1)) */
1053 /* Tss = 2*(SCR + 1)*Txtl */
1054#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
1055 (((Div) - 2)/2 << FShft (SSCR0_SCR))
1056 /* fss = fxtl/(2*Floor (Div/2)) */
1057 /* Tss = 2*Floor (Div/2)*Txtl */
1058#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
1059 (((Div) - 1)/2 << FShft (SSCR0_SCR))
1060 /* fss = fxtl/(2*Ceil (Div/2)) */
1061 /* Tss = 2*Ceil (Div/2)*Txtl */
1062
1063#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
1064 /* Interrupt Enable */
1065#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
1066 /* Interrupt Enable */
1067#define SSCR1_LBM 0x00000004 /* Look-Back Mode */
1068#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
1069#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
1070#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
1071#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
1072#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
1073 /* after frame (SFRM, 1st edge) */
1074#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
1075 /* after frame (SFRM, 1st edge) */
1076#define SSCR1_ECS 0x00000020 /* External Clock Select */
1077#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
1078#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
1079
1080#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
1081
1082#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
1083#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
1084#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
1085#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
1086 /* Service request (read) */
1087#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
1088 /* Service request (read) */
1089#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
1090
1091
1092/*
1093 * Operating System (OS) timer control registers
1094 *
1095 * Registers
1096 * OSMR0 Operating System (OS) timer Match Register 0
1097 * (read/write).
1098 * OSMR1 Operating System (OS) timer Match Register 1
1099 * (read/write).
1100 * OSMR2 Operating System (OS) timer Match Register 2
1101 * (read/write).
1102 * OSMR3 Operating System (OS) timer Match Register 3
1103 * (read/write).
1104 * OSCR Operating System (OS) timer Counter Register
1105 * (read/write).
1106 * OSSR Operating System (OS) timer Status Register
1107 * (read/write).
1108 * OWER Operating System (OS) timer Watch-dog Enable Register
1109 * (read/write).
1110 * OIER Operating System (OS) timer Interrupt Enable Register
1111 * (read/write).
1112 */
1113
1114#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \
1115 (0x90000000 + (Nb)*4)
1116#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */
1117#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */
1118#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */
1119#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */
1120#define _OSCR 0x90000010 /* OS timer Counter Reg. */
1121#define _OSSR 0x90000014 /* OS timer Status Reg. */
1122#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */
1123#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */
1124
1125#if LANGUAGE == C
1126#define OSMR /* OS timer Match Reg. [0..3] */ \
1127 ((volatile Word *) io_p2v (_OSMR (0)))
1128#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */
1129#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */
1130#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */
1131#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */
1132#define OSCR /* OS timer Counter Reg. */ \
1133 (*((volatile Word *) io_p2v (_OSCR)))
1134#define OSSR /* OS timer Status Reg. */ \
1135 (*((volatile Word *) io_p2v (_OSSR)))
1136#define OWER /* OS timer Watch-dog Enable Reg. */ \
1137 (*((volatile Word *) io_p2v (_OWER)))
1138#define OIER /* OS timer Interrupt Enable Reg. */ \
1139 (*((volatile Word *) io_p2v (_OIER)))
1140#endif /* LANGUAGE == C */
1141
1142#define OSSR_M(Nb) /* Match detected [0..3] */ \
1143 (0x00000001 << (Nb))
1144#define OSSR_M0 OSSR_M (0) /* Match detected 0 */
1145#define OSSR_M1 OSSR_M (1) /* Match detected 1 */
1146#define OSSR_M2 OSSR_M (2) /* Match detected 2 */
1147#define OSSR_M3 OSSR_M (3) /* Match detected 3 */
1148
1149#define OWER_WME 0x00000001 /* Watch-dog Match Enable */
1150 /* (set only) */
1151
1152#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
1153 (0x00000001 << (Nb))
1154#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
1155#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
1156#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
1157#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
1158
1159
1160/*
1161 * Real-Time Clock (RTC) control registers
1162 *
1163 * Registers
1164 * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
1165 * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
1166 * RTTR Real-Time Clock (RTC) Trim Register (read/write).
1167 * RTSR Real-Time Clock (RTC) Status Register (read/write).
1168 *
1169 * Clocks
1170 * frtx, Trtx Frequency, period of the real-time clock crystal
1171 * (32.768 kHz nominal).
1172 * frtc, Trtc Frequency, period of the real-time clock counter
1173 * (1 Hz nominal).
1174 */
1175
1176#define _RTAR 0x90010000 /* RTC Alarm Reg. */
1177#define _RCNR 0x90010004 /* RTC CouNt Reg. */
1178#define _RTTR 0x90010008 /* RTC Trim Reg. */
1179#define _RTSR 0x90010010 /* RTC Status Reg. */
1180
1181#if LANGUAGE == C
1182#define RTAR /* RTC Alarm Reg. */ \
1183 (*((volatile Word *) io_p2v (_RTAR)))
1184#define RCNR /* RTC CouNt Reg. */ \
1185 (*((volatile Word *) io_p2v (_RCNR)))
1186#define RTTR /* RTC Trim Reg. */ \
1187 (*((volatile Word *) io_p2v (_RTTR)))
1188#define RTSR /* RTC Status Reg. */ \
1189 (*((volatile Word *) io_p2v (_RTSR)))
1190#endif /* LANGUAGE == C */
1191
1192#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
1193#define RTTR_D Fld (10, 16) /* trim Delete count */
1194 /* frtc = (1023*(C + 1) - D)*frtx/ */
1195 /* (1023*(C + 1)^2) */
1196 /* Trtc = (1023*(C + 1)^2)*Trtx/ */
1197 /* (1023*(C + 1) - D) */
1198
1199#define RTSR_AL 0x00000001 /* ALarm detected */
1200#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */
1201#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */
1202#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */
1203
1204
1205/*
1206 * Power Manager (PM) control registers
1207 *
1208 * Registers
1209 * PMCR Power Manager (PM) Control Register (read/write).
1210 * PSSR Power Manager (PM) Sleep Status Register (read/write).
1211 * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
1212 * PWER Power Manager (PM) Wake-up Enable Register
1213 * (read/write).
1214 * PCFR Power Manager (PM) general ConFiguration Register
1215 * (read/write).
1216 * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
1217 * Configuration Register (read/write).
1218 * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
1219 * Sleep state Register (read/write, see GPIO pins).
1220 * POSR Power Manager (PM) Oscillator Status Register (read).
1221 *
1222 * Clocks
1223 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
1224 * or 3.5795 MHz).
1225 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1226 */
1227
1228#define _PMCR 0x90020000 /* PM Control Reg. */
1229#define _PSSR 0x90020004 /* PM Sleep Status Reg. */
1230#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */
1231#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */
1232#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */
1233#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */
1234#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */
1235#define _POSR 0x9002001C /* PM Oscillator Status Reg. */
1236
1237#if LANGUAGE == C
1238#define PMCR /* PM Control Reg. */ \
1239 (*((volatile Word *) io_p2v (_PMCR)))
1240#define PSSR /* PM Sleep Status Reg. */ \
1241 (*((volatile Word *) io_p2v (_PSSR)))
1242#define PSPR /* PM Scratch-Pad Reg. */ \
1243 (*((volatile Word *) io_p2v (_PSPR)))
1244#define PWER /* PM Wake-up Enable Reg. */ \
1245 (*((volatile Word *) io_p2v (_PWER)))
1246#define PCFR /* PM general ConFiguration Reg. */ \
1247 (*((volatile Word *) io_p2v (_PCFR)))
1248#define PPCR /* PM PLL Configuration Reg. */ \
1249 (*((volatile Word *) io_p2v (_PPCR)))
1250#define PGSR /* PM GPIO Sleep state Reg. */ \
1251 (*((volatile Word *) io_p2v (_PGSR)))
1252#define POSR /* PM Oscillator Status Reg. */ \
1253 (*((volatile Word *) io_p2v (_POSR)))
1254
1255#elif LANGUAGE == Assembly
1256#define PMCR (io_p2v (_PMCR))
1257#define PSSR (io_p2v (_PSSR))
1258#define PSPR (io_p2v (_PSPR))
1259#define PWER (io_p2v (_PWER))
1260#define PCFR (io_p2v (_PCFR))
1261#define PPCR (io_p2v (_PPCR))
1262#define PGSR (io_p2v (_PGSR))
1263#define POSR (io_p2v (_POSR))
1264
1265#endif /* LANGUAGE == C */
1266
1267#define PMCR_SF 0x00000001 /* Sleep Force (set only) */
1268
1269#define PSSR_SS 0x00000001 /* Software Sleep */
1270#define PSSR_BFS 0x00000002 /* Battery Fault Status */
1271 /* (BATT_FAULT) */
1272#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
1273#define PSSR_DH 0x00000008 /* DRAM control Hold */
1274#define PSSR_PH 0x00000010 /* Peripheral control Hold */
1275
1276#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
1277#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1278#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1279#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1280#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1281#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1282#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1283#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1284#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1285#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1286#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1287#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1288#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1289#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1290#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1291#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1292#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1293#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
1294#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
1295#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
1296#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
1297#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
1298#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
1299#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
1300#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
1301#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
1302#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
1303#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
1304#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
1305#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1306
1307#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
1308#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
1309#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
1310#define PCFR_FP 0x00000002 /* Float PCMCIA pins */
1311#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
1312#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
1313#define PCFR_FS 0x00000004 /* Float Static memory pins */
1314#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
1315#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
1316#define PCFR_FO 0x00000008 /* Force RTC oscillator */
1317 /* (32.768 kHz) enable On */
1318
1319#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
1320#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
1321 (0x00 << FShft (PPCR_CCF))
1322#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
1323 (0x01 << FShft (PPCR_CCF))
1324#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
1325 (0x02 << FShft (PPCR_CCF))
1326#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
1327 (0x03 << FShft (PPCR_CCF))
1328#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
1329 (0x04 << FShft (PPCR_CCF))
1330#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
1331 (0x05 << FShft (PPCR_CCF))
1332#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
1333 (0x06 << FShft (PPCR_CCF))
1334#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
1335 (0x07 << FShft (PPCR_CCF))
1336#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
1337 (0x08 << FShft (PPCR_CCF))
1338#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
1339 (0x09 << FShft (PPCR_CCF))
1340#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
1341 (0x0A << FShft (PPCR_CCF))
1342#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
1343 (0x0B << FShft (PPCR_CCF))
1344#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
1345 (0x0C << FShft (PPCR_CCF))
1346#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
1347 (0x0D << FShft (PPCR_CCF))
1348#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
1349 (0x0E << FShft (PPCR_CCF))
1350#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
1351 (0x0F << FShft (PPCR_CCF))
1352 /* 3.6864 MHz crystal (fxtl): */
1353#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
1354#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
1355#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
1356#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
1357#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
1358#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
1359#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
1360#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
1361#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
1362#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
1363#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
1364#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
1365#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
1366#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
1367#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
1368#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
1369 /* 3.5795 MHz crystal (fxtl): */
1370#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
1371#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
1372#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
1373#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
1374#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
1375#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
1376#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
1377#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
1378#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
1379#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
1380#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
1381#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
1382#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
1383#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
1384#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
1385#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
1386
1387#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
1388
1389
1390/*
1391 * Reset Controller (RC) control registers
1392 *
1393 * Registers
1394 * RSRR Reset Controller (RC) Software Reset Register
1395 * (read/write).
1396 * RCSR Reset Controller (RC) Status Register (read/write).
1397 */
1398
1399#define _RSRR 0x90030000 /* RC Software Reset Reg. */
1400#define _RCSR 0x90030004 /* RC Status Reg. */
1401
1402#if LANGUAGE == C
1403#define RSRR /* RC Software Reset Reg. */ \
1404 (*((volatile Word *) io_p2v (_RSRR)))
1405#define RCSR /* RC Status Reg. */ \
1406 (*((volatile Word *) io_p2v (_RCSR)))
1407#endif /* LANGUAGE == C */
1408
1409#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
1410
1411#define RCSR_HWR 0x00000001 /* HardWare Reset */
1412#define RCSR_SWR 0x00000002 /* SoftWare Reset */
1413#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
1414#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
1415
1416
1417/*
1418 * Test unit control registers
1419 *
1420 * Registers
1421 * TUCR Test Unit Control Register (read/write).
1422 */
1423
1424#define _TUCR 0x90030008 /* Test Unit Control Reg. */
1425
1426#if LANGUAGE == C
1427#define TUCR /* Test Unit Control Reg. */ \
1428 (*((volatile Word *) io_p2v (_TUCR)))
1429#endif /* LANGUAGE == C */
1430
1431#define TUCR_TIC 0x00000040 /* TIC mode */
1432#define TUCR_TTST 0x00000080 /* Trim TeST mode */
1433#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
1434 /* Check */
1435#define TUCR_PMD 0x00000200 /* Power Management Disable */
1436#define TUCR_MR 0x00000400 /* Memory Request mode */
1437#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
1438#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
1439 /* grant (MBGNT) on GPIO [22:21] */
1440#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
1441#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
1442#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
1443#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
1444#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
1445#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
1446#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
1447 (0 << FShft (TUCR_TSEL))
1448#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
1449 (1 << FShft (TUCR_TSEL))
1450#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
1451 (2 << FShft (TUCR_TSEL))
1452#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
1453 (3 << FShft (TUCR_TSEL))
1454#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
1455 /* Clocks on GPIO [26:27] */ \
1456 (4 << FShft (TUCR_TSEL))
1457#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
1458 /* (Alternative) */ \
1459 (5 << FShft (TUCR_TSEL))
1460#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
1461 (6 << FShft (TUCR_TSEL))
1462#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
1463 (7 << FShft (TUCR_TSEL))
1464
1465
1466/*
1467 * General-Purpose Input/Output (GPIO) control registers
1468 *
1469 * Registers
1470 * GPLR General-Purpose Input/Output (GPIO) Pin Level
1471 * Register (read).
1472 * GPDR General-Purpose Input/Output (GPIO) Pin Direction
1473 * Register (read/write).
1474 * GPSR General-Purpose Input/Output (GPIO) Pin output Set
1475 * Register (write).
1476 * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
1477 * Register (write).
1478 * GRER General-Purpose Input/Output (GPIO) Rising-Edge
1479 * detect Register (read/write).
1480 * GFER General-Purpose Input/Output (GPIO) Falling-Edge
1481 * detect Register (read/write).
1482 * GEDR General-Purpose Input/Output (GPIO) Edge Detect
1483 * status Register (read/write).
1484 * GAFR General-Purpose Input/Output (GPIO) Alternate
1485 * Function Register (read/write).
1486 *
1487 * Clock
1488 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1489 */
1490
1491#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */
1492#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */
1493#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */
1494#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */
1495#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */
1496#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */
1497#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */
1498#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */
1499
1500#if LANGUAGE == C
1501#define GPLR /* GPIO Pin Level Reg. */ \
1502 (*((volatile Word *) io_p2v (_GPLR)))
1503#define GPDR /* GPIO Pin Direction Reg. */ \
1504 (*((volatile Word *) io_p2v (_GPDR)))
1505#define GPSR /* GPIO Pin output Set Reg. */ \
1506 (*((volatile Word *) io_p2v (_GPSR)))
1507#define GPCR /* GPIO Pin output Clear Reg. */ \
1508 (*((volatile Word *) io_p2v (_GPCR)))
1509#define GRER /* GPIO Rising-Edge detect Reg. */ \
1510 (*((volatile Word *) io_p2v (_GRER)))
1511#define GFER /* GPIO Falling-Edge detect Reg. */ \
1512 (*((volatile Word *) io_p2v (_GFER)))
1513#define GEDR /* GPIO Edge Detect status Reg. */ \
1514 (*((volatile Word *) io_p2v (_GEDR)))
1515#define GAFR /* GPIO Alternate Function Reg. */ \
1516 (*((volatile Word *) io_p2v (_GAFR)))
1517#elif LANGUAGE == Assembly
1518
1519#define GPLR (io_p2v (_GPLR))
1520#define GPDR (io_p2v (_GPDR))
1521#define GPSR (io_p2v (_GPSR))
1522#define GPCR (io_p2v (_GPCR))
1523#define GRER (io_p2v (_GRER))
1524#define GFER (io_p2v (_GFER))
1525#define GEDR (io_p2v (_GEDR))
1526#define GAFR (io_p2v (_GAFR))
1527
1528#endif /* LANGUAGE == C */
1529
1530#define GPIO_MIN (0)
1531#define GPIO_MAX (27)
1532
1533#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
1534 (0x00000001 << (Nb))
1535#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
1536#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
1537#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
1538#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
1539#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
1540#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
1541#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
1542#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
1543#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
1544#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
1545#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
1546#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
1547#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
1548#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
1549#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
1550#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
1551#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
1552#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
1553#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
1554#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
1555#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
1556#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
1557#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
1558#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
1559#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
1560#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
1561#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
1562#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
1563
1564#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
1565 GPIO_GPIO ((Nb) - 6)
1566#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
1567#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
1568#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
1569#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
1570#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
1571#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
1572#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
1573#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
1574 /* ser. port 4: */
1575#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
1576#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
1577#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
1578#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
1579 /* ser. port 1: */
1580#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
1581#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
1582#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
1583#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
1584#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
1585 /* ser. port 4: */
1586#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
1587 /* ser. port 3: */
1588#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
1589 /* ser. port 4: */
1590#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
1591 /* test controller: */
1592#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
1593#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
1594#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
1595#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
1596#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
1597#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
1598#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
1599#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
1600
1601#define GPDR_In 0 /* Input */
1602#define GPDR_Out 1 /* Output */
1603
1604
1605/*
1606 * Interrupt Controller (IC) control registers
1607 *
1608 * Registers
1609 * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
1610 * Pending register (read).
1611 * ICMR Interrupt Controller (IC) Mask Register (read/write).
1612 * ICLR Interrupt Controller (IC) Level Register (read/write).
1613 * ICCR Interrupt Controller (IC) Control Register
1614 * (read/write).
1615 * [The ICCR register is only implemented in versions 2.0
1616 * (rev. = 8) and higher of the StrongARM SA-1100.]
1617 * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
1618 * (FIQ) Pending register (read).
1619 * ICPR Interrupt Controller (IC) Pending Register (read).
1620 * [The ICPR register is active low (inverted) in
1621 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1622 * StrongARM SA-1100, it is active high (non-inverted) in
1623 * versions 2.0 (rev. = 8) and higher.]
1624 */
1625
1626#define _ICIP 0x90050000 /* IC IRQ Pending reg. */
1627#define _ICMR 0x90050004 /* IC Mask Reg. */
1628#define _ICLR 0x90050008 /* IC Level Reg. */
1629#define _ICCR 0x9005000C /* IC Control Reg. */
1630#define _ICFP 0x90050010 /* IC FIQ Pending reg. */
1631#define _ICPR 0x90050020 /* IC Pending Reg. */
1632
1633#if LANGUAGE == C
1634#define ICIP /* IC IRQ Pending reg. */ \
1635 (*((volatile Word *) io_p2v (_ICIP)))
1636#define ICMR /* IC Mask Reg. */ \
1637 (*((volatile Word *) io_p2v (_ICMR)))
1638#define ICLR /* IC Level Reg. */ \
1639 (*((volatile Word *) io_p2v (_ICLR)))
1640#define ICCR /* IC Control Reg. */ \
1641 (*((volatile Word *) io_p2v (_ICCR)))
1642#define ICFP /* IC FIQ Pending reg. */ \
1643 (*((volatile Word *) io_p2v (_ICFP)))
1644#define ICPR /* IC Pending Reg. */ \
1645 (*((volatile Word *) io_p2v (_ICPR)))
1646#endif /* LANGUAGE == C */
1647
1648#define IC_GPIO(Nb) /* GPIO [0..10] */ \
1649 (0x00000001 << (Nb))
1650#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
1651#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
1652#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
1653#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
1654#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
1655#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
1656#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
1657#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
1658#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
1659#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
1660#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
1661#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
1662#define IC_LCD 0x00001000 /* LCD controller */
1663#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
1664#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
1665#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
1666#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
1667#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
1668#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
1669#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
1670#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
1671 (0x00100000 << (Nb))
1672#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
1673#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
1674#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
1675#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
1676#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
1677#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
1678#define IC_OST(Nb) /* OS Timer match [0..3] */ \
1679 (0x04000000 << (Nb))
1680#define IC_OST0 IC_OST (0) /* OS Timer match 0 */
1681#define IC_OST1 IC_OST (1) /* OS Timer match 1 */
1682#define IC_OST2 IC_OST (2) /* OS Timer match 2 */
1683#define IC_OST3 IC_OST (3) /* OS Timer match 3 */
1684#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
1685#define IC_RTCAlrm 0x80000000 /* RTC Alarm */
1686
1687#define ICLR_IRQ 0 /* Interrupt ReQuest */
1688#define ICLR_FIQ 1 /* Fast Interrupt reQuest */
1689
1690#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
1691 /* Mask */
1692#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
1693 /* (ICMR ignored) */
1694#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
1695 /* enable (ICMR used) */
1696
1697
1698/*
1699 * Peripheral Pin Controller (PPC) control registers
1700 *
1701 * Registers
1702 * PPDR Peripheral Pin Controller (PPC) Pin Direction
1703 * Register (read/write).
1704 * PPSR Peripheral Pin Controller (PPC) Pin State Register
1705 * (read/write).
1706 * PPAR Peripheral Pin Controller (PPC) Pin Assignment
1707 * Register (read/write).
1708 * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
1709 * Direction Register (read/write).
1710 * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
1711 * (read).
1712 */
1713
1714#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */
1715#define _PPSR 0x90060004 /* PPC Pin State Reg. */
1716#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */
1717#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */
1718 /* Reg. */
1719#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */
1720
1721#if LANGUAGE == C
1722#define PPDR /* PPC Pin Direction Reg. */ \
1723 (*((volatile Word *) io_p2v (_PPDR)))
1724#define PPSR /* PPC Pin State Reg. */ \
1725 (*((volatile Word *) io_p2v (_PPSR)))
1726#define PPAR /* PPC Pin Assignment Reg. */ \
1727 (*((volatile Word *) io_p2v (_PPAR)))
1728#define PSDR /* PPC Sleep-mode pin Direction */ \
1729 /* Reg. */ \
1730 (*((volatile Word *) io_p2v (_PSDR)))
1731#define PPFR /* PPC Pin Flag Reg. */ \
1732 (*((volatile Word *) io_p2v (_PPFR)))
1733#endif /* LANGUAGE == C */
1734
1735#define PPC_LDD(Nb) /* LCD Data [0..7] */ \
1736 (0x00000001 << (Nb))
1737#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
1738#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
1739#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
1740#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
1741#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
1742#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
1743#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
1744#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
1745#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
1746#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
1747#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
1748#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
1749 /* ser. port 1: */
1750#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
1751#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
1752 /* ser. port 2: */
1753#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
1754#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
1755 /* ser. port 3: */
1756#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
1757#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
1758 /* ser. port 4: */
1759#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
1760#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
1761#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
1762#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
1763
1764#define PPDR_In 0 /* Input */
1765#define PPDR_Out 1 /* Output */
1766
1767 /* ser. port 1: */
1768#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
1769#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
1770#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
1771 /* ser. port 4: */
1772#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
1773#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
1774 /* & SFRM_C */
1775#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
1776
1777#define PSDR_OutL 0 /* Output Low in sleep mode */
1778#define PSDR_Flt 1 /* Floating (input) in sleep mode */
1779
1780#define PPFR_LCD 0x00000001 /* LCD controller */
1781#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
1782#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
1783#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
1784#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
1785#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
1786#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
1787#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
1788#define PPFR_PerEn 0 /* Peripheral Enabled */
1789#define PPFR_PPCEn 1 /* PPC Enabled */
1790
1791
1792/*
1793 * Dynamic Random-Access Memory (DRAM) control registers
1794 *
1795 * Registers
1796 * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
1797 * CoNFiGuration register (read/write).
1798 * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
1799 * Column Address Strobe (CAS) shift register 0
1800 * (read/write).
1801 * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
1802 * Column Address Strobe (CAS) shift register 1
1803 * (read/write).
1804 * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
1805 * Column Address Strobe (CAS) shift register 2
1806 * (read/write).
1807 *
1808 * Clocks
1809 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1810 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
1811 * fcas, Tcas Frequency, period of the DRAM CAS shift registers.
1812 */
1813
1814 /* Memory system: */
1815#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */
1816#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \
1817 (0xA0000004 + (Nb)*4)
1818#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */
1819#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */
1820#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */
1821
1822#if LANGUAGE == C
1823 /* Memory system: */
1824#define MDCNFG /* DRAM CoNFiGuration reg. */ \
1825 (*((volatile Word *) io_p2v (_MDCNFG)))
1826#define MDCAS /* DRAM CAS shift reg. [0..3] */ \
1827 ((volatile Word *) io_p2v (_MDCAS (0)))
1828#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */
1829#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */
1830#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */
1831
1832#elif LANGUAGE == Assembly
1833
1834#define MDCNFG (io_p2v(_MDCNFG))
1835
1836#endif /* LANGUAGE == C */
1837
1838/* SA1100 MDCNFG values */
1839#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
1840 (0x00000001 << (Nb))
1841#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
1842#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
1843#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
1844#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
1845#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
1846#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
1847 (((Add) - 9) << FShft (MDCNFG_DRAC))
1848#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
1849 /* (fcas = fcpu/2) */
1850#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
1851#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
1852 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1853#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
1854 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1855#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
1856#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
1857 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1858#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
1859 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1860#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
1861#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
1862 ((Tcpu) << FShft (MDCNFG_TDL))
1863#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
1864 /* [Tmem] */
1865#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
1866 /* [0..262136 Tcpu] */ \
1867 ((Tcpu)/8 << FShft (MDCNFG_DRI))
1868
1869/* SA1110 MDCNFG values */
1870#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
1871#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
1872#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
1873#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
1874#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
1875 /* bank 0/1 */
1876#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
1877#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
1878#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
1879 /* deassertion 0/1 */
1880#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
1881#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
1882#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
1883#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
1884#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
1885#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
1886 /* bank 0/1 */
1887#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
1888#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
1889#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
1890 /* deassertion 0/1 */
1891#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
1892
1893
1894/*
1895 * Static memory control registers
1896 *
1897 * Registers
1898 * MSC0 Memory system: Static memory Control register 0
1899 * (read/write).
1900 * MSC1 Memory system: Static memory Control register 1
1901 * (read/write).
1902 *
1903 * Clocks
1904 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1905 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
1906 */
1907
1908 /* Memory system: */
1909#define _MSC(Nb) /* Static memory Control reg. */ \
1910 /* [0..1] */ \
1911 (0xA0000010 + (Nb)*4)
1912#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */
1913#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */
1914#define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */
1915
1916#if LANGUAGE == C
1917 /* Memory system: */
1918#define MSC /* Static memory Control reg. */ \
1919 /* [0..1] */ \
1920 ((volatile Word *) io_p2v (_MSC (0)))
1921#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */
1922#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */
1923#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */
1924
1925#elif LANGUAGE == Assembly
1926
1927#define MSC0 io_p2v(0xa0000010)
1928#define MSC1 io_p2v(0xa0000014)
1929#define MSC2 io_p2v(0xa000002c)
1930
1931#endif /* LANGUAGE == C */
1932
1933#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
1934 Fld (16, ((Nb) Modulo 2)*16)
1935#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
1936#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
1937#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
1938#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
1939
1940#define MSC_RT Fld (2, 0) /* ROM/static memory Type */
1941#define MSC_NonBrst /* Non-Burst static memory */ \
1942 (0 << FShft (MSC_RT))
1943#define MSC_SRAM /* 32-bit byte-writable SRAM */ \
1944 (1 << FShft (MSC_RT))
1945#define MSC_Brst4 /* Burst-of-4 static memory */ \
1946 (2 << FShft (MSC_RT))
1947#define MSC_Brst8 /* Burst-of-8 static memory */ \
1948 (3 << FShft (MSC_RT))
1949#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
1950#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
1951#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
1952#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
1953 /* First access - 1(.5) [Tmem] */
1954#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
1955 /* static memory) [3..65 Tcpu] */ \
1956 ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1957#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
1958 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1959#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
1960 /* static memory) [2..64 Tcpu] */ \
1961 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1962#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
1963 ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1964#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
1965 /* Next access - 1 [Tmem] */
1966#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
1967 /* static memory) [2..64 Tcpu] */ \
1968 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1969#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
1970 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1971#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
1972 /* static memory) [2..64 Tcpu] */ \
1973 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1974#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
1975 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1976#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
1977 /* time/2 [Tmem] */
1978#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
1979 (((Tcpu)/4) << FShft (MSC_RRR))
1980#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
1981 ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
1982
1983
1984/*
1985 * Personal Computer Memory Card International Association (PCMCIA) control
1986 * register
1987 *
1988 * Register
1989 * MECR Memory system: Expansion memory bus (PCMCIA)
1990 * Configuration Register (read/write).
1991 *
1992 * Clocks
1993 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
1994 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
1995 * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK).
1996 */
1997
1998 /* Memory system: */
1999#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */
2000 /* Configuration Reg. */
2001
2002#if LANGUAGE == C
2003 /* Memory system: */
2004#define MECR /* Expansion memory bus (PCMCIA) */ \
2005 /* Configuration Reg. */ \
2006 (*((volatile Word *) io_p2v (_MECR)))
2007#endif /* LANGUAGE == C */
2008
2009#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
2010 Fld (15, (Nb)*16)
2011#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
2012#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
2013
2014#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
2015#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
2016 ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
2017#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
2018 ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
2019#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
2020 /* [Tmem] */
2021#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
2022 ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
2023#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
2024 ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
2025#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
2026#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
2027 ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
2028#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
2029 ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
2030
2031/*
2032 * On SA1110 only
2033 */
2034
2035#define _MDREFR 0xA000001C
2036
2037#if LANGUAGE == C
2038 /* Memory system: */
2039#define MDREFR \
2040 (*((volatile Word *) io_p2v (_MDREFR)))
2041
2042#elif LANGUAGE == Assembly
2043
2044#define MDREFR (io_p2v(_MDREFR))
2045
2046#endif /* LANGUAGE == C */
2047
2048#define MDREFR_TRASR Fld (4, 0)
2049#define MDREFR_DRI Fld (12, 4)
2050#define MDREFR_E0PIN (1 << 16)
2051#define MDREFR_K0RUN (1 << 17)
2052#define MDREFR_K0DB2 (1 << 18)
2053#define MDREFR_E1PIN (1 << 20)
2054#define MDREFR_K1RUN (1 << 21)
2055#define MDREFR_K1DB2 (1 << 22)
2056#define MDREFR_K2RUN (1 << 25)
2057#define MDREFR_K2DB2 (1 << 26)
2058#define MDREFR_EAPD (1 << 28)
2059#define MDREFR_KAPD (1 << 29)
2060#define MDREFR_SLFRSH (1 << 31)
2061
2062
2063/*
2064 * Direct Memory Access (DMA) control registers
2065 *
2066 * Registers
2067 * DDAR0 Direct Memory Access (DMA) Device Address Register
2068 * channel 0 (read/write).
2069 * DCSR0 Direct Memory Access (DMA) Control and Status
2070 * Register channel 0 (read/write).
2071 * DBSA0 Direct Memory Access (DMA) Buffer Start address
2072 * register A channel 0 (read/write).
2073 * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
2074 * register A channel 0 (read/write).
2075 * DBSB0 Direct Memory Access (DMA) Buffer Start address
2076 * register B channel 0 (read/write).
2077 * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
2078 * register B channel 0 (read/write).
2079 *
2080 * DDAR1 Direct Memory Access (DMA) Device Address Register
2081 * channel 1 (read/write).
2082 * DCSR1 Direct Memory Access (DMA) Control and Status
2083 * Register channel 1 (read/write).
2084 * DBSA1 Direct Memory Access (DMA) Buffer Start address
2085 * register A channel 1 (read/write).
2086 * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
2087 * register A channel 1 (read/write).
2088 * DBSB1 Direct Memory Access (DMA) Buffer Start address
2089 * register B channel 1 (read/write).
2090 * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
2091 * register B channel 1 (read/write).
2092 *
2093 * DDAR2 Direct Memory Access (DMA) Device Address Register
2094 * channel 2 (read/write).
2095 * DCSR2 Direct Memory Access (DMA) Control and Status
2096 * Register channel 2 (read/write).
2097 * DBSA2 Direct Memory Access (DMA) Buffer Start address
2098 * register A channel 2 (read/write).
2099 * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
2100 * register A channel 2 (read/write).
2101 * DBSB2 Direct Memory Access (DMA) Buffer Start address
2102 * register B channel 2 (read/write).
2103 * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
2104 * register B channel 2 (read/write).
2105 *
2106 * DDAR3 Direct Memory Access (DMA) Device Address Register
2107 * channel 3 (read/write).
2108 * DCSR3 Direct Memory Access (DMA) Control and Status
2109 * Register channel 3 (read/write).
2110 * DBSA3 Direct Memory Access (DMA) Buffer Start address
2111 * register A channel 3 (read/write).
2112 * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
2113 * register A channel 3 (read/write).
2114 * DBSB3 Direct Memory Access (DMA) Buffer Start address
2115 * register B channel 3 (read/write).
2116 * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
2117 * register B channel 3 (read/write).
2118 *
2119 * DDAR4 Direct Memory Access (DMA) Device Address Register
2120 * channel 4 (read/write).
2121 * DCSR4 Direct Memory Access (DMA) Control and Status
2122 * Register channel 4 (read/write).
2123 * DBSA4 Direct Memory Access (DMA) Buffer Start address
2124 * register A channel 4 (read/write).
2125 * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
2126 * register A channel 4 (read/write).
2127 * DBSB4 Direct Memory Access (DMA) Buffer Start address
2128 * register B channel 4 (read/write).
2129 * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
2130 * register B channel 4 (read/write).
2131 *
2132 * DDAR5 Direct Memory Access (DMA) Device Address Register
2133 * channel 5 (read/write).
2134 * DCSR5 Direct Memory Access (DMA) Control and Status
2135 * Register channel 5 (read/write).
2136 * DBSA5 Direct Memory Access (DMA) Buffer Start address
2137 * register A channel 5 (read/write).
2138 * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
2139 * register A channel 5 (read/write).
2140 * DBSB5 Direct Memory Access (DMA) Buffer Start address
2141 * register B channel 5 (read/write).
2142 * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
2143 * register B channel 5 (read/write).
2144 */
2145
2146#define DMASp 0x00000020 /* DMA control reg. Space [byte] */
2147
2148#define _DDAR(Nb) /* DMA Device Address Reg. */ \
2149 /* channel [0..5] */ \
2150 (0xB0000000 + (Nb)*DMASp)
2151#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \
2152 /* channel [0..5] (write) */ \
2153 (0xB0000004 + (Nb)*DMASp)
2154#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \
2155 /* channel [0..5] (write) */ \
2156 (0xB0000008 + (Nb)*DMASp)
2157#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \
2158 /* channel [0..5] (read) */ \
2159 (0xB000000C + (Nb)*DMASp)
2160#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \
2161 /* channel [0..5] */ \
2162 (0xB0000010 + (Nb)*DMASp)
2163#define _DBTA(Nb) /* DMA Buffer Transfer count */ \
2164 /* reg. A channel [0..5] */ \
2165 (0xB0000014 + (Nb)*DMASp)
2166#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \
2167 /* channel [0..5] */ \
2168 (0xB0000018 + (Nb)*DMASp)
2169#define _DBTB(Nb) /* DMA Buffer Transfer count */ \
2170 /* reg. B channel [0..5] */ \
2171 (0xB000001C + (Nb)*DMASp)
2172
2173#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */
2174 /* channel 0 */
2175#define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */
2176 /* channel 0 (write) */
2177#define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */
2178 /* channel 0 (write) */
2179#define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */
2180 /* channel 0 (read) */
2181#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */
2182 /* channel 0 */
2183#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */
2184 /* reg. A channel 0 */
2185#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */
2186 /* channel 0 */
2187#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */
2188 /* reg. B channel 0 */
2189
2190#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */
2191 /* channel 1 */
2192#define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */
2193 /* channel 1 (write) */
2194#define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */
2195 /* channel 1 (write) */
2196#define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */
2197 /* channel 1 (read) */
2198#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */
2199 /* channel 1 */
2200#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */
2201 /* reg. A channel 1 */
2202#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */
2203 /* channel 1 */
2204#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */
2205 /* reg. B channel 1 */
2206
2207#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */
2208 /* channel 2 */
2209#define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */
2210 /* channel 2 (write) */
2211#define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */
2212 /* channel 2 (write) */
2213#define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */
2214 /* channel 2 (read) */
2215#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */
2216 /* channel 2 */
2217#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */
2218 /* reg. A channel 2 */
2219#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */
2220 /* channel 2 */
2221#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */
2222 /* reg. B channel 2 */
2223
2224#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */
2225 /* channel 3 */
2226#define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */
2227 /* channel 3 (write) */
2228#define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */
2229 /* channel 3 (write) */
2230#define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */
2231 /* channel 3 (read) */
2232#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */
2233 /* channel 3 */
2234#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */
2235 /* reg. A channel 3 */
2236#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */
2237 /* channel 3 */
2238#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */
2239 /* reg. B channel 3 */
2240
2241#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */
2242 /* channel 4 */
2243#define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */
2244 /* channel 4 (write) */
2245#define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */
2246 /* channel 4 (write) */
2247#define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */
2248 /* channel 4 (read) */
2249#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */
2250 /* channel 4 */
2251#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */
2252 /* reg. A channel 4 */
2253#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */
2254 /* channel 4 */
2255#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */
2256 /* reg. B channel 4 */
2257
2258#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */
2259 /* channel 5 */
2260#define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */
2261 /* channel 5 (write) */
2262#define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */
2263 /* channel 5 (write) */
2264#define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */
2265 /* channel 5 (read) */
2266#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */
2267 /* channel 5 */
2268#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */
2269 /* reg. A channel 5 */
2270#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */
2271 /* channel 5 */
2272#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */
2273 /* reg. B channel 5 */
2274
2275#if LANGUAGE == C
2276
2277#define DDAR0 /* DMA Device Address Reg. */ \
2278 /* channel 0 */ \
2279 (*((volatile Word *) io_p2v (_DDAR0)))
2280#define SetDCSR0 /* Set DMA Control & Status Reg. */ \
2281 /* channel 0 (write) */ \
2282 (*((volatile Word *) io_p2v (_SetDCSR0)))
2283#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \
2284 /* channel 0 (write) */ \
2285 (*((volatile Word *) io_p2v (_ClrDCSR0)))
2286#define RdDCSR0 /* Read DMA Control & Status Reg. */ \
2287 /* channel 0 (read) */ \
2288 (*((volatile Word *) io_p2v (_RdDCSR0)))
2289#define DBSA0 /* DMA Buffer Start address reg. A */ \
2290 /* channel 0 */ \
2291 (*((volatile Address *) io_p2v (_DBSA0)))
2292#define DBTA0 /* DMA Buffer Transfer count */ \
2293 /* reg. A channel 0 */ \
2294 (*((volatile Word *) io_p2v (_DBTA0)))
2295#define DBSB0 /* DMA Buffer Start address reg. B */ \
2296 /* channel 0 */ \
2297 (*((volatile Address *) io_p2v (_DBSB0)))
2298#define DBTB0 /* DMA Buffer Transfer count */ \
2299 /* reg. B channel 0 */ \
2300 (*((volatile Word *) io_p2v (_DBTB0)))
2301
2302#define DDAR1 /* DMA Device Address Reg. */ \
2303 /* channel 1 */ \
2304 (*((volatile Word *) io_p2v (_DDAR1)))
2305#define SetDCSR1 /* Set DMA Control & Status Reg. */ \
2306 /* channel 1 (write) */ \
2307 (*((volatile Word *) io_p2v (_SetDCSR1)))
2308#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \
2309 /* channel 1 (write) */ \
2310 (*((volatile Word *) io_p2v (_ClrDCSR1)))
2311#define RdDCSR1 /* Read DMA Control & Status Reg. */ \
2312 /* channel 1 (read) */ \
2313 (*((volatile Word *) io_p2v (_RdDCSR1)))
2314#define DBSA1 /* DMA Buffer Start address reg. A */ \
2315 /* channel 1 */ \
2316 (*((volatile Address *) io_p2v (_DBSA1)))
2317#define DBTA1 /* DMA Buffer Transfer count */ \
2318 /* reg. A channel 1 */ \
2319 (*((volatile Word *) io_p2v (_DBTA1)))
2320#define DBSB1 /* DMA Buffer Start address reg. B */ \
2321 /* channel 1 */ \
2322 (*((volatile Address *) io_p2v (_DBSB1)))
2323#define DBTB1 /* DMA Buffer Transfer count */ \
2324 /* reg. B channel 1 */ \
2325 (*((volatile Word *) io_p2v (_DBTB1)))
2326
2327#define DDAR2 /* DMA Device Address Reg. */ \
2328 /* channel 2 */ \
2329 (*((volatile Word *) io_p2v (_DDAR2)))
2330#define SetDCSR2 /* Set DMA Control & Status Reg. */ \
2331 /* channel 2 (write) */ \
2332 (*((volatile Word *) io_p2v (_SetDCSR2)))
2333#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \
2334 /* channel 2 (write) */ \
2335 (*((volatile Word *) io_p2v (_ClrDCSR2)))
2336#define RdDCSR2 /* Read DMA Control & Status Reg. */ \
2337 /* channel 2 (read) */ \
2338 (*((volatile Word *) io_p2v (_RdDCSR2)))
2339#define DBSA2 /* DMA Buffer Start address reg. A */ \
2340 /* channel 2 */ \
2341 (*((volatile Address *) io_p2v (_DBSA2)))
2342#define DBTA2 /* DMA Buffer Transfer count */ \
2343 /* reg. A channel 2 */ \
2344 (*((volatile Word *) io_p2v (_DBTA2)))
2345#define DBSB2 /* DMA Buffer Start address reg. B */ \
2346 /* channel 2 */ \
2347 (*((volatile Address *) io_p2v (_DBSB2)))
2348#define DBTB2 /* DMA Buffer Transfer count */ \
2349 /* reg. B channel 2 */ \
2350 (*((volatile Word *) io_p2v (_DBTB2)))
2351
2352#define DDAR3 /* DMA Device Address Reg. */ \
2353 /* channel 3 */ \
2354 (*((volatile Word *) io_p2v (_DDAR3)))
2355#define SetDCSR3 /* Set DMA Control & Status Reg. */ \
2356 /* channel 3 (write) */ \
2357 (*((volatile Word *) io_p2v (_SetDCSR3)))
2358#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \
2359 /* channel 3 (write) */ \
2360 (*((volatile Word *) io_p2v (_ClrDCSR3)))
2361#define RdDCSR3 /* Read DMA Control & Status Reg. */ \
2362 /* channel 3 (read) */ \
2363 (*((volatile Word *) io_p2v (_RdDCSR3)))
2364#define DBSA3 /* DMA Buffer Start address reg. A */ \
2365 /* channel 3 */ \
2366 (*((volatile Address *) io_p2v (_DBSA3)))
2367#define DBTA3 /* DMA Buffer Transfer count */ \
2368 /* reg. A channel 3 */ \
2369 (*((volatile Word *) io_p2v (_DBTA3)))
2370#define DBSB3 /* DMA Buffer Start address reg. B */ \
2371 /* channel 3 */ \
2372 (*((volatile Address *) io_p2v (_DBSB3)))
2373#define DBTB3 /* DMA Buffer Transfer count */ \
2374 /* reg. B channel 3 */ \
2375 (*((volatile Word *) io_p2v (_DBTB3)))
2376
2377#define DDAR4 /* DMA Device Address Reg. */ \
2378 /* channel 4 */ \
2379 (*((volatile Word *) io_p2v (_DDAR4)))
2380#define SetDCSR4 /* Set DMA Control & Status Reg. */ \
2381 /* channel 4 (write) */ \
2382 (*((volatile Word *) io_p2v (_SetDCSR4)))
2383#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \
2384 /* channel 4 (write) */ \
2385 (*((volatile Word *) io_p2v (_ClrDCSR4)))
2386#define RdDCSR4 /* Read DMA Control & Status Reg. */ \
2387 /* channel 4 (read) */ \
2388 (*((volatile Word *) io_p2v (_RdDCSR4)))
2389#define DBSA4 /* DMA Buffer Start address reg. A */ \
2390 /* channel 4 */ \
2391 (*((volatile Address *) io_p2v (_DBSA4)))
2392#define DBTA4 /* DMA Buffer Transfer count */ \
2393 /* reg. A channel 4 */ \
2394 (*((volatile Word *) io_p2v (_DBTA4)))
2395#define DBSB4 /* DMA Buffer Start address reg. B */ \
2396 /* channel 4 */ \
2397 (*((volatile Address *) io_p2v (_DBSB4)))
2398#define DBTB4 /* DMA Buffer Transfer count */ \
2399 /* reg. B channel 4 */ \
2400 (*((volatile Word *) io_p2v (_DBTB4)))
2401
2402#define DDAR5 /* DMA Device Address Reg. */ \
2403 /* channel 5 */ \
2404 (*((volatile Word *) io_p2v (_DDAR5)))
2405#define SetDCSR5 /* Set DMA Control & Status Reg. */ \
2406 /* channel 5 (write) */ \
2407 (*((volatile Word *) io_p2v (_SetDCSR5)))
2408#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \
2409 /* channel 5 (write) */ \
2410 (*((volatile Word *) io_p2v (_ClrDCSR5)))
2411#define RdDCSR5 /* Read DMA Control & Status Reg. */ \
2412 /* channel 5 (read) */ \
2413 (*((volatile Word *) io_p2v (_RdDCSR5)))
2414#define DBSA5 /* DMA Buffer Start address reg. A */ \
2415 /* channel 5 */ \
2416 (*((volatile Address *) io_p2v (_DBSA5)))
2417#define DBTA5 /* DMA Buffer Transfer count */ \
2418 /* reg. A channel 5 */ \
2419 (*((volatile Word *) io_p2v (_DBTA5)))
2420#define DBSB5 /* DMA Buffer Start address reg. B */ \
2421 /* channel 5 */ \
2422 (*((volatile Address *) io_p2v (_DBSB5)))
2423#define DBTB5 /* DMA Buffer Transfer count */ \
2424 /* reg. B channel 5 */ \
2425 (*((volatile Word *) io_p2v (_DBTB5)))
2426
2427#endif /* LANGUAGE == C */
2428
2429#define DDAR_RW 0x00000001 /* device data Read/Write */
2430#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
2431 /* (memory -> device) */
2432#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
2433 /* (device -> memory) */
2434#define DDAR_E 0x00000002 /* big/little Endian device */
2435#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
2436#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
2437#define DDAR_BS 0x00000004 /* device Burst Size */
2438#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
2439#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
2440#define DDAR_DW 0x00000008 /* device Data Width */
2441#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
2442#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
2443#define DDAR_DS Fld (4, 4) /* Device Select */
2444#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
2445 (0x0 << FShft (DDAR_DS))
2446#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
2447 (0x1 << FShft (DDAR_DS))
2448#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
2449 (0x2 << FShft (DDAR_DS))
2450#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
2451 (0x3 << FShft (DDAR_DS))
2452#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
2453 (0x4 << FShft (DDAR_DS))
2454#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
2455 (0x5 << FShft (DDAR_DS))
2456#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
2457 (0x6 << FShft (DDAR_DS))
2458#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
2459 (0x7 << FShft (DDAR_DS))
2460#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
2461 (0x8 << FShft (DDAR_DS))
2462#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
2463 (0x9 << FShft (DDAR_DS))
2464#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
2465 /* (audio) */ \
2466 (0xA << FShft (DDAR_DS))
2467#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
2468 /* (audio) */ \
2469 (0xB << FShft (DDAR_DS))
2470#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
2471 /* (telecom) */ \
2472 (0xC << FShft (DDAR_DS))
2473#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
2474 /* (telecom) */ \
2475 (0xD << FShft (DDAR_DS))
2476#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
2477 (0xE << FShft (DDAR_DS))
2478#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
2479 (0xF << FShft (DDAR_DS))
2480#define DDAR_DA Fld (24, 8) /* Device Address */
2481#define DDAR_DevAdd(Add) /* Device Address */ \
2482 (((Add) & 0xF0000000) | \
2483 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
2484#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
2485 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
2486 DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
2487#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
2488 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
2489 DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
2490#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
2491 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
2492 DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
2493#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
2494 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
2495 DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
2496#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
2497 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
2498 DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
2499#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
2500 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
2501 DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
2502#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
2503 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
2504 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
2505#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
2506 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
2507 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
2508#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
2509 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
2510 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
2511#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
2512 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
2513 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
2514#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
2515 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
2516 DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
2517#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
2518 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
2519 DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
2520#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
2521 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
2522 DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
2523#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
2524 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
2525 DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
2526#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
2527 /* (telecom) */ \
2528 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
2529 DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
2530#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
2531 /* (telecom) */ \
2532 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
2533 DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
2534#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
2535 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
2536 DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
2537#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
2538 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
2539 DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
2540
2541#define DCSR_RUN 0x00000001 /* DMA RUNing */
2542#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
2543#define DCSR_ERROR 0x00000004 /* DMA ERROR */
2544#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
2545#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
2546#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
2547#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
2548#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
2549#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
2550#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
2551
2552#define DBT_TC Fld (13, 0) /* Transfer Count */
2553#define DBTA_TCA DBT_TC /* Transfer Count buffer A */
2554#define DBTB_TCB DBT_TC /* Transfer Count buffer B */
2555
2556
2557/*
2558 * Liquid Crystal Display (LCD) control registers
2559 *
2560 * Registers
2561 * LCCR0 Liquid Crystal Display (LCD) Control Register 0
2562 * (read/write).
2563 * [Bits LDM, BAM, and ERM are only implemented in
2564 * versions 2.0 (rev. = 8) and higher of the StrongARM
2565 * SA-1100.]
2566 * LCSR Liquid Crystal Display (LCD) Status Register
2567 * (read/write).
2568 * [Bit LDD can be only read in versions 1.0 (rev. = 1)
2569 * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
2570 * read and written (cleared) in versions 2.0 (rev. = 8)
2571 * and higher.]
2572 * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
2573 * (DMA) Base Address Register channel 1 (read/write).
2574 * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
2575 * (DMA) Current Address Register channel 1 (read).
2576 * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
2577 * (DMA) Base Address Register channel 2 (read/write).
2578 * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
2579 * (DMA) Current Address Register channel 2 (read).
2580 * LCCR1 Liquid Crystal Display (LCD) Control Register 1
2581 * (read/write).
2582 * [The LCCR1 register can be only written in
2583 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
2584 * StrongARM SA-1100, it can be written and read in
2585 * versions 2.0 (rev. = 8) and higher.]
2586 * LCCR2 Liquid Crystal Display (LCD) Control Register 2
2587 * (read/write).
2588 * [The LCCR1 register can be only written in
2589 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
2590 * StrongARM SA-1100, it can be written and read in
2591 * versions 2.0 (rev. = 8) and higher.]
2592 * LCCR3 Liquid Crystal Display (LCD) Control Register 3
2593 * (read/write).
2594 * [The LCCR1 register can be only written in
2595 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
2596 * StrongARM SA-1100, it can be written and read in
2597 * versions 2.0 (rev. = 8) and higher. Bit PCP is only
2598 * implemented in versions 2.0 (rev. = 8) and higher of
2599 * the StrongARM SA-1100.]
2600 *
2601 * Clocks
2602 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
2603 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
2604 * fpix, Tpix Frequency, period of the pixel clock.
2605 * fln, Tln Frequency, period of the line clock.
2606 * fac, Tac Frequency, period of the AC bias clock.
2607 */
2608
2609#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
2610#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
2611 /* [byte] */ \
2612 (16*LCD_PEntrySp)
2613#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
2614 /* [byte] */ \
2615 (256*LCD_PEntrySp)
2616#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
2617 /* dummy-Palette Space [byte] */ \
2618 (16*LCD_PEntrySp)
2619
2620#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
2621#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
2622#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
2623#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
2624#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
2625#define LCD_4Bit /* LCD 4-Bit pixel mode */ \
2626 (0 << FShft (LCD_PBS))
2627#define LCD_8Bit /* LCD 8-Bit pixel mode */ \
2628 (1 << FShft (LCD_PBS))
2629#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
2630 (2 << FShft (LCD_PBS))
2631
2632#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
2633#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
2634#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
2635#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
2636#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
2637#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
2638#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
2639#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
2640#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
2641#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
2642#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
2643#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
2644#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
2645#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
2646#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
2647#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
2648 /* (Alternative) */
2649
2650#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */
2651#define _LCSR 0xB0100004 /* LCD Status Reg. */
2652#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */
2653 /* channel 1 */
2654#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */
2655 /* channel 1 */
2656#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */
2657 /* channel 2 */
2658#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */
2659 /* channel 2 */
2660#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */
2661#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */
2662#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */
2663
2664#if LANGUAGE == C
2665#define LCCR0 /* LCD Control Reg. 0 */ \
2666 (*((volatile Word *) io_p2v (_LCCR0)))
2667#define LCSR /* LCD Status Reg. */ \
2668 (*((volatile Word *) io_p2v (_LCSR)))
2669#define DBAR1 /* LCD DMA Base Address Reg. */ \
2670 /* channel 1 */ \
2671 (*((volatile Address *) io_p2v (_DBAR1)))
2672#define DCAR1 /* LCD DMA Current Address Reg. */ \
2673 /* channel 1 */ \
2674 (*((volatile Address *) io_p2v (_DCAR1)))
2675#define DBAR2 /* LCD DMA Base Address Reg. */ \
2676 /* channel 2 */ \
2677 (*((volatile Address *) io_p2v (_DBAR2)))
2678#define DCAR2 /* LCD DMA Current Address Reg. */ \
2679 /* channel 2 */ \
2680 (*((volatile Address *) io_p2v (_DCAR2)))
2681#define LCCR1 /* LCD Control Reg. 1 */ \
2682 (*((volatile Word *) io_p2v (_LCCR1)))
2683#define LCCR2 /* LCD Control Reg. 2 */ \
2684 (*((volatile Word *) io_p2v (_LCCR2)))
2685#define LCCR3 /* LCD Control Reg. 3 */ \
2686 (*((volatile Word *) io_p2v (_LCCR3)))
2687#endif /* LANGUAGE == C */
2688
2689#define LCCR0_LEN 0x00000001 /* LCD ENable */
2690#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
2691#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
2692#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
2693#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
2694 /* Select */
2695#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
2696#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
2697#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
2698 /* interrupt Mask (disable) */
2699#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
2700 /* interrupt Mask (disable) */
2701#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
2702 /* IUU, OOL, OUL, OOU, and OUU) */
2703 /* interrupt Mask (disable) */
2704#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
2705#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
2706#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
2707#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
2708#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
2709#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
2710#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
2711 /* display mode) */
2712#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
2713 /* display */
2714#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
2715 /* display */
2716#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
2717 /* [Tmem] */
2718#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
2719 /* [0..510 Tcpu] */ \
2720 ((Tcpu)/2 << FShft (LCCR0_PDD))
2721
2722#define LCSR_LDD 0x00000001 /* LCD Disable Done */
2723#define LCSR_BAU 0x00000002 /* Base Address Update (read) */
2724#define LCSR_BER 0x00000004 /* Bus ERror */
2725#define LCSR_ABC 0x00000008 /* AC Bias clock Count */
2726#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
2727 /* panel */
2728#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
2729 /* panel */
2730#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
2731 /* panel */
2732#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
2733 /* panel */
2734#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
2735 /* panel */
2736#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
2737 /* panel */
2738#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
2739 /* panel */
2740#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
2741 /* panel */
2742
2743#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
2744#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
2745 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
2746#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
2747 /* pulse Width - 2 [Tpix] (L_LCLK) */
2748#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
2749 /* pulse Width [2..65 Tpix] */ \
2750 (((Tpix) - 2) << FShft (LCCR1_HSW))
2751#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2752 /* count - 1 [Tpix] */
2753#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
2754 /* [1..256 Tpix] */ \
2755 (((Tpix) - 1) << FShft (LCCR1_ELW))
2756#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2757 /* Wait count - 1 [Tpix] */
2758#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
2759 /* [1..256 Tpix] */ \
2760 (((Tpix) - 1) << FShft (LCCR1_BLW))
2761
2762#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2763#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
2764 (((Line) - 1) << FShft (LCCR2_LPP))
2765#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
2766 /* Width - 1 [Tln] (L_FCLK) */
2767#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
2768 /* Width [1..64 Tln] */ \
2769 (((Tln) - 1) << FShft (LCCR2_VSW))
2770#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2771 /* count [Tln] */
2772#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
2773 /* [0..255 Tln] */ \
2774 ((Tln) << FShft (LCCR2_EFW))
2775#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2776 /* Wait count [Tln] */
2777#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
2778 /* [0..255 Tln] */ \
2779 ((Tln) << FShft (LCCR2_BFW))
2780
2781#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
2782 /* [1..255] (L_PCLK) */
2783 /* fpix = fcpu/(2*(PCD + 2)) */
2784 /* Tpix = 2*(PCD + 2)*Tcpu */
2785#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
2786 (((Div) - 4)/2 << FShft (LCCR3_PCD))
2787 /* fpix = fcpu/(2*Floor (Div/2)) */
2788 /* Tpix = 2*Floor (Div/2)*Tcpu */
2789#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
2790 (((Div) - 3)/2 << FShft (LCCR3_PCD))
2791 /* fpix = fcpu/(2*Ceil (Div/2)) */
2792 /* Tpix = 2*Ceil (Div/2)*Tcpu */
2793#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
2794 /* [Tln] (L_BIAS) */
2795#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
2796 (((Div) - 2)/2 << FShft (LCCR3_ACB))
2797 /* fac = fln/(2*Floor (Div/2)) */
2798 /* Tac = 2*Floor (Div/2)*Tln */
2799#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
2800 (((Div) - 1)/2 << FShft (LCCR3_ACB))
2801 /* fac = fln/(2*Ceil (Div/2)) */
2802 /* Tac = 2*Ceil (Div/2)*Tln */
2803#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
2804 /* Interrupt */
2805#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
2806 /* Off */ \
2807 (0 << FShft (LCCR3_API))
2808#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
2809 /* [1..15] */ \
2810 ((Trans) << FShft (LCCR3_API))
2811#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
2812 /* Polarity (L_FCLK) */
2813#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
2814 /* active High */
2815#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
2816 /* active Low */
2817#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
2818 /* pulse Polarity (L_LCLK) */
2819#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
2820 /* pulse active High */
2821#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
2822 /* pulse active Low */
2823#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
2824#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
2825#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
2826#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
2827 /* active display mode) */
2828#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
2829#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
2830
2831
2832#undef C
2833#undef Assembly
2834