Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
| 4 | * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 7 | #include <asm-offsets.h> |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 8 | #include <config.h> |
| 9 | #include "version.h" |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 10 | #include <asm/cache.h> |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 11 | |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 12 | #define _START _start |
| 13 | #define _FAULT _fault |
| 14 | |
| 15 | #define SAVE_ALL \ |
| 16 | move.w #0x2700,%sr; /* disable intrs */ \ |
| 17 | subl #60,%sp; /* space for 15 regs */ \ |
| 18 | moveml %d0-%d7/%a0-%a6,%sp@; |
| 19 | |
| 20 | #define RESTORE_ALL \ |
| 21 | moveml %sp@,%d0-%d7/%a0-%a6; \ |
| 22 | addl #60,%sp; /* space for 15 regs */ \ |
| 23 | rte; |
| 24 | |
| 25 | .text |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 26 | |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 27 | /* |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 28 | * Vector table. This is used for initial platform startup. |
| 29 | * These vectors are to catch any un-intended traps. |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 30 | */ |
| 31 | _vectors: |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 32 | INITSP: .long 0x00000000 /* Initial SP */ |
| 33 | INITPC: .long _START /* Initial PC */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 34 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 35 | vector02_0F: |
| 36 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 37 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 38 | |
| 39 | /* Reserved */ |
| 40 | vector10_17: |
| 41 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 42 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 43 | vector18_1F: |
| 44 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 45 | |
| 46 | /* TRAP #0 - #15 */ |
| 47 | vector20_2F: |
| 48 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 49 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 50 | |
| 51 | /* Reserved */ |
| 52 | vector30_3F: |
| 53 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 54 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 55 | |
| 56 | vector64_127: |
| 57 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 58 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 59 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 60 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 61 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 62 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 63 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 64 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 65 | |
| 66 | vector128_191: |
| 67 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 68 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 69 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 70 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 71 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 72 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 73 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 74 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 75 | |
| 76 | vector192_255: |
| 77 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 78 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 79 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 80 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 81 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 82 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 83 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 84 | .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT |
| 85 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 86 | .text |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 87 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 88 | .globl _start |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 89 | _start: |
| 90 | nop |
| 91 | nop |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 92 | move.w #0x2700,%sr /* Mask off Interrupt */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 93 | |
| 94 | /* Set vector base register at the beginning of the Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 95 | move.l #CONFIG_SYS_FLASH_BASE, %d0 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 96 | movec %d0, %VBR |
| 97 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 98 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 99 | movec %d0, %RAMBAR1 |
| 100 | |
| 101 | /* invalidate and disable cache */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 102 | move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ |
| 103 | movec %d0, %CACR /* Invalidate cache */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 104 | nop |
| 105 | move.l #0, %d0 |
| 106 | movec %d0, %ACR0 |
| 107 | movec %d0, %ACR1 |
| 108 | |
| 109 | /* initialize general use internal ram */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 110 | move.l #0, %d0 |
| 111 | move.l #(ICACHE_STATUS), %a1 /* icache */ |
| 112 | move.l #(DCACHE_STATUS), %a2 /* icache */ |
| 113 | move.l %d0, (%a1) |
| 114 | move.l %d0, (%a2) |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 115 | |
angelo@sysam.it | 5044c9c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 116 | /* put relocation table address to a5 */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 117 | move.l #__got_start, %a5 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 118 | |
angelo@sysam.it | 5044c9c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 119 | /* setup stack initially on top of internal static ram */ |
| 120 | move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp |
| 121 | |
| 122 | /* |
| 123 | * if configured, malloc_f arena will be reserved first, |
| 124 | * then (and always) gd struct space will be reserved |
| 125 | */ |
| 126 | move.l %sp, -(%sp) |
| 127 | move.l #board_init_f_alloc_reserve, %a1 |
| 128 | jsr (%a1) |
| 129 | |
| 130 | /* update stack and frame-pointers */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 131 | move.l %d0, %sp |
| 132 | move.l %sp, %fp |
angelo@sysam.it | 5044c9c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 133 | |
| 134 | /* initialize reserved area */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 135 | move.l %d0, -(%sp) |
angelo@sysam.it | 5044c9c | 2016-04-27 21:50:44 +0200 | [diff] [blame] | 136 | move.l #board_init_f_init_reserve, %a1 |
| 137 | jsr (%a1) |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 138 | |
angelo@sysam.it | 55ac54c | 2016-04-12 00:30:59 +0200 | [diff] [blame] | 139 | /* run low-level CPU init code (from flash) */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 140 | move.l #cpu_init_f, %a1 |
| 141 | jsr (%a1) |
| 142 | |
angelo@sysam.it | 55ac54c | 2016-04-12 00:30:59 +0200 | [diff] [blame] | 143 | /* run low-level board init code (from flash) */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 144 | clr.l %sp@- |
| 145 | move.l #board_init_f, %a1 |
| 146 | jsr (%a1) |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 147 | |
| 148 | /* board_init_f() does not return */ |
| 149 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 150 | /******************************************************************************/ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 151 | |
| 152 | /* |
| 153 | * void relocate_code (addr_sp, gd, addr_moni) |
| 154 | * |
| 155 | * This "function" does not return, instead it continues in RAM |
| 156 | * after relocating the monitor code. |
| 157 | * |
| 158 | * r3 = dest |
| 159 | * r4 = src |
| 160 | * r5 = length in bytes |
| 161 | * r6 = cachelinesize |
| 162 | */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 163 | .globl relocate_code |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 164 | relocate_code: |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 165 | link.w %a6,#0 |
| 166 | move.l 8(%a6), %sp /* set new stack pointer */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 167 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 168 | move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ |
| 169 | move.l 16(%a6), %a0 /* Save copy of Destination Address */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 170 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 171 | move.l #CONFIG_SYS_MONITOR_BASE, %a1 |
| 172 | move.l #__init_end, %a2 |
| 173 | move.l %a0, %a3 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 174 | |
| 175 | /* copy the code to RAM */ |
| 176 | 1: |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 177 | move.l (%a1)+, (%a3)+ |
| 178 | cmp.l %a1,%a2 |
| 179 | bgt.s 1b |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 180 | |
| 181 | /* |
| 182 | * We are done. Do not return, instead branch to second part of board |
| 183 | * initialization, now running from RAM. |
| 184 | */ |
| 185 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 186 | add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 187 | jmp (%a1) |
| 188 | |
| 189 | in_ram: |
| 190 | |
| 191 | clear_bss: |
| 192 | /* |
| 193 | * Now clear BSS segment |
| 194 | */ |
| 195 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 197 | move.l %a0, %d1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 198 | add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 199 | 6: |
| 200 | clr.l (%a1)+ |
| 201 | cmp.l %a1,%d1 |
| 202 | bgt.s 6b |
| 203 | |
| 204 | /* |
| 205 | * fix got table in RAM |
| 206 | */ |
| 207 | move.l %a0, %a1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 208 | add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 209 | move.l %a1,%a5 /* * fix got pointer register a5 */ |
| 210 | |
| 211 | move.l %a0, %a2 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 212 | add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 213 | |
| 214 | 7: |
| 215 | move.l (%a1),%d1 |
| 216 | sub.l #_start,%d1 |
| 217 | add.l %a0,%d1 |
| 218 | move.l %d1,(%a1)+ |
| 219 | cmp.l %a2, %a1 |
| 220 | bne 7b |
| 221 | |
| 222 | /* calculate relative jump to board_init_r in ram */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 223 | move.l %a0, %a1 |
| 224 | add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 225 | |
| 226 | /* set parameters for board_init_r */ |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 227 | move.l %a0,-(%sp) /* dest_addr */ |
| 228 | move.l %d0,-(%sp) /* gd */ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 229 | jsr (%a1) |
| 230 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 231 | /******************************************************************************/ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 232 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 233 | /* exception code */ |
| 234 | .globl _fault |
| 235 | _fault: |
| 236 | bra _fault |
| 237 | |
| 238 | .globl _exc_handler |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 239 | _exc_handler: |
| 240 | SAVE_ALL |
| 241 | movel %sp,%sp@- |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 242 | bsr exc_handler |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 243 | addql #4,%sp |
| 244 | RESTORE_ALL |
| 245 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 246 | .globl _int_handler |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 247 | _int_handler: |
| 248 | SAVE_ALL |
| 249 | movel %sp,%sp@- |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 250 | bsr int_handler |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 251 | addql #4,%sp |
| 252 | RESTORE_ALL |
| 253 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 254 | /******************************************************************************/ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 255 | |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 256 | .globl version_string |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 257 | version_string: |
Angelo Dureghello | 5c928d0 | 2016-05-22 00:14:29 +0200 | [diff] [blame] | 258 | .ascii U_BOOT_VERSION_STRING, "\0" |
| 259 | .align 4 |